1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MipsISelLowering.h" 16 #include "InstPrinter/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsBaseInfo.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "MipsCCState.h" 20 #include "MipsInstrInfo.h" 21 #include "MipsMachineFunction.h" 22 #include "MipsRegisterInfo.h" 23 #include "MipsSubtarget.h" 24 #include "MipsTargetMachine.h" 25 #include "MipsTargetObjectFile.h" 26 #include "llvm/ADT/APFloat.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/SmallVector.h" 29 #include "llvm/ADT/Statistic.h" 30 #include "llvm/ADT/StringRef.h" 31 #include "llvm/ADT/StringSwitch.h" 32 #include "llvm/CodeGen/CallingConvLower.h" 33 #include "llvm/CodeGen/FunctionLoweringInfo.h" 34 #include "llvm/CodeGen/ISDOpcodes.h" 35 #include "llvm/CodeGen/MachineBasicBlock.h" 36 #include "llvm/CodeGen/MachineFrameInfo.h" 37 #include "llvm/CodeGen/MachineFunction.h" 38 #include "llvm/CodeGen/MachineInstr.h" 39 #include "llvm/CodeGen/MachineInstrBuilder.h" 40 #include "llvm/CodeGen/MachineJumpTableInfo.h" 41 #include "llvm/CodeGen/MachineMemOperand.h" 42 #include "llvm/CodeGen/MachineOperand.h" 43 #include "llvm/CodeGen/MachineRegisterInfo.h" 44 #include "llvm/CodeGen/RuntimeLibcalls.h" 45 #include "llvm/CodeGen/SelectionDAG.h" 46 #include "llvm/CodeGen/SelectionDAGNodes.h" 47 #include "llvm/CodeGen/TargetFrameLowering.h" 48 #include "llvm/CodeGen/TargetInstrInfo.h" 49 #include "llvm/CodeGen/TargetRegisterInfo.h" 50 #include "llvm/CodeGen/ValueTypes.h" 51 #include "llvm/IR/CallingConv.h" 52 #include "llvm/IR/Constants.h" 53 #include "llvm/IR/DataLayout.h" 54 #include "llvm/IR/DebugLoc.h" 55 #include "llvm/IR/DerivedTypes.h" 56 #include "llvm/IR/Function.h" 57 #include "llvm/IR/GlobalValue.h" 58 #include "llvm/IR/Type.h" 59 #include "llvm/IR/Value.h" 60 #include "llvm/MC/MCRegisterInfo.h" 61 #include "llvm/Support/Casting.h" 62 #include "llvm/Support/CodeGen.h" 63 #include "llvm/Support/CommandLine.h" 64 #include "llvm/Support/Compiler.h" 65 #include "llvm/Support/ErrorHandling.h" 66 #include "llvm/Support/MachineValueType.h" 67 #include "llvm/Support/MathExtras.h" 68 #include "llvm/Target/TargetMachine.h" 69 #include "llvm/Target/TargetOptions.h" 70 #include <algorithm> 71 #include <cassert> 72 #include <cctype> 73 #include <cstdint> 74 #include <deque> 75 #include <iterator> 76 #include <utility> 77 #include <vector> 78 79 using namespace llvm; 80 81 #define DEBUG_TYPE "mips-lower" 82 83 STATISTIC(NumTailCalls, "Number of tail calls"); 84 85 static cl::opt<bool> 86 LargeGOT("mxgot", cl::Hidden, 87 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 88 89 static cl::opt<bool> 90 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 91 cl::desc("MIPS: Don't trap on integer division by zero."), 92 cl::init(false)); 93 94 static const MCPhysReg Mips64DPRegs[8] = { 95 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 96 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 97 }; 98 99 // If I is a shifted mask, set the size (Size) and the first bit of the 100 // mask (Pos), and return true. 101 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 102 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 103 if (!isShiftedMask_64(I)) 104 return false; 105 106 Size = countPopulation(I); 107 Pos = countTrailingZeros(I); 108 return true; 109 } 110 111 // The MIPS MSA ABI passes vector arguments in the integer register set. 112 // The number of integer registers used is dependant on the ABI used. 113 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 114 CallingConv::ID CC, 115 EVT VT) const { 116 if (VT.isVector()) { 117 if (Subtarget.isABI_O32()) { 118 return MVT::i32; 119 } else { 120 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64; 121 } 122 } 123 return MipsTargetLowering::getRegisterType(Context, VT); 124 } 125 126 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 127 CallingConv::ID CC, 128 EVT VT) const { 129 if (VT.isVector()) 130 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)), 131 1U); 132 return MipsTargetLowering::getNumRegisters(Context, VT); 133 } 134 135 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 136 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 137 unsigned &NumIntermediates, MVT &RegisterVT) const { 138 // Break down vector types to either 2 i64s or 4 i32s. 139 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); 140 IntermediateVT = RegisterVT; 141 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() 142 ? VT.getVectorNumElements() 143 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); 144 145 return NumIntermediates; 146 } 147 148 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 149 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 150 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 151 } 152 153 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 154 SelectionDAG &DAG, 155 unsigned Flag) const { 156 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 157 } 158 159 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 160 SelectionDAG &DAG, 161 unsigned Flag) const { 162 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 163 } 164 165 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 166 SelectionDAG &DAG, 167 unsigned Flag) const { 168 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 169 } 170 171 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 172 SelectionDAG &DAG, 173 unsigned Flag) const { 174 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 175 } 176 177 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 178 SelectionDAG &DAG, 179 unsigned Flag) const { 180 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 181 N->getOffset(), Flag); 182 } 183 184 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 185 switch ((MipsISD::NodeType)Opcode) { 186 case MipsISD::FIRST_NUMBER: break; 187 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 188 case MipsISD::TailCall: return "MipsISD::TailCall"; 189 case MipsISD::Highest: return "MipsISD::Highest"; 190 case MipsISD::Higher: return "MipsISD::Higher"; 191 case MipsISD::Hi: return "MipsISD::Hi"; 192 case MipsISD::Lo: return "MipsISD::Lo"; 193 case MipsISD::GotHi: return "MipsISD::GotHi"; 194 case MipsISD::TlsHi: return "MipsISD::TlsHi"; 195 case MipsISD::GPRel: return "MipsISD::GPRel"; 196 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 197 case MipsISD::Ret: return "MipsISD::Ret"; 198 case MipsISD::ERet: return "MipsISD::ERet"; 199 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 200 case MipsISD::FMS: return "MipsISD::FMS"; 201 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 202 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 203 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 204 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 205 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 206 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 207 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 208 case MipsISD::MFHI: return "MipsISD::MFHI"; 209 case MipsISD::MFLO: return "MipsISD::MFLO"; 210 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 211 case MipsISD::Mult: return "MipsISD::Mult"; 212 case MipsISD::Multu: return "MipsISD::Multu"; 213 case MipsISD::MAdd: return "MipsISD::MAdd"; 214 case MipsISD::MAddu: return "MipsISD::MAddu"; 215 case MipsISD::MSub: return "MipsISD::MSub"; 216 case MipsISD::MSubu: return "MipsISD::MSubu"; 217 case MipsISD::DivRem: return "MipsISD::DivRem"; 218 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 219 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 220 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 221 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 222 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 223 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 224 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 225 case MipsISD::Sync: return "MipsISD::Sync"; 226 case MipsISD::Ext: return "MipsISD::Ext"; 227 case MipsISD::Ins: return "MipsISD::Ins"; 228 case MipsISD::CIns: return "MipsISD::CIns"; 229 case MipsISD::LWL: return "MipsISD::LWL"; 230 case MipsISD::LWR: return "MipsISD::LWR"; 231 case MipsISD::SWL: return "MipsISD::SWL"; 232 case MipsISD::SWR: return "MipsISD::SWR"; 233 case MipsISD::LDL: return "MipsISD::LDL"; 234 case MipsISD::LDR: return "MipsISD::LDR"; 235 case MipsISD::SDL: return "MipsISD::SDL"; 236 case MipsISD::SDR: return "MipsISD::SDR"; 237 case MipsISD::EXTP: return "MipsISD::EXTP"; 238 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 239 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 240 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 241 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 242 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 243 case MipsISD::SHILO: return "MipsISD::SHILO"; 244 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 245 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 246 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 247 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 248 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 249 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 250 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 251 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 252 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 253 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 254 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 255 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 256 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 257 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 258 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 259 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 260 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 261 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 262 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 263 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 264 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 265 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 266 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 267 case MipsISD::MULT: return "MipsISD::MULT"; 268 case MipsISD::MULTU: return "MipsISD::MULTU"; 269 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 270 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 271 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 272 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 273 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 274 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 275 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 276 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 277 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 278 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 279 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 280 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 281 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 282 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 283 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 284 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 285 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 286 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 287 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 288 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 289 case MipsISD::VNOR: return "MipsISD::VNOR"; 290 case MipsISD::VSHF: return "MipsISD::VSHF"; 291 case MipsISD::SHF: return "MipsISD::SHF"; 292 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 293 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 294 case MipsISD::ILVL: return "MipsISD::ILVL"; 295 case MipsISD::ILVR: return "MipsISD::ILVR"; 296 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 297 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 298 case MipsISD::INSVE: return "MipsISD::INSVE"; 299 } 300 return nullptr; 301 } 302 303 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 304 const MipsSubtarget &STI) 305 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 306 // Mips does not have i1 type, so use i32 for 307 // setcc operations results (slt, sgt, ...). 308 setBooleanContents(ZeroOrOneBooleanContent); 309 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 310 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 311 // does. Integer booleans still use 0 and 1. 312 if (Subtarget.hasMips32r6()) 313 setBooleanContents(ZeroOrOneBooleanContent, 314 ZeroOrNegativeOneBooleanContent); 315 316 // Load extented operations for i1 types must be promoted 317 for (MVT VT : MVT::integer_valuetypes()) { 318 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 319 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 320 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 321 } 322 323 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 324 // for f32, f16 325 for (MVT VT : MVT::fp_valuetypes()) { 326 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 327 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 328 } 329 330 // Set LoadExtAction for f16 vectors to Expand 331 for (MVT VT : MVT::fp_vector_valuetypes()) { 332 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 333 if (F16VT.isValid()) 334 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 335 } 336 337 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 338 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 339 340 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 341 342 // Used by legalize types to correctly generate the setcc result. 343 // Without this, every float setcc comes with a AND/OR with the result, 344 // we don't want this, since the fpcmp result goes to a flag register, 345 // which is used implicitly by brcond and select operations. 346 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 347 348 // Mips Custom Operations 349 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 350 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 351 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 352 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 353 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 354 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 355 setOperationAction(ISD::SELECT, MVT::f32, Custom); 356 setOperationAction(ISD::SELECT, MVT::f64, Custom); 357 setOperationAction(ISD::SELECT, MVT::i32, Custom); 358 setOperationAction(ISD::SETCC, MVT::f32, Custom); 359 setOperationAction(ISD::SETCC, MVT::f64, Custom); 360 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 361 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 362 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 363 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 364 365 if (Subtarget.isGP64bit()) { 366 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 367 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 368 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 369 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 370 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 371 setOperationAction(ISD::SELECT, MVT::i64, Custom); 372 setOperationAction(ISD::LOAD, MVT::i64, Custom); 373 setOperationAction(ISD::STORE, MVT::i64, Custom); 374 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 375 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 376 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 377 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 378 } 379 380 if (!Subtarget.isGP64bit()) { 381 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 382 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 383 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 384 } 385 386 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 387 if (Subtarget.isGP64bit()) 388 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 389 390 setOperationAction(ISD::SDIV, MVT::i32, Expand); 391 setOperationAction(ISD::SREM, MVT::i32, Expand); 392 setOperationAction(ISD::UDIV, MVT::i32, Expand); 393 setOperationAction(ISD::UREM, MVT::i32, Expand); 394 setOperationAction(ISD::SDIV, MVT::i64, Expand); 395 setOperationAction(ISD::SREM, MVT::i64, Expand); 396 setOperationAction(ISD::UDIV, MVT::i64, Expand); 397 setOperationAction(ISD::UREM, MVT::i64, Expand); 398 399 // Operations not directly supported by Mips. 400 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 401 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 402 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 403 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 404 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 405 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 406 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 407 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 408 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 409 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 410 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 411 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 412 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 413 if (Subtarget.hasCnMips()) { 414 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 415 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 416 } else { 417 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 418 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 419 } 420 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 421 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 422 setOperationAction(ISD::ROTL, MVT::i32, Expand); 423 setOperationAction(ISD::ROTL, MVT::i64, Expand); 424 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 425 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 426 427 if (!Subtarget.hasMips32r2()) 428 setOperationAction(ISD::ROTR, MVT::i32, Expand); 429 430 if (!Subtarget.hasMips64r2()) 431 setOperationAction(ISD::ROTR, MVT::i64, Expand); 432 433 setOperationAction(ISD::FSIN, MVT::f32, Expand); 434 setOperationAction(ISD::FSIN, MVT::f64, Expand); 435 setOperationAction(ISD::FCOS, MVT::f32, Expand); 436 setOperationAction(ISD::FCOS, MVT::f64, Expand); 437 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 438 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 439 setOperationAction(ISD::FPOW, MVT::f32, Expand); 440 setOperationAction(ISD::FPOW, MVT::f64, Expand); 441 setOperationAction(ISD::FLOG, MVT::f32, Expand); 442 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 443 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 444 setOperationAction(ISD::FEXP, MVT::f32, Expand); 445 setOperationAction(ISD::FMA, MVT::f32, Expand); 446 setOperationAction(ISD::FMA, MVT::f64, Expand); 447 setOperationAction(ISD::FREM, MVT::f32, Expand); 448 setOperationAction(ISD::FREM, MVT::f64, Expand); 449 450 // Lower f16 conversion operations into library calls 451 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 452 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 453 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 454 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 455 456 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 457 458 setOperationAction(ISD::VASTART, MVT::Other, Custom); 459 setOperationAction(ISD::VAARG, MVT::Other, Custom); 460 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 461 setOperationAction(ISD::VAEND, MVT::Other, Expand); 462 463 // Use the default for now 464 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 465 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 466 467 if (!Subtarget.isGP64bit()) { 468 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 469 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 470 } 471 472 if (!Subtarget.hasMips32r2()) { 473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 474 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 475 } 476 477 // MIPS16 lacks MIPS32's clz and clo instructions. 478 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 479 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 480 if (!Subtarget.hasMips64()) 481 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 482 483 if (!Subtarget.hasMips32r2()) 484 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 485 if (!Subtarget.hasMips64r2()) 486 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 487 488 if (Subtarget.isGP64bit()) { 489 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 490 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 491 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 492 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 493 } 494 495 setOperationAction(ISD::TRAP, MVT::Other, Legal); 496 497 setTargetDAGCombine(ISD::SDIVREM); 498 setTargetDAGCombine(ISD::UDIVREM); 499 setTargetDAGCombine(ISD::SELECT); 500 setTargetDAGCombine(ISD::AND); 501 setTargetDAGCombine(ISD::OR); 502 setTargetDAGCombine(ISD::ADD); 503 setTargetDAGCombine(ISD::SUB); 504 setTargetDAGCombine(ISD::AssertZext); 505 setTargetDAGCombine(ISD::SHL); 506 507 if (ABI.IsO32()) { 508 // These libcalls are not available in 32-bit. 509 setLibcallName(RTLIB::SHL_I128, nullptr); 510 setLibcallName(RTLIB::SRL_I128, nullptr); 511 setLibcallName(RTLIB::SRA_I128, nullptr); 512 } 513 514 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 515 516 // The arguments on the stack are defined in terms of 4-byte slots on O32 517 // and 8-byte slots on N32/N64. 518 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 519 520 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 521 522 MaxStoresPerMemcpy = 16; 523 524 isMicroMips = Subtarget.inMicroMipsMode(); 525 } 526 527 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 528 const MipsSubtarget &STI) { 529 if (STI.inMips16Mode()) 530 return createMips16TargetLowering(TM, STI); 531 532 return createMipsSETargetLowering(TM, STI); 533 } 534 535 // Create a fast isel object. 536 FastISel * 537 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 538 const TargetLibraryInfo *libInfo) const { 539 const MipsTargetMachine &TM = 540 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 541 542 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 543 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 544 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 545 !Subtarget.inMicroMipsMode(); 546 547 // Disable if either of the following is true: 548 // We do not generate PIC, the ABI is not O32, LargeGOT is being used. 549 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT) 550 UseFastISel = false; 551 552 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 553 } 554 555 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 556 EVT VT) const { 557 if (!VT.isVector()) 558 return MVT::i32; 559 return VT.changeVectorElementTypeToInteger(); 560 } 561 562 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 563 TargetLowering::DAGCombinerInfo &DCI, 564 const MipsSubtarget &Subtarget) { 565 if (DCI.isBeforeLegalizeOps()) 566 return SDValue(); 567 568 EVT Ty = N->getValueType(0); 569 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 570 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 571 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 572 MipsISD::DivRemU16; 573 SDLoc DL(N); 574 575 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 576 N->getOperand(0), N->getOperand(1)); 577 SDValue InChain = DAG.getEntryNode(); 578 SDValue InGlue = DivRem; 579 580 // insert MFLO 581 if (N->hasAnyUseOfValue(0)) { 582 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 583 InGlue); 584 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 585 InChain = CopyFromLo.getValue(1); 586 InGlue = CopyFromLo.getValue(2); 587 } 588 589 // insert MFHI 590 if (N->hasAnyUseOfValue(1)) { 591 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 592 HI, Ty, InGlue); 593 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 594 } 595 596 return SDValue(); 597 } 598 599 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 600 switch (CC) { 601 default: llvm_unreachable("Unknown fp condition code!"); 602 case ISD::SETEQ: 603 case ISD::SETOEQ: return Mips::FCOND_OEQ; 604 case ISD::SETUNE: return Mips::FCOND_UNE; 605 case ISD::SETLT: 606 case ISD::SETOLT: return Mips::FCOND_OLT; 607 case ISD::SETGT: 608 case ISD::SETOGT: return Mips::FCOND_OGT; 609 case ISD::SETLE: 610 case ISD::SETOLE: return Mips::FCOND_OLE; 611 case ISD::SETGE: 612 case ISD::SETOGE: return Mips::FCOND_OGE; 613 case ISD::SETULT: return Mips::FCOND_ULT; 614 case ISD::SETULE: return Mips::FCOND_ULE; 615 case ISD::SETUGT: return Mips::FCOND_UGT; 616 case ISD::SETUGE: return Mips::FCOND_UGE; 617 case ISD::SETUO: return Mips::FCOND_UN; 618 case ISD::SETO: return Mips::FCOND_OR; 619 case ISD::SETNE: 620 case ISD::SETONE: return Mips::FCOND_ONE; 621 case ISD::SETUEQ: return Mips::FCOND_UEQ; 622 } 623 } 624 625 /// This function returns true if the floating point conditional branches and 626 /// conditional moves which use condition code CC should be inverted. 627 static bool invertFPCondCodeUser(Mips::CondCode CC) { 628 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 629 return false; 630 631 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 632 "Illegal Condition Code"); 633 634 return true; 635 } 636 637 // Creates and returns an FPCmp node from a setcc node. 638 // Returns Op if setcc is not a floating point comparison. 639 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 640 // must be a SETCC node 641 if (Op.getOpcode() != ISD::SETCC) 642 return Op; 643 644 SDValue LHS = Op.getOperand(0); 645 646 if (!LHS.getValueType().isFloatingPoint()) 647 return Op; 648 649 SDValue RHS = Op.getOperand(1); 650 SDLoc DL(Op); 651 652 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 653 // node if necessary. 654 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 655 656 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 657 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 658 } 659 660 // Creates and returns a CMovFPT/F node. 661 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 662 SDValue False, const SDLoc &DL) { 663 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 664 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 665 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 666 667 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 668 True.getValueType(), True, FCC0, False, Cond); 669 } 670 671 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 672 TargetLowering::DAGCombinerInfo &DCI, 673 const MipsSubtarget &Subtarget) { 674 if (DCI.isBeforeLegalizeOps()) 675 return SDValue(); 676 677 SDValue SetCC = N->getOperand(0); 678 679 if ((SetCC.getOpcode() != ISD::SETCC) || 680 !SetCC.getOperand(0).getValueType().isInteger()) 681 return SDValue(); 682 683 SDValue False = N->getOperand(2); 684 EVT FalseTy = False.getValueType(); 685 686 if (!FalseTy.isInteger()) 687 return SDValue(); 688 689 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 690 691 // If the RHS (False) is 0, we swap the order of the operands 692 // of ISD::SELECT (obviously also inverting the condition) so that we can 693 // take advantage of conditional moves using the $0 register. 694 // Example: 695 // return (a != 0) ? x : 0; 696 // load $reg, x 697 // movz $reg, $0, a 698 if (!FalseC) 699 return SDValue(); 700 701 const SDLoc DL(N); 702 703 if (!FalseC->getZExtValue()) { 704 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 705 SDValue True = N->getOperand(1); 706 707 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 708 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 709 710 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 711 } 712 713 // If both operands are integer constants there's a possibility that we 714 // can do some interesting optimizations. 715 SDValue True = N->getOperand(1); 716 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 717 718 if (!TrueC || !True.getValueType().isInteger()) 719 return SDValue(); 720 721 // We'll also ignore MVT::i64 operands as this optimizations proves 722 // to be ineffective because of the required sign extensions as the result 723 // of a SETCC operator is always MVT::i32 for non-vector types. 724 if (True.getValueType() == MVT::i64) 725 return SDValue(); 726 727 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 728 729 // 1) (a < x) ? y : y-1 730 // slti $reg1, a, x 731 // addiu $reg2, $reg1, y-1 732 if (Diff == 1) 733 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 734 735 // 2) (a < x) ? y-1 : y 736 // slti $reg1, a, x 737 // xor $reg1, $reg1, 1 738 // addiu $reg2, $reg1, y-1 739 if (Diff == -1) { 740 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 741 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 742 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 743 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 744 } 745 746 // Could not optimize. 747 return SDValue(); 748 } 749 750 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 751 TargetLowering::DAGCombinerInfo &DCI, 752 const MipsSubtarget &Subtarget) { 753 if (DCI.isBeforeLegalizeOps()) 754 return SDValue(); 755 756 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 757 758 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 759 if (!FalseC || FalseC->getZExtValue()) 760 return SDValue(); 761 762 // Since RHS (False) is 0, we swap the order of the True/False operands 763 // (obviously also inverting the condition) so that we can 764 // take advantage of conditional moves using the $0 register. 765 // Example: 766 // return (a != 0) ? x : 0; 767 // load $reg, x 768 // movz $reg, $0, a 769 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 770 MipsISD::CMovFP_T; 771 772 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 773 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 774 ValueIfFalse, FCC, ValueIfTrue, Glue); 775 } 776 777 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 778 TargetLowering::DAGCombinerInfo &DCI, 779 const MipsSubtarget &Subtarget) { 780 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 781 return SDValue(); 782 783 SDValue FirstOperand = N->getOperand(0); 784 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 785 SDValue Mask = N->getOperand(1); 786 EVT ValTy = N->getValueType(0); 787 SDLoc DL(N); 788 789 uint64_t Pos = 0, SMPos, SMSize; 790 ConstantSDNode *CN; 791 SDValue NewOperand; 792 unsigned Opc; 793 794 // Op's second operand must be a shifted mask. 795 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 796 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 797 return SDValue(); 798 799 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 800 // Pattern match EXT. 801 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 802 // => ext $dst, $src, pos, size 803 804 // The second operand of the shift must be an immediate. 805 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 806 return SDValue(); 807 808 Pos = CN->getZExtValue(); 809 810 // Return if the shifted mask does not start at bit 0 or the sum of its size 811 // and Pos exceeds the word's size. 812 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 813 return SDValue(); 814 815 Opc = MipsISD::Ext; 816 NewOperand = FirstOperand.getOperand(0); 817 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 818 // Pattern match CINS. 819 // $dst = and (shl $src , pos), mask 820 // => cins $dst, $src, pos, size 821 // mask is a shifted mask with consecutive 1's, pos = shift amount, 822 // size = population count. 823 824 // The second operand of the shift must be an immediate. 825 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 826 return SDValue(); 827 828 Pos = CN->getZExtValue(); 829 830 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 831 Pos + SMSize > ValTy.getSizeInBits()) 832 return SDValue(); 833 834 NewOperand = FirstOperand.getOperand(0); 835 // SMSize is 'location' (position) in this case, not size. 836 SMSize--; 837 Opc = MipsISD::CIns; 838 } else { 839 // Pattern match EXT. 840 // $dst = and $src, (2**size - 1) , if size > 16 841 // => ext $dst, $src, pos, size , pos = 0 842 843 // If the mask is <= 0xffff, andi can be used instead. 844 if (CN->getZExtValue() <= 0xffff) 845 return SDValue(); 846 847 // Return if the mask doesn't start at position 0. 848 if (SMPos) 849 return SDValue(); 850 851 Opc = MipsISD::Ext; 852 NewOperand = FirstOperand; 853 } 854 return DAG.getNode(Opc, DL, ValTy, NewOperand, 855 DAG.getConstant(Pos, DL, MVT::i32), 856 DAG.getConstant(SMSize, DL, MVT::i32)); 857 } 858 859 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 860 TargetLowering::DAGCombinerInfo &DCI, 861 const MipsSubtarget &Subtarget) { 862 // Pattern match INS. 863 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 864 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 865 // => ins $dst, $src, size, pos, $src1 866 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 867 return SDValue(); 868 869 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 870 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 871 ConstantSDNode *CN, *CN1; 872 873 // See if Op's first operand matches (and $src1 , mask0). 874 if (And0.getOpcode() != ISD::AND) 875 return SDValue(); 876 877 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 878 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 879 return SDValue(); 880 881 // See if Op's second operand matches (and (shl $src, pos), mask1). 882 if (And1.getOpcode() == ISD::AND && 883 And1.getOperand(0).getOpcode() == ISD::SHL) { 884 885 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 886 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 887 return SDValue(); 888 889 // The shift masks must have the same position and size. 890 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 891 return SDValue(); 892 893 SDValue Shl = And1.getOperand(0); 894 895 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 896 return SDValue(); 897 898 unsigned Shamt = CN->getZExtValue(); 899 900 // Return if the shift amount and the first bit position of mask are not the 901 // same. 902 EVT ValTy = N->getValueType(0); 903 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 904 return SDValue(); 905 906 SDLoc DL(N); 907 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 908 DAG.getConstant(SMPos0, DL, MVT::i32), 909 DAG.getConstant(SMSize0, DL, MVT::i32), 910 And0.getOperand(0)); 911 } else { 912 // Pattern match DINS. 913 // $dst = or (and $src, mask0), mask1 914 // where mask0 = ((1 << SMSize0) -1) << SMPos0 915 // => dins $dst, $src, pos, size 916 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 917 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 918 (SMSize0 + SMPos0 <= 32))) { 919 // Check if AND instruction has constant as argument 920 bool isConstCase = And1.getOpcode() != ISD::AND; 921 if (And1.getOpcode() == ISD::AND) { 922 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 923 return SDValue(); 924 } else { 925 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 926 return SDValue(); 927 } 928 // Don't generate INS if constant OR operand doesn't fit into bits 929 // cleared by constant AND operand. 930 if (CN->getSExtValue() & CN1->getSExtValue()) 931 return SDValue(); 932 933 SDLoc DL(N); 934 EVT ValTy = N->getOperand(0)->getValueType(0); 935 SDValue Const1; 936 SDValue SrlX; 937 if (!isConstCase) { 938 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 939 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 940 } 941 return DAG.getNode( 942 MipsISD::Ins, DL, N->getValueType(0), 943 isConstCase 944 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 945 : SrlX, 946 DAG.getConstant(SMPos0, DL, MVT::i32), 947 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 948 : SMSize0, 949 DL, MVT::i32), 950 And0->getOperand(0)); 951 952 } 953 return SDValue(); 954 } 955 } 956 957 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 958 const MipsSubtarget &Subtarget) { 959 // ROOTNode must have a multiplication as an operand for the match to be 960 // successful. 961 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 962 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 963 return SDValue(); 964 965 // We don't handle vector types here. 966 if (ROOTNode->getValueType(0).isVector()) 967 return SDValue(); 968 969 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 970 // arithmetic. E.g. 971 // (add (mul a b) c) => 972 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 973 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 974 // or 975 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 976 // 977 // The overhead of setting up the Hi/Lo registers and reassembling the 978 // result makes this a dubious optimzation for MIPS64. The core of the 979 // problem is that Hi/Lo contain the upper and lower 32 bits of the 980 // operand and result. 981 // 982 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 983 // density than doing it naively, 5 for MIPS64. Additionally, using 984 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 985 // extended operands, not true 64 bit values. 986 // 987 // FIXME: For the moment, disable this completely for MIPS64. 988 if (Subtarget.hasMips64()) 989 return SDValue(); 990 991 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 992 ? ROOTNode->getOperand(0) 993 : ROOTNode->getOperand(1); 994 995 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 996 ? ROOTNode->getOperand(1) 997 : ROOTNode->getOperand(0); 998 999 // Transform this to a MADD only if the user of this node is the add. 1000 // If there are other users of the mul, this function returns here. 1001 if (!Mult.hasOneUse()) 1002 return SDValue(); 1003 1004 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 1005 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 1006 // of the multiply must have 32 or more sign bits, otherwise we cannot 1007 // perform this optimization. We have to check this here as we're performing 1008 // this optimization pre-legalization. 1009 SDValue MultLHS = Mult->getOperand(0); 1010 SDValue MultRHS = Mult->getOperand(1); 1011 1012 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1013 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1014 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1015 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1016 1017 if (!IsSigned && !IsUnsigned) 1018 return SDValue(); 1019 1020 // Initialize accumulator. 1021 SDLoc DL(ROOTNode); 1022 SDValue TopHalf; 1023 SDValue BottomHalf; 1024 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1025 CurDAG.getIntPtrConstant(0, DL)); 1026 1027 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1028 CurDAG.getIntPtrConstant(1, DL)); 1029 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1030 BottomHalf, 1031 TopHalf); 1032 1033 // Create MipsMAdd(u) / MipsMSub(u) node. 1034 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1035 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1036 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1037 SDValue MAddOps[3] = { 1038 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1039 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1040 EVT VTs[2] = {MVT::i32, MVT::i32}; 1041 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1042 1043 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1044 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1045 SDValue Combined = 1046 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1047 return Combined; 1048 } 1049 1050 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1051 TargetLowering::DAGCombinerInfo &DCI, 1052 const MipsSubtarget &Subtarget) { 1053 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1054 if (DCI.isBeforeLegalizeOps()) { 1055 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1056 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1057 return performMADD_MSUBCombine(N, DAG, Subtarget); 1058 1059 return SDValue(); 1060 } 1061 1062 return SDValue(); 1063 } 1064 1065 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1066 TargetLowering::DAGCombinerInfo &DCI, 1067 const MipsSubtarget &Subtarget) { 1068 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1069 if (DCI.isBeforeLegalizeOps()) { 1070 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1071 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1072 return performMADD_MSUBCombine(N, DAG, Subtarget); 1073 1074 return SDValue(); 1075 } 1076 1077 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1078 SDValue Add = N->getOperand(1); 1079 1080 if (Add.getOpcode() != ISD::ADD) 1081 return SDValue(); 1082 1083 SDValue Lo = Add.getOperand(1); 1084 1085 if ((Lo.getOpcode() != MipsISD::Lo) || 1086 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1087 return SDValue(); 1088 1089 EVT ValTy = N->getValueType(0); 1090 SDLoc DL(N); 1091 1092 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1093 Add.getOperand(0)); 1094 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1095 } 1096 1097 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1098 TargetLowering::DAGCombinerInfo &DCI, 1099 const MipsSubtarget &Subtarget) { 1100 // Pattern match CINS. 1101 // $dst = shl (and $src , imm), pos 1102 // => cins $dst, $src, pos, size 1103 1104 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1105 return SDValue(); 1106 1107 SDValue FirstOperand = N->getOperand(0); 1108 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1109 SDValue SecondOperand = N->getOperand(1); 1110 EVT ValTy = N->getValueType(0); 1111 SDLoc DL(N); 1112 1113 uint64_t Pos = 0, SMPos, SMSize; 1114 ConstantSDNode *CN; 1115 SDValue NewOperand; 1116 1117 // The second operand of the shift must be an immediate. 1118 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1119 return SDValue(); 1120 1121 Pos = CN->getZExtValue(); 1122 1123 if (Pos >= ValTy.getSizeInBits()) 1124 return SDValue(); 1125 1126 if (FirstOperandOpc != ISD::AND) 1127 return SDValue(); 1128 1129 // AND's second operand must be a shifted mask. 1130 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1131 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 1132 return SDValue(); 1133 1134 // Return if the shifted mask does not start at bit 0 or the sum of its size 1135 // and Pos exceeds the word's size. 1136 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1137 return SDValue(); 1138 1139 NewOperand = FirstOperand.getOperand(0); 1140 // SMSize is 'location' (position) in this case, not size. 1141 SMSize--; 1142 1143 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1144 DAG.getConstant(Pos, DL, MVT::i32), 1145 DAG.getConstant(SMSize, DL, MVT::i32)); 1146 } 1147 1148 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1149 const { 1150 SelectionDAG &DAG = DCI.DAG; 1151 unsigned Opc = N->getOpcode(); 1152 1153 switch (Opc) { 1154 default: break; 1155 case ISD::SDIVREM: 1156 case ISD::UDIVREM: 1157 return performDivRemCombine(N, DAG, DCI, Subtarget); 1158 case ISD::SELECT: 1159 return performSELECTCombine(N, DAG, DCI, Subtarget); 1160 case MipsISD::CMovFP_F: 1161 case MipsISD::CMovFP_T: 1162 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1163 case ISD::AND: 1164 return performANDCombine(N, DAG, DCI, Subtarget); 1165 case ISD::OR: 1166 return performORCombine(N, DAG, DCI, Subtarget); 1167 case ISD::ADD: 1168 return performADDCombine(N, DAG, DCI, Subtarget); 1169 case ISD::SHL: 1170 return performSHLCombine(N, DAG, DCI, Subtarget); 1171 case ISD::SUB: 1172 return performSUBCombine(N, DAG, DCI, Subtarget); 1173 } 1174 1175 return SDValue(); 1176 } 1177 1178 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1179 return Subtarget.hasMips32(); 1180 } 1181 1182 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1183 return Subtarget.hasMips32(); 1184 } 1185 1186 void 1187 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1188 SmallVectorImpl<SDValue> &Results, 1189 SelectionDAG &DAG) const { 1190 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1191 1192 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1193 Results.push_back(Res.getValue(I)); 1194 } 1195 1196 void 1197 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1198 SmallVectorImpl<SDValue> &Results, 1199 SelectionDAG &DAG) const { 1200 return LowerOperationWrapper(N, Results, DAG); 1201 } 1202 1203 SDValue MipsTargetLowering:: 1204 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1205 { 1206 switch (Op.getOpcode()) 1207 { 1208 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1209 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1210 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1211 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1212 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1213 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1214 case ISD::SELECT: return lowerSELECT(Op, DAG); 1215 case ISD::SETCC: return lowerSETCC(Op, DAG); 1216 case ISD::VASTART: return lowerVASTART(Op, DAG); 1217 case ISD::VAARG: return lowerVAARG(Op, DAG); 1218 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1219 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1220 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1221 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1222 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1223 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1224 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1225 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1226 case ISD::LOAD: return lowerLOAD(Op, DAG); 1227 case ISD::STORE: return lowerSTORE(Op, DAG); 1228 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1229 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1230 } 1231 return SDValue(); 1232 } 1233 1234 //===----------------------------------------------------------------------===// 1235 // Lower helper functions 1236 //===----------------------------------------------------------------------===// 1237 1238 // addLiveIn - This helper function adds the specified physical register to the 1239 // MachineFunction as a live in value. It also creates a corresponding 1240 // virtual register for it. 1241 static unsigned 1242 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1243 { 1244 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1245 MF.getRegInfo().addLiveIn(PReg, VReg); 1246 return VReg; 1247 } 1248 1249 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1250 MachineBasicBlock &MBB, 1251 const TargetInstrInfo &TII, 1252 bool Is64Bit, bool IsMicroMips) { 1253 if (NoZeroDivCheck) 1254 return &MBB; 1255 1256 // Insert instruction "teq $divisor_reg, $zero, 7". 1257 MachineBasicBlock::iterator I(MI); 1258 MachineInstrBuilder MIB; 1259 MachineOperand &Divisor = MI.getOperand(2); 1260 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1261 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1262 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1263 .addReg(Mips::ZERO) 1264 .addImm(7); 1265 1266 // Use the 32-bit sub-register if this is a 64-bit division. 1267 if (Is64Bit) 1268 MIB->getOperand(0).setSubReg(Mips::sub_32); 1269 1270 // Clear Divisor's kill flag. 1271 Divisor.setIsKill(false); 1272 1273 // We would normally delete the original instruction here but in this case 1274 // we only needed to inject an additional instruction rather than replace it. 1275 1276 return &MBB; 1277 } 1278 1279 MachineBasicBlock * 1280 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1281 MachineBasicBlock *BB) const { 1282 switch (MI.getOpcode()) { 1283 default: 1284 llvm_unreachable("Unexpected instr type to insert"); 1285 case Mips::ATOMIC_LOAD_ADD_I8: 1286 return emitAtomicBinaryPartword(MI, BB, 1); 1287 case Mips::ATOMIC_LOAD_ADD_I16: 1288 return emitAtomicBinaryPartword(MI, BB, 2); 1289 case Mips::ATOMIC_LOAD_ADD_I32: 1290 return emitAtomicBinary(MI, BB); 1291 case Mips::ATOMIC_LOAD_ADD_I64: 1292 return emitAtomicBinary(MI, BB); 1293 1294 case Mips::ATOMIC_LOAD_AND_I8: 1295 return emitAtomicBinaryPartword(MI, BB, 1); 1296 case Mips::ATOMIC_LOAD_AND_I16: 1297 return emitAtomicBinaryPartword(MI, BB, 2); 1298 case Mips::ATOMIC_LOAD_AND_I32: 1299 return emitAtomicBinary(MI, BB); 1300 case Mips::ATOMIC_LOAD_AND_I64: 1301 return emitAtomicBinary(MI, BB); 1302 1303 case Mips::ATOMIC_LOAD_OR_I8: 1304 return emitAtomicBinaryPartword(MI, BB, 1); 1305 case Mips::ATOMIC_LOAD_OR_I16: 1306 return emitAtomicBinaryPartword(MI, BB, 2); 1307 case Mips::ATOMIC_LOAD_OR_I32: 1308 return emitAtomicBinary(MI, BB); 1309 case Mips::ATOMIC_LOAD_OR_I64: 1310 return emitAtomicBinary(MI, BB); 1311 1312 case Mips::ATOMIC_LOAD_XOR_I8: 1313 return emitAtomicBinaryPartword(MI, BB, 1); 1314 case Mips::ATOMIC_LOAD_XOR_I16: 1315 return emitAtomicBinaryPartword(MI, BB, 2); 1316 case Mips::ATOMIC_LOAD_XOR_I32: 1317 return emitAtomicBinary(MI, BB); 1318 case Mips::ATOMIC_LOAD_XOR_I64: 1319 return emitAtomicBinary(MI, BB); 1320 1321 case Mips::ATOMIC_LOAD_NAND_I8: 1322 return emitAtomicBinaryPartword(MI, BB, 1); 1323 case Mips::ATOMIC_LOAD_NAND_I16: 1324 return emitAtomicBinaryPartword(MI, BB, 2); 1325 case Mips::ATOMIC_LOAD_NAND_I32: 1326 return emitAtomicBinary(MI, BB); 1327 case Mips::ATOMIC_LOAD_NAND_I64: 1328 return emitAtomicBinary(MI, BB); 1329 1330 case Mips::ATOMIC_LOAD_SUB_I8: 1331 return emitAtomicBinaryPartword(MI, BB, 1); 1332 case Mips::ATOMIC_LOAD_SUB_I16: 1333 return emitAtomicBinaryPartword(MI, BB, 2); 1334 case Mips::ATOMIC_LOAD_SUB_I32: 1335 return emitAtomicBinary(MI, BB); 1336 case Mips::ATOMIC_LOAD_SUB_I64: 1337 return emitAtomicBinary(MI, BB); 1338 1339 case Mips::ATOMIC_SWAP_I8: 1340 return emitAtomicBinaryPartword(MI, BB, 1); 1341 case Mips::ATOMIC_SWAP_I16: 1342 return emitAtomicBinaryPartword(MI, BB, 2); 1343 case Mips::ATOMIC_SWAP_I32: 1344 return emitAtomicBinary(MI, BB); 1345 case Mips::ATOMIC_SWAP_I64: 1346 return emitAtomicBinary(MI, BB); 1347 1348 case Mips::ATOMIC_CMP_SWAP_I8: 1349 return emitAtomicCmpSwapPartword(MI, BB, 1); 1350 case Mips::ATOMIC_CMP_SWAP_I16: 1351 return emitAtomicCmpSwapPartword(MI, BB, 2); 1352 case Mips::ATOMIC_CMP_SWAP_I32: 1353 return emitAtomicCmpSwap(MI, BB); 1354 case Mips::ATOMIC_CMP_SWAP_I64: 1355 return emitAtomicCmpSwap(MI, BB); 1356 case Mips::PseudoSDIV: 1357 case Mips::PseudoUDIV: 1358 case Mips::DIV: 1359 case Mips::DIVU: 1360 case Mips::MOD: 1361 case Mips::MODU: 1362 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1363 false); 1364 case Mips::SDIV_MM_Pseudo: 1365 case Mips::UDIV_MM_Pseudo: 1366 case Mips::SDIV_MM: 1367 case Mips::UDIV_MM: 1368 case Mips::DIV_MMR6: 1369 case Mips::DIVU_MMR6: 1370 case Mips::MOD_MMR6: 1371 case Mips::MODU_MMR6: 1372 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1373 case Mips::PseudoDSDIV: 1374 case Mips::PseudoDUDIV: 1375 case Mips::DDIV: 1376 case Mips::DDIVU: 1377 case Mips::DMOD: 1378 case Mips::DMODU: 1379 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1380 1381 case Mips::PseudoSELECT_I: 1382 case Mips::PseudoSELECT_I64: 1383 case Mips::PseudoSELECT_S: 1384 case Mips::PseudoSELECT_D32: 1385 case Mips::PseudoSELECT_D64: 1386 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1387 case Mips::PseudoSELECTFP_F_I: 1388 case Mips::PseudoSELECTFP_F_I64: 1389 case Mips::PseudoSELECTFP_F_S: 1390 case Mips::PseudoSELECTFP_F_D32: 1391 case Mips::PseudoSELECTFP_F_D64: 1392 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1393 case Mips::PseudoSELECTFP_T_I: 1394 case Mips::PseudoSELECTFP_T_I64: 1395 case Mips::PseudoSELECTFP_T_S: 1396 case Mips::PseudoSELECTFP_T_D32: 1397 case Mips::PseudoSELECTFP_T_D64: 1398 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1399 } 1400 } 1401 1402 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1403 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1404 MachineBasicBlock * 1405 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1406 MachineBasicBlock *BB) const { 1407 1408 MachineFunction *MF = BB->getParent(); 1409 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1410 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1411 DebugLoc DL = MI.getDebugLoc(); 1412 1413 unsigned AtomicOp; 1414 switch (MI.getOpcode()) { 1415 case Mips::ATOMIC_LOAD_ADD_I32: 1416 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA; 1417 break; 1418 case Mips::ATOMIC_LOAD_SUB_I32: 1419 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA; 1420 break; 1421 case Mips::ATOMIC_LOAD_AND_I32: 1422 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA; 1423 break; 1424 case Mips::ATOMIC_LOAD_OR_I32: 1425 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA; 1426 break; 1427 case Mips::ATOMIC_LOAD_XOR_I32: 1428 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA; 1429 break; 1430 case Mips::ATOMIC_LOAD_NAND_I32: 1431 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA; 1432 break; 1433 case Mips::ATOMIC_SWAP_I32: 1434 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA; 1435 break; 1436 case Mips::ATOMIC_LOAD_ADD_I64: 1437 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA; 1438 break; 1439 case Mips::ATOMIC_LOAD_SUB_I64: 1440 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA; 1441 break; 1442 case Mips::ATOMIC_LOAD_AND_I64: 1443 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA; 1444 break; 1445 case Mips::ATOMIC_LOAD_OR_I64: 1446 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA; 1447 break; 1448 case Mips::ATOMIC_LOAD_XOR_I64: 1449 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA; 1450 break; 1451 case Mips::ATOMIC_LOAD_NAND_I64: 1452 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA; 1453 break; 1454 case Mips::ATOMIC_SWAP_I64: 1455 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA; 1456 break; 1457 default: 1458 llvm_unreachable("Unknown pseudo atomic for replacement!"); 1459 } 1460 1461 unsigned OldVal = MI.getOperand(0).getReg(); 1462 unsigned Ptr = MI.getOperand(1).getReg(); 1463 unsigned Incr = MI.getOperand(2).getReg(); 1464 unsigned Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1465 1466 MachineBasicBlock::iterator II(MI); 1467 1468 // The scratch registers here with the EarlyClobber | Define | Implicit 1469 // flags is used to persuade the register allocator and the machine 1470 // verifier to accept the usage of this register. This has to be a real 1471 // register which has an UNDEF value but is dead after the instruction which 1472 // is unique among the registers chosen for the instruction. 1473 1474 // The EarlyClobber flag has the semantic properties that the operand it is 1475 // attached to is clobbered before the rest of the inputs are read. Hence it 1476 // must be unique among the operands to the instruction. 1477 // The Define flag is needed to coerce the machine verifier that an Undef 1478 // value isn't a problem. 1479 // The Dead flag is needed as the value in scratch isn't used by any other 1480 // instruction. Kill isn't used as Dead is more precise. 1481 // The implicit flag is here due to the interaction between the other flags 1482 // and the machine verifier. 1483 1484 // For correctness purpose, a new pseudo is introduced here. We need this 1485 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence 1486 // that is spread over >1 basic blocks. A register allocator which 1487 // introduces (or any codegen infact) a store, can violate the expectations 1488 // of the hardware. 1489 // 1490 // An atomic read-modify-write sequence starts with a linked load 1491 // instruction and ends with a store conditional instruction. The atomic 1492 // read-modify-write sequence fails if any of the following conditions 1493 // occur between the execution of ll and sc: 1494 // * A coherent store is completed by another process or coherent I/O 1495 // module into the block of synchronizable physical memory containing 1496 // the word. The size and alignment of the block is 1497 // implementation-dependent. 1498 // * A coherent store is executed between an LL and SC sequence on the 1499 // same processor to the block of synchornizable physical memory 1500 // containing the word. 1501 // 1502 1503 unsigned PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); 1504 unsigned IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); 1505 1506 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); 1507 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1508 1509 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1510 .addReg(OldVal, RegState::Define | RegState::EarlyClobber) 1511 .addReg(PtrCopy) 1512 .addReg(IncrCopy) 1513 .addReg(Scratch, RegState::Define | RegState::EarlyClobber | 1514 RegState::Implicit | RegState::Dead); 1515 1516 MI.eraseFromParent(); 1517 1518 return BB; 1519 } 1520 1521 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1522 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1523 unsigned SrcReg) const { 1524 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1525 const DebugLoc &DL = MI.getDebugLoc(); 1526 1527 if (Subtarget.hasMips32r2() && Size == 1) { 1528 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1529 return BB; 1530 } 1531 1532 if (Subtarget.hasMips32r2() && Size == 2) { 1533 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1534 return BB; 1535 } 1536 1537 MachineFunction *MF = BB->getParent(); 1538 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1539 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1540 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1541 1542 assert(Size < 32); 1543 int64_t ShiftImm = 32 - (Size * 8); 1544 1545 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1546 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1547 1548 return BB; 1549 } 1550 1551 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1552 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1553 assert((Size == 1 || Size == 2) && 1554 "Unsupported size for EmitAtomicBinaryPartial."); 1555 1556 MachineFunction *MF = BB->getParent(); 1557 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1558 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1559 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1560 const TargetRegisterClass *RCp = 1561 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1562 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1563 DebugLoc DL = MI.getDebugLoc(); 1564 1565 unsigned Dest = MI.getOperand(0).getReg(); 1566 unsigned Ptr = MI.getOperand(1).getReg(); 1567 unsigned Incr = MI.getOperand(2).getReg(); 1568 1569 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1570 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1571 unsigned Mask = RegInfo.createVirtualRegister(RC); 1572 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1573 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1574 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1575 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1576 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1577 unsigned Scratch = RegInfo.createVirtualRegister(RC); 1578 unsigned Scratch2 = RegInfo.createVirtualRegister(RC); 1579 unsigned Scratch3 = RegInfo.createVirtualRegister(RC); 1580 1581 unsigned AtomicOp = 0; 1582 switch (MI.getOpcode()) { 1583 case Mips::ATOMIC_LOAD_NAND_I8: 1584 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA; 1585 break; 1586 case Mips::ATOMIC_LOAD_NAND_I16: 1587 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA; 1588 break; 1589 case Mips::ATOMIC_SWAP_I8: 1590 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA; 1591 break; 1592 case Mips::ATOMIC_SWAP_I16: 1593 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA; 1594 break; 1595 case Mips::ATOMIC_LOAD_ADD_I8: 1596 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA; 1597 break; 1598 case Mips::ATOMIC_LOAD_ADD_I16: 1599 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA; 1600 break; 1601 case Mips::ATOMIC_LOAD_SUB_I8: 1602 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA; 1603 break; 1604 case Mips::ATOMIC_LOAD_SUB_I16: 1605 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA; 1606 break; 1607 case Mips::ATOMIC_LOAD_AND_I8: 1608 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA; 1609 break; 1610 case Mips::ATOMIC_LOAD_AND_I16: 1611 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA; 1612 break; 1613 case Mips::ATOMIC_LOAD_OR_I8: 1614 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA; 1615 break; 1616 case Mips::ATOMIC_LOAD_OR_I16: 1617 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA; 1618 break; 1619 case Mips::ATOMIC_LOAD_XOR_I8: 1620 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA; 1621 break; 1622 case Mips::ATOMIC_LOAD_XOR_I16: 1623 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA; 1624 break; 1625 default: 1626 llvm_unreachable("Unknown subword atomic pseudo for expansion!"); 1627 } 1628 1629 // insert new blocks after the current block 1630 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1631 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1632 MachineFunction::iterator It = ++BB->getIterator(); 1633 MF->insert(It, exitMBB); 1634 1635 // Transfer the remainder of BB and its successor edges to exitMBB. 1636 exitMBB->splice(exitMBB->begin(), BB, 1637 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1638 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1639 1640 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1641 1642 // thisMBB: 1643 // addiu masklsb2,$0,-4 # 0xfffffffc 1644 // and alignedaddr,ptr,masklsb2 1645 // andi ptrlsb2,ptr,3 1646 // sll shiftamt,ptrlsb2,3 1647 // ori maskupper,$0,255 # 0xff 1648 // sll mask,maskupper,shiftamt 1649 // nor mask2,$0,mask 1650 // sll incr2,incr,shiftamt 1651 1652 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1653 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1654 .addReg(ABI.GetNullPtr()).addImm(-4); 1655 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1656 .addReg(Ptr).addReg(MaskLSB2); 1657 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1658 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1659 if (Subtarget.isLittle()) { 1660 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1661 } else { 1662 unsigned Off = RegInfo.createVirtualRegister(RC); 1663 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1664 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1665 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1666 } 1667 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1668 .addReg(Mips::ZERO).addImm(MaskImm); 1669 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1670 .addReg(MaskUpper).addReg(ShiftAmt); 1671 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1672 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1673 1674 1675 // The purposes of the flags on the scratch registers is explained in 1676 // emitAtomicBinary. In summary, we need a scratch register which is going to 1677 // be undef, that is unique among registers chosen for the instruction. 1678 1679 BuildMI(BB, DL, TII->get(AtomicOp)) 1680 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1681 .addReg(AlignedAddr) 1682 .addReg(Incr2) 1683 .addReg(Mask) 1684 .addReg(Mask2) 1685 .addReg(ShiftAmt) 1686 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1687 RegState::Dead | RegState::Implicit) 1688 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1689 RegState::Dead | RegState::Implicit) 1690 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | 1691 RegState::Dead | RegState::Implicit); 1692 1693 MI.eraseFromParent(); // The instruction is gone now. 1694 1695 return exitMBB; 1696 } 1697 1698 // Lower atomic compare and swap to a pseudo instruction, taking care to 1699 // define a scratch register for the pseudo instruction's expansion. The 1700 // instruction is expanded after the register allocator as to prevent 1701 // the insertion of stores between the linked load and the store conditional. 1702 1703 MachineBasicBlock * 1704 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1705 MachineBasicBlock *BB) const { 1706 1707 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 || 1708 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) && 1709 "Unsupported atomic psseudo for EmitAtomicCmpSwap."); 1710 1711 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8; 1712 1713 MachineFunction *MF = BB->getParent(); 1714 MachineRegisterInfo &MRI = MF->getRegInfo(); 1715 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1716 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1717 DebugLoc DL = MI.getDebugLoc(); 1718 1719 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 1720 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA 1721 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA; 1722 unsigned Dest = MI.getOperand(0).getReg(); 1723 unsigned Ptr = MI.getOperand(1).getReg(); 1724 unsigned OldVal = MI.getOperand(2).getReg(); 1725 unsigned NewVal = MI.getOperand(3).getReg(); 1726 1727 unsigned Scratch = MRI.createVirtualRegister(RC); 1728 MachineBasicBlock::iterator II(MI); 1729 1730 // We need to create copies of the various registers and kill them at the 1731 // atomic pseudo. If the copies are not made, when the atomic is expanded 1732 // after fast register allocation, the spills will end up outside of the 1733 // blocks that their values are defined in, causing livein errors. 1734 1735 unsigned DestCopy = MRI.createVirtualRegister(MRI.getRegClass(Dest)); 1736 unsigned PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr)); 1737 unsigned OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal)); 1738 unsigned NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal)); 1739 1740 BuildMI(*BB, II, DL, TII->get(Mips::COPY), DestCopy).addReg(Dest); 1741 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1742 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal); 1743 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal); 1744 1745 // The purposes of the flags on the scratch registers is explained in 1746 // emitAtomicBinary. In summary, we need a scratch register which is going to 1747 // be undef, that is unique among registers chosen for the instruction. 1748 1749 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1750 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1751 .addReg(PtrCopy, RegState::Kill) 1752 .addReg(OldValCopy, RegState::Kill) 1753 .addReg(NewValCopy, RegState::Kill) 1754 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1755 RegState::Dead | RegState::Implicit); 1756 1757 MI.eraseFromParent(); // The instruction is gone now. 1758 1759 return BB; 1760 } 1761 1762 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1763 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1764 assert((Size == 1 || Size == 2) && 1765 "Unsupported size for EmitAtomicCmpSwapPartial."); 1766 1767 MachineFunction *MF = BB->getParent(); 1768 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1769 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1770 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1771 const TargetRegisterClass *RCp = 1772 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1773 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1774 DebugLoc DL = MI.getDebugLoc(); 1775 1776 unsigned Dest = MI.getOperand(0).getReg(); 1777 unsigned Ptr = MI.getOperand(1).getReg(); 1778 unsigned CmpVal = MI.getOperand(2).getReg(); 1779 unsigned NewVal = MI.getOperand(3).getReg(); 1780 1781 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1782 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1783 unsigned Mask = RegInfo.createVirtualRegister(RC); 1784 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1785 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1786 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1787 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1788 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1789 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1790 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1791 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1792 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8 1793 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA 1794 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA; 1795 1796 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit 1797 // flags are used to coerce the register allocator and the machine verifier to 1798 // accept the usage of these registers. 1799 // The EarlyClobber flag has the semantic properties that the operand it is 1800 // attached to is clobbered before the rest of the inputs are read. Hence it 1801 // must be unique among the operands to the instruction. 1802 // The Define flag is needed to coerce the machine verifier that an Undef 1803 // value isn't a problem. 1804 // The Dead flag is needed as the value in scratch isn't used by any other 1805 // instruction. Kill isn't used as Dead is more precise. 1806 unsigned Scratch = RegInfo.createVirtualRegister(RC); 1807 unsigned Scratch2 = RegInfo.createVirtualRegister(RC); 1808 1809 // insert new blocks after the current block 1810 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1811 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1812 MachineFunction::iterator It = ++BB->getIterator(); 1813 MF->insert(It, exitMBB); 1814 1815 // Transfer the remainder of BB and its successor edges to exitMBB. 1816 exitMBB->splice(exitMBB->begin(), BB, 1817 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1818 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1819 1820 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1821 1822 // thisMBB: 1823 // addiu masklsb2,$0,-4 # 0xfffffffc 1824 // and alignedaddr,ptr,masklsb2 1825 // andi ptrlsb2,ptr,3 1826 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1827 // sll shiftamt,ptrlsb2,3 1828 // ori maskupper,$0,255 # 0xff 1829 // sll mask,maskupper,shiftamt 1830 // nor mask2,$0,mask 1831 // andi maskedcmpval,cmpval,255 1832 // sll shiftedcmpval,maskedcmpval,shiftamt 1833 // andi maskednewval,newval,255 1834 // sll shiftednewval,maskednewval,shiftamt 1835 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1836 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1837 .addReg(ABI.GetNullPtr()).addImm(-4); 1838 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1839 .addReg(Ptr).addReg(MaskLSB2); 1840 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1841 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1842 if (Subtarget.isLittle()) { 1843 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1844 } else { 1845 unsigned Off = RegInfo.createVirtualRegister(RC); 1846 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1847 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1848 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1849 } 1850 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1851 .addReg(Mips::ZERO).addImm(MaskImm); 1852 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1853 .addReg(MaskUpper).addReg(ShiftAmt); 1854 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1855 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1856 .addReg(CmpVal).addImm(MaskImm); 1857 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1858 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1859 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1860 .addReg(NewVal).addImm(MaskImm); 1861 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1862 .addReg(MaskedNewVal).addReg(ShiftAmt); 1863 1864 // The purposes of the flags on the scratch registers are explained in 1865 // emitAtomicBinary. In summary, we need a scratch register which is going to 1866 // be undef, that is unique among the register chosen for the instruction. 1867 1868 BuildMI(BB, DL, TII->get(AtomicOp)) 1869 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1870 .addReg(AlignedAddr) 1871 .addReg(Mask) 1872 .addReg(ShiftedCmpVal) 1873 .addReg(Mask2) 1874 .addReg(ShiftedNewVal) 1875 .addReg(ShiftAmt) 1876 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1877 RegState::Dead | RegState::Implicit) 1878 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1879 RegState::Dead | RegState::Implicit); 1880 1881 MI.eraseFromParent(); // The instruction is gone now. 1882 1883 return exitMBB; 1884 } 1885 1886 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1887 // The first operand is the chain, the second is the condition, the third is 1888 // the block to branch to if the condition is true. 1889 SDValue Chain = Op.getOperand(0); 1890 SDValue Dest = Op.getOperand(2); 1891 SDLoc DL(Op); 1892 1893 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1894 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1895 1896 // Return if flag is not set by a floating point comparison. 1897 if (CondRes.getOpcode() != MipsISD::FPCmp) 1898 return Op; 1899 1900 SDValue CCNode = CondRes.getOperand(2); 1901 Mips::CondCode CC = 1902 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1903 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1904 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1905 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1906 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1907 FCC0, Dest, CondRes); 1908 } 1909 1910 SDValue MipsTargetLowering:: 1911 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1912 { 1913 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1914 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1915 1916 // Return if flag is not set by a floating point comparison. 1917 if (Cond.getOpcode() != MipsISD::FPCmp) 1918 return Op; 1919 1920 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1921 SDLoc(Op)); 1922 } 1923 1924 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1925 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1926 SDValue Cond = createFPCmp(DAG, Op); 1927 1928 assert(Cond.getOpcode() == MipsISD::FPCmp && 1929 "Floating point operand expected."); 1930 1931 SDLoc DL(Op); 1932 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1933 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1934 1935 return createCMovFP(DAG, Cond, True, False, DL); 1936 } 1937 1938 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1939 SelectionDAG &DAG) const { 1940 EVT Ty = Op.getValueType(); 1941 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1942 const GlobalValue *GV = N->getGlobal(); 1943 1944 if (!isPositionIndependent()) { 1945 const MipsTargetObjectFile *TLOF = 1946 static_cast<const MipsTargetObjectFile *>( 1947 getTargetMachine().getObjFileLowering()); 1948 const GlobalObject *GO = GV->getBaseObject(); 1949 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 1950 // %gp_rel relocation 1951 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 1952 1953 // %hi/%lo relocation 1954 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 1955 // %highest/%higher/%hi/%lo relocation 1956 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 1957 } 1958 1959 // Every other architecture would use shouldAssumeDSOLocal in here, but 1960 // mips is special. 1961 // * In PIC code mips requires got loads even for local statics! 1962 // * To save on got entries, for local statics the got entry contains the 1963 // page and an additional add instruction takes care of the low bits. 1964 // * It is legal to access a hidden symbol with a non hidden undefined, 1965 // so one cannot guarantee that all access to a hidden symbol will know 1966 // it is hidden. 1967 // * Mips linkers don't support creating a page and a full got entry for 1968 // the same symbol. 1969 // * Given all that, we have to use a full got entry for hidden symbols :-( 1970 if (GV->hasLocalLinkage()) 1971 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1972 1973 if (LargeGOT) 1974 return getAddrGlobalLargeGOT( 1975 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 1976 DAG.getEntryNode(), 1977 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1978 1979 return getAddrGlobal( 1980 N, SDLoc(N), Ty, DAG, 1981 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 1982 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1983 } 1984 1985 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1986 SelectionDAG &DAG) const { 1987 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1988 EVT Ty = Op.getValueType(); 1989 1990 if (!isPositionIndependent()) 1991 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 1992 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 1993 1994 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1995 } 1996 1997 SDValue MipsTargetLowering:: 1998 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1999 { 2000 // If the relocation model is PIC, use the General Dynamic TLS Model or 2001 // Local Dynamic TLS model, otherwise use the Initial Exec or 2002 // Local Exec TLS Model. 2003 2004 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2005 if (DAG.getTarget().useEmulatedTLS()) 2006 return LowerToTLSEmulatedModel(GA, DAG); 2007 2008 SDLoc DL(GA); 2009 const GlobalValue *GV = GA->getGlobal(); 2010 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2011 2012 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2013 2014 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2015 // General Dynamic and Local Dynamic TLS Model. 2016 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2017 : MipsII::MO_TLSGD; 2018 2019 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2020 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2021 getGlobalReg(DAG, PtrVT), TGA); 2022 unsigned PtrSize = PtrVT.getSizeInBits(); 2023 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2024 2025 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2026 2027 ArgListTy Args; 2028 ArgListEntry Entry; 2029 Entry.Node = Argument; 2030 Entry.Ty = PtrTy; 2031 Args.push_back(Entry); 2032 2033 TargetLowering::CallLoweringInfo CLI(DAG); 2034 CLI.setDebugLoc(DL) 2035 .setChain(DAG.getEntryNode()) 2036 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2037 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2038 2039 SDValue Ret = CallResult.first; 2040 2041 if (model != TLSModel::LocalDynamic) 2042 return Ret; 2043 2044 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2045 MipsII::MO_DTPREL_HI); 2046 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2047 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2048 MipsII::MO_DTPREL_LO); 2049 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2050 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2051 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2052 } 2053 2054 SDValue Offset; 2055 if (model == TLSModel::InitialExec) { 2056 // Initial Exec TLS Model 2057 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2058 MipsII::MO_GOTTPREL); 2059 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2060 TGA); 2061 Offset = 2062 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2063 } else { 2064 // Local Exec TLS Model 2065 assert(model == TLSModel::LocalExec); 2066 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2067 MipsII::MO_TPREL_HI); 2068 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2069 MipsII::MO_TPREL_LO); 2070 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2071 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2072 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2073 } 2074 2075 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2076 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2077 } 2078 2079 SDValue MipsTargetLowering:: 2080 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2081 { 2082 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2083 EVT Ty = Op.getValueType(); 2084 2085 if (!isPositionIndependent()) 2086 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2087 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2088 2089 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2090 } 2091 2092 SDValue MipsTargetLowering:: 2093 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2094 { 2095 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2096 EVT Ty = Op.getValueType(); 2097 2098 if (!isPositionIndependent()) { 2099 const MipsTargetObjectFile *TLOF = 2100 static_cast<const MipsTargetObjectFile *>( 2101 getTargetMachine().getObjFileLowering()); 2102 2103 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2104 getTargetMachine())) 2105 // %gp_rel relocation 2106 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2107 2108 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2109 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2110 } 2111 2112 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2113 } 2114 2115 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2116 MachineFunction &MF = DAG.getMachineFunction(); 2117 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2118 2119 SDLoc DL(Op); 2120 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2121 getPointerTy(MF.getDataLayout())); 2122 2123 // vastart just stores the address of the VarArgsFrameIndex slot into the 2124 // memory location argument. 2125 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2126 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2127 MachinePointerInfo(SV)); 2128 } 2129 2130 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2131 SDNode *Node = Op.getNode(); 2132 EVT VT = Node->getValueType(0); 2133 SDValue Chain = Node->getOperand(0); 2134 SDValue VAListPtr = Node->getOperand(1); 2135 unsigned Align = Node->getConstantOperandVal(3); 2136 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2137 SDLoc DL(Node); 2138 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2139 2140 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2141 VAListPtr, MachinePointerInfo(SV)); 2142 SDValue VAList = VAListLoad; 2143 2144 // Re-align the pointer if necessary. 2145 // It should only ever be necessary for 64-bit types on O32 since the minimum 2146 // argument alignment is the same as the maximum type alignment for N32/N64. 2147 // 2148 // FIXME: We currently align too often. The code generator doesn't notice 2149 // when the pointer is still aligned from the last va_arg (or pair of 2150 // va_args for the i64 on O32 case). 2151 if (Align > getMinStackArgumentAlignment()) { 2152 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2153 2154 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2155 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 2156 2157 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 2158 DAG.getConstant(-(int64_t)Align, DL, 2159 VAList.getValueType())); 2160 } 2161 2162 // Increment the pointer, VAList, to the next vaarg. 2163 auto &TD = DAG.getDataLayout(); 2164 unsigned ArgSizeInBytes = 2165 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2166 SDValue Tmp3 = 2167 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2168 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2169 DL, VAList.getValueType())); 2170 // Store the incremented VAList to the legalized pointer 2171 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2172 MachinePointerInfo(SV)); 2173 2174 // In big-endian mode we must adjust the pointer when the load size is smaller 2175 // than the argument slot size. We must also reduce the known alignment to 2176 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2177 // the correct half of the slot, and reduce the alignment from 8 (slot 2178 // alignment) down to 4 (type alignment). 2179 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2180 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2181 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2182 DAG.getIntPtrConstant(Adjustment, DL)); 2183 } 2184 // Load the actual argument out of the pointer VAList 2185 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2186 } 2187 2188 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2189 bool HasExtractInsert) { 2190 EVT TyX = Op.getOperand(0).getValueType(); 2191 EVT TyY = Op.getOperand(1).getValueType(); 2192 SDLoc DL(Op); 2193 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2194 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2195 SDValue Res; 2196 2197 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2198 // to i32. 2199 SDValue X = (TyX == MVT::f32) ? 2200 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2201 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2202 Const1); 2203 SDValue Y = (TyY == MVT::f32) ? 2204 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2205 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2206 Const1); 2207 2208 if (HasExtractInsert) { 2209 // ext E, Y, 31, 1 ; extract bit31 of Y 2210 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2211 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2212 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2213 } else { 2214 // sll SllX, X, 1 2215 // srl SrlX, SllX, 1 2216 // srl SrlY, Y, 31 2217 // sll SllY, SrlX, 31 2218 // or Or, SrlX, SllY 2219 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2220 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2221 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2222 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2223 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2224 } 2225 2226 if (TyX == MVT::f32) 2227 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2228 2229 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2230 Op.getOperand(0), 2231 DAG.getConstant(0, DL, MVT::i32)); 2232 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2233 } 2234 2235 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2236 bool HasExtractInsert) { 2237 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2238 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2239 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2240 SDLoc DL(Op); 2241 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2242 2243 // Bitcast to integer nodes. 2244 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2245 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2246 2247 if (HasExtractInsert) { 2248 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2249 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2250 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2251 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2252 2253 if (WidthX > WidthY) 2254 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2255 else if (WidthY > WidthX) 2256 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2257 2258 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2259 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2260 X); 2261 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2262 } 2263 2264 // (d)sll SllX, X, 1 2265 // (d)srl SrlX, SllX, 1 2266 // (d)srl SrlY, Y, width(Y)-1 2267 // (d)sll SllY, SrlX, width(Y)-1 2268 // or Or, SrlX, SllY 2269 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2270 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2271 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2272 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2273 2274 if (WidthX > WidthY) 2275 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2276 else if (WidthY > WidthX) 2277 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2278 2279 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2280 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2281 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2282 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2283 } 2284 2285 SDValue 2286 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2287 if (Subtarget.isGP64bit()) 2288 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2289 2290 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2291 } 2292 2293 SDValue MipsTargetLowering:: 2294 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2295 // check the depth 2296 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2297 "Frame address can only be determined for current frame."); 2298 2299 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2300 MFI.setFrameAddressIsTaken(true); 2301 EVT VT = Op.getValueType(); 2302 SDLoc DL(Op); 2303 SDValue FrameAddr = DAG.getCopyFromReg( 2304 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2305 return FrameAddr; 2306 } 2307 2308 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2309 SelectionDAG &DAG) const { 2310 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2311 return SDValue(); 2312 2313 // check the depth 2314 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2315 "Return address can be determined only for current frame."); 2316 2317 MachineFunction &MF = DAG.getMachineFunction(); 2318 MachineFrameInfo &MFI = MF.getFrameInfo(); 2319 MVT VT = Op.getSimpleValueType(); 2320 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2321 MFI.setReturnAddressIsTaken(true); 2322 2323 // Return RA, which contains the return address. Mark it an implicit live-in. 2324 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2325 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2326 } 2327 2328 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2329 // generated from __builtin_eh_return (offset, handler) 2330 // The effect of this is to adjust the stack pointer by "offset" 2331 // and then branch to "handler". 2332 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2333 const { 2334 MachineFunction &MF = DAG.getMachineFunction(); 2335 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2336 2337 MipsFI->setCallsEhReturn(); 2338 SDValue Chain = Op.getOperand(0); 2339 SDValue Offset = Op.getOperand(1); 2340 SDValue Handler = Op.getOperand(2); 2341 SDLoc DL(Op); 2342 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2343 2344 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2345 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2346 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2347 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2348 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2349 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2350 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2351 DAG.getRegister(OffsetReg, Ty), 2352 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2353 Chain.getValue(1)); 2354 } 2355 2356 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2357 SelectionDAG &DAG) const { 2358 // FIXME: Need pseudo-fence for 'singlethread' fences 2359 // FIXME: Set SType for weaker fences where supported/appropriate. 2360 unsigned SType = 0; 2361 SDLoc DL(Op); 2362 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2363 DAG.getConstant(SType, DL, MVT::i32)); 2364 } 2365 2366 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2367 SelectionDAG &DAG) const { 2368 SDLoc DL(Op); 2369 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2370 2371 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2372 SDValue Shamt = Op.getOperand(2); 2373 // if shamt < (VT.bits): 2374 // lo = (shl lo, shamt) 2375 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2376 // else: 2377 // lo = 0 2378 // hi = (shl lo, shamt[4:0]) 2379 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2380 DAG.getConstant(-1, DL, MVT::i32)); 2381 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2382 DAG.getConstant(1, DL, VT)); 2383 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2384 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2385 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2386 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2387 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2388 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2389 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2390 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2391 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2392 2393 SDValue Ops[2] = {Lo, Hi}; 2394 return DAG.getMergeValues(Ops, DL); 2395 } 2396 2397 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2398 bool IsSRA) const { 2399 SDLoc DL(Op); 2400 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2401 SDValue Shamt = Op.getOperand(2); 2402 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2403 2404 // if shamt < (VT.bits): 2405 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2406 // if isSRA: 2407 // hi = (sra hi, shamt) 2408 // else: 2409 // hi = (srl hi, shamt) 2410 // else: 2411 // if isSRA: 2412 // lo = (sra hi, shamt[4:0]) 2413 // hi = (sra hi, 31) 2414 // else: 2415 // lo = (srl hi, shamt[4:0]) 2416 // hi = 0 2417 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2418 DAG.getConstant(-1, DL, MVT::i32)); 2419 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2420 DAG.getConstant(1, DL, VT)); 2421 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2422 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2423 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2424 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2425 DL, VT, Hi, Shamt); 2426 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2427 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2428 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2429 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2430 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2431 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2432 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2433 2434 SDValue Ops[2] = {Lo, Hi}; 2435 return DAG.getMergeValues(Ops, DL); 2436 } 2437 2438 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2439 SDValue Chain, SDValue Src, unsigned Offset) { 2440 SDValue Ptr = LD->getBasePtr(); 2441 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2442 EVT BasePtrVT = Ptr.getValueType(); 2443 SDLoc DL(LD); 2444 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2445 2446 if (Offset) 2447 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2448 DAG.getConstant(Offset, DL, BasePtrVT)); 2449 2450 SDValue Ops[] = { Chain, Ptr, Src }; 2451 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2452 LD->getMemOperand()); 2453 } 2454 2455 // Expand an unaligned 32 or 64-bit integer load node. 2456 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2457 LoadSDNode *LD = cast<LoadSDNode>(Op); 2458 EVT MemVT = LD->getMemoryVT(); 2459 2460 if (Subtarget.systemSupportsUnalignedAccess()) 2461 return Op; 2462 2463 // Return if load is aligned or if MemVT is neither i32 nor i64. 2464 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2465 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2466 return SDValue(); 2467 2468 bool IsLittle = Subtarget.isLittle(); 2469 EVT VT = Op.getValueType(); 2470 ISD::LoadExtType ExtType = LD->getExtensionType(); 2471 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2472 2473 assert((VT == MVT::i32) || (VT == MVT::i64)); 2474 2475 // Expand 2476 // (set dst, (i64 (load baseptr))) 2477 // to 2478 // (set tmp, (ldl (add baseptr, 7), undef)) 2479 // (set dst, (ldr baseptr, tmp)) 2480 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2481 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2482 IsLittle ? 7 : 0); 2483 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2484 IsLittle ? 0 : 7); 2485 } 2486 2487 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2488 IsLittle ? 3 : 0); 2489 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2490 IsLittle ? 0 : 3); 2491 2492 // Expand 2493 // (set dst, (i32 (load baseptr))) or 2494 // (set dst, (i64 (sextload baseptr))) or 2495 // (set dst, (i64 (extload baseptr))) 2496 // to 2497 // (set tmp, (lwl (add baseptr, 3), undef)) 2498 // (set dst, (lwr baseptr, tmp)) 2499 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2500 (ExtType == ISD::EXTLOAD)) 2501 return LWR; 2502 2503 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2504 2505 // Expand 2506 // (set dst, (i64 (zextload baseptr))) 2507 // to 2508 // (set tmp0, (lwl (add baseptr, 3), undef)) 2509 // (set tmp1, (lwr baseptr, tmp0)) 2510 // (set tmp2, (shl tmp1, 32)) 2511 // (set dst, (srl tmp2, 32)) 2512 SDLoc DL(LD); 2513 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2514 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2515 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2516 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2517 return DAG.getMergeValues(Ops, DL); 2518 } 2519 2520 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2521 SDValue Chain, unsigned Offset) { 2522 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2523 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2524 SDLoc DL(SD); 2525 SDVTList VTList = DAG.getVTList(MVT::Other); 2526 2527 if (Offset) 2528 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2529 DAG.getConstant(Offset, DL, BasePtrVT)); 2530 2531 SDValue Ops[] = { Chain, Value, Ptr }; 2532 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2533 SD->getMemOperand()); 2534 } 2535 2536 // Expand an unaligned 32 or 64-bit integer store node. 2537 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2538 bool IsLittle) { 2539 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2540 EVT VT = Value.getValueType(); 2541 2542 // Expand 2543 // (store val, baseptr) or 2544 // (truncstore val, baseptr) 2545 // to 2546 // (swl val, (add baseptr, 3)) 2547 // (swr val, baseptr) 2548 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2549 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2550 IsLittle ? 3 : 0); 2551 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2552 } 2553 2554 assert(VT == MVT::i64); 2555 2556 // Expand 2557 // (store val, baseptr) 2558 // to 2559 // (sdl val, (add baseptr, 7)) 2560 // (sdr val, baseptr) 2561 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2562 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2563 } 2564 2565 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2566 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, 2567 bool SingleFloat) { 2568 SDValue Val = SD->getValue(); 2569 2570 if (Val.getOpcode() != ISD::FP_TO_SINT || 2571 (Val.getValueSizeInBits() > 32 && SingleFloat)) 2572 return SDValue(); 2573 2574 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2575 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2576 Val.getOperand(0)); 2577 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2578 SD->getPointerInfo(), SD->getAlignment(), 2579 SD->getMemOperand()->getFlags()); 2580 } 2581 2582 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2583 StoreSDNode *SD = cast<StoreSDNode>(Op); 2584 EVT MemVT = SD->getMemoryVT(); 2585 2586 // Lower unaligned integer stores. 2587 if (!Subtarget.systemSupportsUnalignedAccess() && 2588 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2589 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2590 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2591 2592 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat()); 2593 } 2594 2595 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2596 SelectionDAG &DAG) const { 2597 2598 // Return a fixed StackObject with offset 0 which points to the old stack 2599 // pointer. 2600 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2601 EVT ValTy = Op->getValueType(0); 2602 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2603 return DAG.getFrameIndex(FI, ValTy); 2604 } 2605 2606 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2607 SelectionDAG &DAG) const { 2608 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat()) 2609 return SDValue(); 2610 2611 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2612 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2613 Op.getOperand(0)); 2614 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2615 } 2616 2617 //===----------------------------------------------------------------------===// 2618 // Calling Convention Implementation 2619 //===----------------------------------------------------------------------===// 2620 2621 //===----------------------------------------------------------------------===// 2622 // TODO: Implement a generic logic using tblgen that can support this. 2623 // Mips O32 ABI rules: 2624 // --- 2625 // i32 - Passed in A0, A1, A2, A3 and stack 2626 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2627 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2628 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2629 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2630 // not used, it must be shadowed. If only A3 is available, shadow it and 2631 // go to stack. 2632 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2633 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2634 // with the remainder spilled to the stack. 2635 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2636 // spilling the remainder to the stack. 2637 // 2638 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2639 //===----------------------------------------------------------------------===// 2640 2641 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2642 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2643 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2644 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2645 State.getMachineFunction().getSubtarget()); 2646 2647 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2648 2649 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2650 2651 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2652 2653 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2654 2655 // Do not process byval args here. 2656 if (ArgFlags.isByVal()) 2657 return true; 2658 2659 // Promote i8 and i16 2660 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2661 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2662 LocVT = MVT::i32; 2663 if (ArgFlags.isSExt()) 2664 LocInfo = CCValAssign::SExtUpper; 2665 else if (ArgFlags.isZExt()) 2666 LocInfo = CCValAssign::ZExtUpper; 2667 else 2668 LocInfo = CCValAssign::AExtUpper; 2669 } 2670 } 2671 2672 // Promote i8 and i16 2673 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2674 LocVT = MVT::i32; 2675 if (ArgFlags.isSExt()) 2676 LocInfo = CCValAssign::SExt; 2677 else if (ArgFlags.isZExt()) 2678 LocInfo = CCValAssign::ZExt; 2679 else 2680 LocInfo = CCValAssign::AExt; 2681 } 2682 2683 unsigned Reg; 2684 2685 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2686 // is true: function is vararg, argument is 3rd or higher, there is previous 2687 // argument which is not f32 or f64. 2688 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2689 State.getFirstUnallocated(F32Regs) != ValNo; 2690 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2691 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2692 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2693 2694 // The MIPS vector ABI for floats passes them in a pair of registers 2695 if (ValVT == MVT::i32 && isVectorFloat) { 2696 // This is the start of an vector that was scalarized into an unknown number 2697 // of components. It doesn't matter how many there are. Allocate one of the 2698 // notional 8 byte aligned registers which map onto the argument stack, and 2699 // shadow the register lost to alignment requirements. 2700 if (ArgFlags.isSplit()) { 2701 Reg = State.AllocateReg(FloatVectorIntRegs); 2702 if (Reg == Mips::A2) 2703 State.AllocateReg(Mips::A1); 2704 else if (Reg == 0) 2705 State.AllocateReg(Mips::A3); 2706 } else { 2707 // If we're an intermediate component of the split, we can just attempt to 2708 // allocate a register directly. 2709 Reg = State.AllocateReg(IntRegs); 2710 } 2711 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2712 Reg = State.AllocateReg(IntRegs); 2713 // If this is the first part of an i64 arg, 2714 // the allocated register must be either A0 or A2. 2715 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2716 Reg = State.AllocateReg(IntRegs); 2717 LocVT = MVT::i32; 2718 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2719 // Allocate int register and shadow next int register. If first 2720 // available register is Mips::A1 or Mips::A3, shadow it too. 2721 Reg = State.AllocateReg(IntRegs); 2722 if (Reg == Mips::A1 || Reg == Mips::A3) 2723 Reg = State.AllocateReg(IntRegs); 2724 State.AllocateReg(IntRegs); 2725 LocVT = MVT::i32; 2726 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2727 // we are guaranteed to find an available float register 2728 if (ValVT == MVT::f32) { 2729 Reg = State.AllocateReg(F32Regs); 2730 // Shadow int register 2731 State.AllocateReg(IntRegs); 2732 } else { 2733 Reg = State.AllocateReg(F64Regs); 2734 // Shadow int registers 2735 unsigned Reg2 = State.AllocateReg(IntRegs); 2736 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2737 State.AllocateReg(IntRegs); 2738 State.AllocateReg(IntRegs); 2739 } 2740 } else 2741 llvm_unreachable("Cannot handle this ValVT."); 2742 2743 if (!Reg) { 2744 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2745 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2746 } else 2747 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2748 2749 return false; 2750 } 2751 2752 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2753 MVT LocVT, CCValAssign::LocInfo LocInfo, 2754 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2755 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2756 2757 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2758 } 2759 2760 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2761 MVT LocVT, CCValAssign::LocInfo LocInfo, 2762 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2763 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2764 2765 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2766 } 2767 2768 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2769 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2770 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2771 2772 #include "MipsGenCallingConv.inc" 2773 2774 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{ 2775 return CC_Mips; 2776 } 2777 2778 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{ 2779 return RetCC_Mips; 2780 } 2781 //===----------------------------------------------------------------------===// 2782 // Call Calling Convention Implementation 2783 //===----------------------------------------------------------------------===// 2784 2785 // Return next O32 integer argument register. 2786 static unsigned getNextIntArgReg(unsigned Reg) { 2787 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2788 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2789 } 2790 2791 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2792 SDValue Chain, SDValue Arg, 2793 const SDLoc &DL, bool IsTailCall, 2794 SelectionDAG &DAG) const { 2795 if (!IsTailCall) { 2796 SDValue PtrOff = 2797 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2798 DAG.getIntPtrConstant(Offset, DL)); 2799 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2800 } 2801 2802 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2803 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2804 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2805 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2806 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2807 } 2808 2809 void MipsTargetLowering:: 2810 getOpndList(SmallVectorImpl<SDValue> &Ops, 2811 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 2812 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2813 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2814 SDValue Chain) const { 2815 // Insert node "GP copy globalreg" before call to function. 2816 // 2817 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2818 // in PIC mode) allow symbols to be resolved via lazy binding. 2819 // The lazy binding stub requires GP to point to the GOT. 2820 // Note that we don't need GP to point to the GOT for indirect calls 2821 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2822 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2823 // used for the function (that is, Mips linker doesn't generate lazy binding 2824 // stub for a function whose address is taken in the program). 2825 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2826 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2827 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2828 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2829 } 2830 2831 // Build a sequence of copy-to-reg nodes chained together with token 2832 // chain and flag operands which copy the outgoing args into registers. 2833 // The InFlag in necessary since all emitted instructions must be 2834 // stuck together. 2835 SDValue InFlag; 2836 2837 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2838 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2839 RegsToPass[i].second, InFlag); 2840 InFlag = Chain.getValue(1); 2841 } 2842 2843 // Add argument registers to the end of the list so that they are 2844 // known live into the call. 2845 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2846 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2847 RegsToPass[i].second.getValueType())); 2848 2849 // Add a register mask operand representing the call-preserved registers. 2850 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2851 const uint32_t *Mask = 2852 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2853 assert(Mask && "Missing call preserved mask for calling convention"); 2854 if (Subtarget.inMips16HardFloat()) { 2855 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2856 StringRef Sym = G->getGlobal()->getName(); 2857 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2858 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2859 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2860 } 2861 } 2862 } 2863 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2864 2865 if (InFlag.getNode()) 2866 Ops.push_back(InFlag); 2867 } 2868 2869 /// LowerCall - functions arguments are copied from virtual regs to 2870 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2871 SDValue 2872 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2873 SmallVectorImpl<SDValue> &InVals) const { 2874 SelectionDAG &DAG = CLI.DAG; 2875 SDLoc DL = CLI.DL; 2876 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2877 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2878 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2879 SDValue Chain = CLI.Chain; 2880 SDValue Callee = CLI.Callee; 2881 bool &IsTailCall = CLI.IsTailCall; 2882 CallingConv::ID CallConv = CLI.CallConv; 2883 bool IsVarArg = CLI.IsVarArg; 2884 2885 MachineFunction &MF = DAG.getMachineFunction(); 2886 MachineFrameInfo &MFI = MF.getFrameInfo(); 2887 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2888 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2889 bool IsPIC = isPositionIndependent(); 2890 2891 // Analyze operands of the call, assigning locations to each operand. 2892 SmallVector<CCValAssign, 16> ArgLocs; 2893 MipsCCState CCInfo( 2894 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2895 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2896 2897 const ExternalSymbolSDNode *ES = 2898 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 2899 2900 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 2901 // is during the lowering of a call with a byval argument which produces 2902 // a call to memcpy. For the O32 case, this causes the caller to allocate 2903 // stack space for the reserved argument area for the callee, then recursively 2904 // again for the memcpy call. In the NEWABI case, this doesn't occur as those 2905 // ABIs mandate that the callee allocates the reserved argument area. We do 2906 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 2907 // 2908 // If the callee has a byval argument and memcpy is used, we are mandated 2909 // to already have produced a reserved argument area for the callee for O32. 2910 // Therefore, the reserved argument area can be reused for both calls. 2911 // 2912 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 2913 // present, as we have yet to hook that node onto the chain. 2914 // 2915 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 2916 // case. GCC does a similar trick, in that wherever possible, it calculates 2917 // the maximum out going argument area (including the reserved area), and 2918 // preallocates the stack space on entrance to the caller. 2919 // 2920 // FIXME: We should do the same for efficency and space. 2921 2922 // Note: The check on the calling convention below must match 2923 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 2924 bool MemcpyInByVal = ES && 2925 StringRef(ES->getSymbol()) == StringRef("memcpy") && 2926 CallConv != CallingConv::Fast && 2927 Chain.getOpcode() == ISD::CALLSEQ_START; 2928 2929 // Allocate the reserved argument area. It seems strange to do this from the 2930 // caller side but removing it breaks the frame size calculation. 2931 unsigned ReservedArgArea = 2932 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); 2933 CCInfo.AllocateStack(ReservedArgArea, 1); 2934 2935 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 2936 ES ? ES->getSymbol() : nullptr); 2937 2938 // Get a count of how many bytes are to be pushed on the stack. 2939 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2940 2941 // Check if it's really possible to do a tail call. Restrict it to functions 2942 // that are part of this compilation unit. 2943 bool InternalLinkage = false; 2944 if (IsTailCall) { 2945 IsTailCall = isEligibleForTailCallOptimization( 2946 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2947 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2948 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 2949 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 2950 G->getGlobal()->hasPrivateLinkage() || 2951 G->getGlobal()->hasHiddenVisibility() || 2952 G->getGlobal()->hasProtectedVisibility()); 2953 } 2954 } 2955 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) 2956 report_fatal_error("failed to perform tail call elimination on a call " 2957 "site marked musttail"); 2958 2959 if (IsTailCall) 2960 ++NumTailCalls; 2961 2962 // Chain is the output chain of the last Load/Store or CopyToReg node. 2963 // ByValChain is the output chain of the last Memcpy node created for copying 2964 // byval arguments to the stack. 2965 unsigned StackAlignment = TFL->getStackAlignment(); 2966 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 2967 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 2968 2969 if (!(IsTailCall || MemcpyInByVal)) 2970 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 2971 2972 SDValue StackPtr = 2973 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 2974 getPointerTy(DAG.getDataLayout())); 2975 2976 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 2977 SmallVector<SDValue, 8> MemOpChains; 2978 2979 CCInfo.rewindByValRegsInfo(); 2980 2981 // Walk the register/memloc assignments, inserting copies/loads. 2982 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2983 SDValue Arg = OutVals[i]; 2984 CCValAssign &VA = ArgLocs[i]; 2985 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2986 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2987 bool UseUpperBits = false; 2988 2989 // ByVal Arg. 2990 if (Flags.isByVal()) { 2991 unsigned FirstByValReg, LastByValReg; 2992 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2993 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2994 2995 assert(Flags.getByValSize() && 2996 "ByVal args of size 0 should have been ignored by front-end."); 2997 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2998 assert(!IsTailCall && 2999 "Do not tail-call optimize if there is a byval argument."); 3000 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3001 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3002 VA); 3003 CCInfo.nextInRegsParam(); 3004 continue; 3005 } 3006 3007 // Promote the value if needed. 3008 switch (VA.getLocInfo()) { 3009 default: 3010 llvm_unreachable("Unknown loc info!"); 3011 case CCValAssign::Full: 3012 if (VA.isRegLoc()) { 3013 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3014 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3015 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3016 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3017 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3018 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3019 Arg, DAG.getConstant(0, DL, MVT::i32)); 3020 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3021 Arg, DAG.getConstant(1, DL, MVT::i32)); 3022 if (!Subtarget.isLittle()) 3023 std::swap(Lo, Hi); 3024 unsigned LocRegLo = VA.getLocReg(); 3025 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 3026 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3027 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3028 continue; 3029 } 3030 } 3031 break; 3032 case CCValAssign::BCvt: 3033 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3034 break; 3035 case CCValAssign::SExtUpper: 3036 UseUpperBits = true; 3037 LLVM_FALLTHROUGH; 3038 case CCValAssign::SExt: 3039 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3040 break; 3041 case CCValAssign::ZExtUpper: 3042 UseUpperBits = true; 3043 LLVM_FALLTHROUGH; 3044 case CCValAssign::ZExt: 3045 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3046 break; 3047 case CCValAssign::AExtUpper: 3048 UseUpperBits = true; 3049 LLVM_FALLTHROUGH; 3050 case CCValAssign::AExt: 3051 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3052 break; 3053 } 3054 3055 if (UseUpperBits) { 3056 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3057 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3058 Arg = DAG.getNode( 3059 ISD::SHL, DL, VA.getLocVT(), Arg, 3060 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3061 } 3062 3063 // Arguments that can be passed on register must be kept at 3064 // RegsToPass vector 3065 if (VA.isRegLoc()) { 3066 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3067 continue; 3068 } 3069 3070 // Register can't get to this point... 3071 assert(VA.isMemLoc()); 3072 3073 // emit ISD::STORE whichs stores the 3074 // parameter value to a stack Location 3075 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3076 Chain, Arg, DL, IsTailCall, DAG)); 3077 } 3078 3079 // Transform all store nodes into one single node because all store 3080 // nodes are independent of each other. 3081 if (!MemOpChains.empty()) 3082 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3083 3084 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3085 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3086 // node so that legalize doesn't hack it. 3087 3088 EVT Ty = Callee.getValueType(); 3089 bool GlobalOrExternal = false, IsCallReloc = false; 3090 3091 // The long-calls feature is ignored in case of PIC. 3092 // While we do not support -mshared / -mno-shared properly, 3093 // ignore long-calls in case of -mabicalls too. 3094 if (!Subtarget.isABICalls() && !IsPIC) { 3095 // If the function should be called using "long call", 3096 // get its address into a register to prevent using 3097 // of the `jal` instruction for the direct call. 3098 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3099 if (Subtarget.useLongCalls()) 3100 Callee = Subtarget.hasSym32() 3101 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3102 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3103 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3104 bool UseLongCalls = Subtarget.useLongCalls(); 3105 // If the function has long-call/far/near attribute 3106 // it overrides command line switch pased to the backend. 3107 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3108 if (F->hasFnAttribute("long-call")) 3109 UseLongCalls = true; 3110 else if (F->hasFnAttribute("short-call")) 3111 UseLongCalls = false; 3112 } 3113 if (UseLongCalls) 3114 Callee = Subtarget.hasSym32() 3115 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3116 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3117 } 3118 } 3119 3120 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3121 if (IsPIC) { 3122 const GlobalValue *Val = G->getGlobal(); 3123 InternalLinkage = Val->hasInternalLinkage(); 3124 3125 if (InternalLinkage) 3126 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3127 else if (LargeGOT) { 3128 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3129 MipsII::MO_CALL_LO16, Chain, 3130 FuncInfo->callPtrInfo(Val)); 3131 IsCallReloc = true; 3132 } else { 3133 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3134 FuncInfo->callPtrInfo(Val)); 3135 IsCallReloc = true; 3136 } 3137 } else 3138 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3139 getPointerTy(DAG.getDataLayout()), 0, 3140 MipsII::MO_NO_FLAG); 3141 GlobalOrExternal = true; 3142 } 3143 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3144 const char *Sym = S->getSymbol(); 3145 3146 if (!IsPIC) // static 3147 Callee = DAG.getTargetExternalSymbol( 3148 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3149 else if (LargeGOT) { 3150 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3151 MipsII::MO_CALL_LO16, Chain, 3152 FuncInfo->callPtrInfo(Sym)); 3153 IsCallReloc = true; 3154 } else { // PIC 3155 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3156 FuncInfo->callPtrInfo(Sym)); 3157 IsCallReloc = true; 3158 } 3159 3160 GlobalOrExternal = true; 3161 } 3162 3163 SmallVector<SDValue, 8> Ops(1, Chain); 3164 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3165 3166 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3167 IsCallReloc, CLI, Callee, Chain); 3168 3169 if (IsTailCall) { 3170 MF.getFrameInfo().setHasTailCall(); 3171 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3172 } 3173 3174 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3175 SDValue InFlag = Chain.getValue(1); 3176 3177 // Create the CALLSEQ_END node in the case of where it is not a call to 3178 // memcpy. 3179 if (!(MemcpyInByVal)) { 3180 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3181 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3182 InFlag = Chain.getValue(1); 3183 } 3184 3185 // Handle result values, copying them out of physregs into vregs that we 3186 // return. 3187 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3188 InVals, CLI); 3189 } 3190 3191 /// LowerCallResult - Lower the result values of a call into the 3192 /// appropriate copies out of appropriate physical registers. 3193 SDValue MipsTargetLowering::LowerCallResult( 3194 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3195 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3196 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3197 TargetLowering::CallLoweringInfo &CLI) const { 3198 // Assign locations to each value returned by this call. 3199 SmallVector<CCValAssign, 16> RVLocs; 3200 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3201 *DAG.getContext()); 3202 3203 const ExternalSymbolSDNode *ES = 3204 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3205 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3206 ES ? ES->getSymbol() : nullptr); 3207 3208 // Copy all of the result registers out of their specified physreg. 3209 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3210 CCValAssign &VA = RVLocs[i]; 3211 assert(VA.isRegLoc() && "Can only return in registers!"); 3212 3213 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3214 RVLocs[i].getLocVT(), InFlag); 3215 Chain = Val.getValue(1); 3216 InFlag = Val.getValue(2); 3217 3218 if (VA.isUpperBitsInLoc()) { 3219 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3220 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3221 unsigned Shift = 3222 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3223 Val = DAG.getNode( 3224 Shift, DL, VA.getLocVT(), Val, 3225 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3226 } 3227 3228 switch (VA.getLocInfo()) { 3229 default: 3230 llvm_unreachable("Unknown loc info!"); 3231 case CCValAssign::Full: 3232 break; 3233 case CCValAssign::BCvt: 3234 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3235 break; 3236 case CCValAssign::AExt: 3237 case CCValAssign::AExtUpper: 3238 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3239 break; 3240 case CCValAssign::ZExt: 3241 case CCValAssign::ZExtUpper: 3242 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3243 DAG.getValueType(VA.getValVT())); 3244 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3245 break; 3246 case CCValAssign::SExt: 3247 case CCValAssign::SExtUpper: 3248 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3249 DAG.getValueType(VA.getValVT())); 3250 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3251 break; 3252 } 3253 3254 InVals.push_back(Val); 3255 } 3256 3257 return Chain; 3258 } 3259 3260 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3261 EVT ArgVT, const SDLoc &DL, 3262 SelectionDAG &DAG) { 3263 MVT LocVT = VA.getLocVT(); 3264 EVT ValVT = VA.getValVT(); 3265 3266 // Shift into the upper bits if necessary. 3267 switch (VA.getLocInfo()) { 3268 default: 3269 break; 3270 case CCValAssign::AExtUpper: 3271 case CCValAssign::SExtUpper: 3272 case CCValAssign::ZExtUpper: { 3273 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3274 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3275 unsigned Opcode = 3276 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3277 Val = DAG.getNode( 3278 Opcode, DL, VA.getLocVT(), Val, 3279 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3280 break; 3281 } 3282 } 3283 3284 // If this is an value smaller than the argument slot size (32-bit for O32, 3285 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3286 // size. Extract the value and insert any appropriate assertions regarding 3287 // sign/zero extension. 3288 switch (VA.getLocInfo()) { 3289 default: 3290 llvm_unreachable("Unknown loc info!"); 3291 case CCValAssign::Full: 3292 break; 3293 case CCValAssign::AExtUpper: 3294 case CCValAssign::AExt: 3295 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3296 break; 3297 case CCValAssign::SExtUpper: 3298 case CCValAssign::SExt: 3299 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3300 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3301 break; 3302 case CCValAssign::ZExtUpper: 3303 case CCValAssign::ZExt: 3304 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3305 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3306 break; 3307 case CCValAssign::BCvt: 3308 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3309 break; 3310 } 3311 3312 return Val; 3313 } 3314 3315 //===----------------------------------------------------------------------===// 3316 // Formal Arguments Calling Convention Implementation 3317 //===----------------------------------------------------------------------===// 3318 /// LowerFormalArguments - transform physical registers into virtual registers 3319 /// and generate load operations for arguments places on the stack. 3320 SDValue MipsTargetLowering::LowerFormalArguments( 3321 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3322 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3323 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3324 MachineFunction &MF = DAG.getMachineFunction(); 3325 MachineFrameInfo &MFI = MF.getFrameInfo(); 3326 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3327 3328 MipsFI->setVarArgsFrameIndex(0); 3329 3330 // Used with vargs to acumulate store chains. 3331 std::vector<SDValue> OutChains; 3332 3333 // Assign locations to all of the incoming arguments. 3334 SmallVector<CCValAssign, 16> ArgLocs; 3335 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3336 *DAG.getContext()); 3337 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3338 const Function &Func = DAG.getMachineFunction().getFunction(); 3339 Function::const_arg_iterator FuncArg = Func.arg_begin(); 3340 3341 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) 3342 report_fatal_error( 3343 "Functions with the interrupt attribute cannot have arguments!"); 3344 3345 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3346 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3347 CCInfo.getInRegsParamsCount() > 0); 3348 3349 unsigned CurArgIdx = 0; 3350 CCInfo.rewindByValRegsInfo(); 3351 3352 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3353 CCValAssign &VA = ArgLocs[i]; 3354 if (Ins[i].isOrigArg()) { 3355 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3356 CurArgIdx = Ins[i].getOrigArgIndex(); 3357 } 3358 EVT ValVT = VA.getValVT(); 3359 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3360 bool IsRegLoc = VA.isRegLoc(); 3361 3362 if (Flags.isByVal()) { 3363 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3364 unsigned FirstByValReg, LastByValReg; 3365 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3366 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3367 3368 assert(Flags.getByValSize() && 3369 "ByVal args of size 0 should have been ignored by front-end."); 3370 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3371 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3372 FirstByValReg, LastByValReg, VA, CCInfo); 3373 CCInfo.nextInRegsParam(); 3374 continue; 3375 } 3376 3377 // Arguments stored on registers 3378 if (IsRegLoc) { 3379 MVT RegVT = VA.getLocVT(); 3380 unsigned ArgReg = VA.getLocReg(); 3381 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3382 3383 // Transform the arguments stored on 3384 // physical registers into virtual ones 3385 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3386 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3387 3388 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3389 3390 // Handle floating point arguments passed in integer registers and 3391 // long double arguments passed in floating point registers. 3392 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3393 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3394 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3395 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3396 else if (ABI.IsO32() && RegVT == MVT::i32 && 3397 ValVT == MVT::f64) { 3398 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3399 getNextIntArgReg(ArgReg), RC); 3400 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3401 if (!Subtarget.isLittle()) 3402 std::swap(ArgValue, ArgValue2); 3403 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3404 ArgValue, ArgValue2); 3405 } 3406 3407 InVals.push_back(ArgValue); 3408 } else { // VA.isRegLoc() 3409 MVT LocVT = VA.getLocVT(); 3410 3411 if (ABI.IsO32()) { 3412 // We ought to be able to use LocVT directly but O32 sets it to i32 3413 // when allocating floating point values to integer registers. 3414 // This shouldn't influence how we load the value into registers unless 3415 // we are targeting softfloat. 3416 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3417 LocVT = VA.getValVT(); 3418 } 3419 3420 // sanity check 3421 assert(VA.isMemLoc()); 3422 3423 // The stack pointer offset is relative to the caller stack frame. 3424 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3425 VA.getLocMemOffset(), true); 3426 3427 // Create load nodes to retrieve arguments from the stack 3428 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3429 SDValue ArgValue = DAG.getLoad( 3430 LocVT, DL, Chain, FIN, 3431 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3432 OutChains.push_back(ArgValue.getValue(1)); 3433 3434 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3435 3436 InVals.push_back(ArgValue); 3437 } 3438 } 3439 3440 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3441 // The mips ABIs for returning structs by value requires that we copy 3442 // the sret argument into $v0 for the return. Save the argument into 3443 // a virtual register so that we can access it from the return points. 3444 if (Ins[i].Flags.isSRet()) { 3445 unsigned Reg = MipsFI->getSRetReturnReg(); 3446 if (!Reg) { 3447 Reg = MF.getRegInfo().createVirtualRegister( 3448 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3449 MipsFI->setSRetReturnReg(Reg); 3450 } 3451 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3452 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3453 break; 3454 } 3455 } 3456 3457 if (IsVarArg) 3458 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3459 3460 // All stores are grouped in one node to allow the matching between 3461 // the size of Ins and InVals. This only happens when on varg functions 3462 if (!OutChains.empty()) { 3463 OutChains.push_back(Chain); 3464 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3465 } 3466 3467 return Chain; 3468 } 3469 3470 //===----------------------------------------------------------------------===// 3471 // Return Value Calling Convention Implementation 3472 //===----------------------------------------------------------------------===// 3473 3474 bool 3475 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3476 MachineFunction &MF, bool IsVarArg, 3477 const SmallVectorImpl<ISD::OutputArg> &Outs, 3478 LLVMContext &Context) const { 3479 SmallVector<CCValAssign, 16> RVLocs; 3480 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3481 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3482 } 3483 3484 bool 3485 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3486 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) 3487 return true; 3488 3489 return IsSigned; 3490 } 3491 3492 SDValue 3493 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3494 const SDLoc &DL, 3495 SelectionDAG &DAG) const { 3496 MachineFunction &MF = DAG.getMachineFunction(); 3497 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3498 3499 MipsFI->setISR(); 3500 3501 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3502 } 3503 3504 SDValue 3505 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3506 bool IsVarArg, 3507 const SmallVectorImpl<ISD::OutputArg> &Outs, 3508 const SmallVectorImpl<SDValue> &OutVals, 3509 const SDLoc &DL, SelectionDAG &DAG) const { 3510 // CCValAssign - represent the assignment of 3511 // the return value to a location 3512 SmallVector<CCValAssign, 16> RVLocs; 3513 MachineFunction &MF = DAG.getMachineFunction(); 3514 3515 // CCState - Info about the registers and stack slot. 3516 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3517 3518 // Analyze return values. 3519 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3520 3521 SDValue Flag; 3522 SmallVector<SDValue, 4> RetOps(1, Chain); 3523 3524 // Copy the result values into the output registers. 3525 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3526 SDValue Val = OutVals[i]; 3527 CCValAssign &VA = RVLocs[i]; 3528 assert(VA.isRegLoc() && "Can only return in registers!"); 3529 bool UseUpperBits = false; 3530 3531 switch (VA.getLocInfo()) { 3532 default: 3533 llvm_unreachable("Unknown loc info!"); 3534 case CCValAssign::Full: 3535 break; 3536 case CCValAssign::BCvt: 3537 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3538 break; 3539 case CCValAssign::AExtUpper: 3540 UseUpperBits = true; 3541 LLVM_FALLTHROUGH; 3542 case CCValAssign::AExt: 3543 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3544 break; 3545 case CCValAssign::ZExtUpper: 3546 UseUpperBits = true; 3547 LLVM_FALLTHROUGH; 3548 case CCValAssign::ZExt: 3549 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3550 break; 3551 case CCValAssign::SExtUpper: 3552 UseUpperBits = true; 3553 LLVM_FALLTHROUGH; 3554 case CCValAssign::SExt: 3555 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3556 break; 3557 } 3558 3559 if (UseUpperBits) { 3560 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3561 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3562 Val = DAG.getNode( 3563 ISD::SHL, DL, VA.getLocVT(), Val, 3564 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3565 } 3566 3567 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3568 3569 // Guarantee that all emitted copies are stuck together with flags. 3570 Flag = Chain.getValue(1); 3571 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3572 } 3573 3574 // The mips ABIs for returning structs by value requires that we copy 3575 // the sret argument into $v0 for the return. We saved the argument into 3576 // a virtual register in the entry block, so now we copy the value out 3577 // and into $v0. 3578 if (MF.getFunction().hasStructRetAttr()) { 3579 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3580 unsigned Reg = MipsFI->getSRetReturnReg(); 3581 3582 if (!Reg) 3583 llvm_unreachable("sret virtual register not created in the entry block"); 3584 SDValue Val = 3585 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3586 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3587 3588 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3589 Flag = Chain.getValue(1); 3590 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3591 } 3592 3593 RetOps[0] = Chain; // Update chain. 3594 3595 // Add the flag if we have it. 3596 if (Flag.getNode()) 3597 RetOps.push_back(Flag); 3598 3599 // ISRs must use "eret". 3600 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 3601 return LowerInterruptReturn(RetOps, DL, DAG); 3602 3603 // Standard return on Mips is a "jr $ra" 3604 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3605 } 3606 3607 //===----------------------------------------------------------------------===// 3608 // Mips Inline Assembly Support 3609 //===----------------------------------------------------------------------===// 3610 3611 /// getConstraintType - Given a constraint letter, return the type of 3612 /// constraint it is for this target. 3613 MipsTargetLowering::ConstraintType 3614 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3615 // Mips specific constraints 3616 // GCC config/mips/constraints.md 3617 // 3618 // 'd' : An address register. Equivalent to r 3619 // unless generating MIPS16 code. 3620 // 'y' : Equivalent to r; retained for 3621 // backwards compatibility. 3622 // 'c' : A register suitable for use in an indirect 3623 // jump. This will always be $25 for -mabicalls. 3624 // 'l' : The lo register. 1 word storage. 3625 // 'x' : The hilo register pair. Double word storage. 3626 if (Constraint.size() == 1) { 3627 switch (Constraint[0]) { 3628 default : break; 3629 case 'd': 3630 case 'y': 3631 case 'f': 3632 case 'c': 3633 case 'l': 3634 case 'x': 3635 return C_RegisterClass; 3636 case 'R': 3637 return C_Memory; 3638 } 3639 } 3640 3641 if (Constraint == "ZC") 3642 return C_Memory; 3643 3644 return TargetLowering::getConstraintType(Constraint); 3645 } 3646 3647 /// Examine constraint type and operand type and determine a weight value. 3648 /// This object must already have been set up with the operand type 3649 /// and the current alternative constraint selected. 3650 TargetLowering::ConstraintWeight 3651 MipsTargetLowering::getSingleConstraintMatchWeight( 3652 AsmOperandInfo &info, const char *constraint) const { 3653 ConstraintWeight weight = CW_Invalid; 3654 Value *CallOperandVal = info.CallOperandVal; 3655 // If we don't have a value, we can't do a match, 3656 // but allow it at the lowest weight. 3657 if (!CallOperandVal) 3658 return CW_Default; 3659 Type *type = CallOperandVal->getType(); 3660 // Look at the constraint type. 3661 switch (*constraint) { 3662 default: 3663 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3664 break; 3665 case 'd': 3666 case 'y': 3667 if (type->isIntegerTy()) 3668 weight = CW_Register; 3669 break; 3670 case 'f': // FPU or MSA register 3671 if (Subtarget.hasMSA() && type->isVectorTy() && 3672 cast<VectorType>(type)->getBitWidth() == 128) 3673 weight = CW_Register; 3674 else if (type->isFloatTy()) 3675 weight = CW_Register; 3676 break; 3677 case 'c': // $25 for indirect jumps 3678 case 'l': // lo register 3679 case 'x': // hilo register pair 3680 if (type->isIntegerTy()) 3681 weight = CW_SpecificReg; 3682 break; 3683 case 'I': // signed 16 bit immediate 3684 case 'J': // integer zero 3685 case 'K': // unsigned 16 bit immediate 3686 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3687 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3688 case 'O': // signed 15 bit immediate (+- 16383) 3689 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3690 if (isa<ConstantInt>(CallOperandVal)) 3691 weight = CW_Constant; 3692 break; 3693 case 'R': 3694 weight = CW_Memory; 3695 break; 3696 } 3697 return weight; 3698 } 3699 3700 /// This is a helper function to parse a physical register string and split it 3701 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3702 /// that is returned indicates whether parsing was successful. The second flag 3703 /// is true if the numeric part exists. 3704 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3705 unsigned long long &Reg) { 3706 if (C.front() != '{' || C.back() != '}') 3707 return std::make_pair(false, false); 3708 3709 // Search for the first numeric character. 3710 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3711 I = std::find_if(B, E, isdigit); 3712 3713 Prefix = StringRef(B, I - B); 3714 3715 // The second flag is set to false if no numeric characters were found. 3716 if (I == E) 3717 return std::make_pair(true, false); 3718 3719 // Parse the numeric characters. 3720 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3721 true); 3722 } 3723 3724 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, 3725 ISD::NodeType) const { 3726 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32; 3727 EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32); 3728 return VT.bitsLT(MinVT) ? MinVT : VT; 3729 } 3730 3731 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3732 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3733 const TargetRegisterInfo *TRI = 3734 Subtarget.getRegisterInfo(); 3735 const TargetRegisterClass *RC; 3736 StringRef Prefix; 3737 unsigned long long Reg; 3738 3739 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3740 3741 if (!R.first) 3742 return std::make_pair(0U, nullptr); 3743 3744 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3745 // No numeric characters follow "hi" or "lo". 3746 if (R.second) 3747 return std::make_pair(0U, nullptr); 3748 3749 RC = TRI->getRegClass(Prefix == "hi" ? 3750 Mips::HI32RegClassID : Mips::LO32RegClassID); 3751 return std::make_pair(*(RC->begin()), RC); 3752 } else if (Prefix.startswith("$msa")) { 3753 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3754 3755 // No numeric characters follow the name. 3756 if (R.second) 3757 return std::make_pair(0U, nullptr); 3758 3759 Reg = StringSwitch<unsigned long long>(Prefix) 3760 .Case("$msair", Mips::MSAIR) 3761 .Case("$msacsr", Mips::MSACSR) 3762 .Case("$msaaccess", Mips::MSAAccess) 3763 .Case("$msasave", Mips::MSASave) 3764 .Case("$msamodify", Mips::MSAModify) 3765 .Case("$msarequest", Mips::MSARequest) 3766 .Case("$msamap", Mips::MSAMap) 3767 .Case("$msaunmap", Mips::MSAUnmap) 3768 .Default(0); 3769 3770 if (!Reg) 3771 return std::make_pair(0U, nullptr); 3772 3773 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3774 return std::make_pair(Reg, RC); 3775 } 3776 3777 if (!R.second) 3778 return std::make_pair(0U, nullptr); 3779 3780 if (Prefix == "$f") { // Parse $f0-$f31. 3781 // If the size of FP registers is 64-bit or Reg is an even number, select 3782 // the 64-bit register class. Otherwise, select the 32-bit register class. 3783 if (VT == MVT::Other) 3784 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3785 3786 RC = getRegClassFor(VT); 3787 3788 if (RC == &Mips::AFGR64RegClass) { 3789 assert(Reg % 2 == 0); 3790 Reg >>= 1; 3791 } 3792 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3793 RC = TRI->getRegClass(Mips::FCCRegClassID); 3794 else if (Prefix == "$w") { // Parse $w0-$w31. 3795 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3796 } else { // Parse $0-$31. 3797 assert(Prefix == "$"); 3798 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3799 } 3800 3801 assert(Reg < RC->getNumRegs()); 3802 return std::make_pair(*(RC->begin() + Reg), RC); 3803 } 3804 3805 /// Given a register class constraint, like 'r', if this corresponds directly 3806 /// to an LLVM register class, return a register of 0 and the register class 3807 /// pointer. 3808 std::pair<unsigned, const TargetRegisterClass *> 3809 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3810 StringRef Constraint, 3811 MVT VT) const { 3812 if (Constraint.size() == 1) { 3813 switch (Constraint[0]) { 3814 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3815 case 'y': // Same as 'r'. Exists for compatibility. 3816 case 'r': 3817 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3818 if (Subtarget.inMips16Mode()) 3819 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3820 return std::make_pair(0U, &Mips::GPR32RegClass); 3821 } 3822 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3823 return std::make_pair(0U, &Mips::GPR32RegClass); 3824 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3825 return std::make_pair(0U, &Mips::GPR64RegClass); 3826 // This will generate an error message 3827 return std::make_pair(0U, nullptr); 3828 case 'f': // FPU or MSA register 3829 if (VT == MVT::v16i8) 3830 return std::make_pair(0U, &Mips::MSA128BRegClass); 3831 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3832 return std::make_pair(0U, &Mips::MSA128HRegClass); 3833 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3834 return std::make_pair(0U, &Mips::MSA128WRegClass); 3835 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3836 return std::make_pair(0U, &Mips::MSA128DRegClass); 3837 else if (VT == MVT::f32) 3838 return std::make_pair(0U, &Mips::FGR32RegClass); 3839 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3840 if (Subtarget.isFP64bit()) 3841 return std::make_pair(0U, &Mips::FGR64RegClass); 3842 return std::make_pair(0U, &Mips::AFGR64RegClass); 3843 } 3844 break; 3845 case 'c': // register suitable for indirect jump 3846 if (VT == MVT::i32) 3847 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3848 if (VT == MVT::i64) 3849 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3850 // This will generate an error message 3851 return std::make_pair(0U, nullptr); 3852 case 'l': // use the `lo` register to store values 3853 // that are no bigger than a word 3854 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 3855 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3856 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3857 case 'x': // use the concatenated `hi` and `lo` registers 3858 // to store doubleword values 3859 // Fixme: Not triggering the use of both hi and low 3860 // This will generate an error message 3861 return std::make_pair(0U, nullptr); 3862 } 3863 } 3864 3865 std::pair<unsigned, const TargetRegisterClass *> R; 3866 R = parseRegForInlineAsmConstraint(Constraint, VT); 3867 3868 if (R.second) 3869 return R; 3870 3871 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3872 } 3873 3874 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3875 /// vector. If it is invalid, don't add anything to Ops. 3876 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3877 std::string &Constraint, 3878 std::vector<SDValue>&Ops, 3879 SelectionDAG &DAG) const { 3880 SDLoc DL(Op); 3881 SDValue Result; 3882 3883 // Only support length 1 constraints for now. 3884 if (Constraint.length() > 1) return; 3885 3886 char ConstraintLetter = Constraint[0]; 3887 switch (ConstraintLetter) { 3888 default: break; // This will fall through to the generic implementation 3889 case 'I': // Signed 16 bit constant 3890 // If this fails, the parent routine will give an error 3891 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3892 EVT Type = Op.getValueType(); 3893 int64_t Val = C->getSExtValue(); 3894 if (isInt<16>(Val)) { 3895 Result = DAG.getTargetConstant(Val, DL, Type); 3896 break; 3897 } 3898 } 3899 return; 3900 case 'J': // integer zero 3901 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3902 EVT Type = Op.getValueType(); 3903 int64_t Val = C->getZExtValue(); 3904 if (Val == 0) { 3905 Result = DAG.getTargetConstant(0, DL, Type); 3906 break; 3907 } 3908 } 3909 return; 3910 case 'K': // unsigned 16 bit immediate 3911 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3912 EVT Type = Op.getValueType(); 3913 uint64_t Val = (uint64_t)C->getZExtValue(); 3914 if (isUInt<16>(Val)) { 3915 Result = DAG.getTargetConstant(Val, DL, Type); 3916 break; 3917 } 3918 } 3919 return; 3920 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3921 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3922 EVT Type = Op.getValueType(); 3923 int64_t Val = C->getSExtValue(); 3924 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3925 Result = DAG.getTargetConstant(Val, DL, Type); 3926 break; 3927 } 3928 } 3929 return; 3930 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3931 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3932 EVT Type = Op.getValueType(); 3933 int64_t Val = C->getSExtValue(); 3934 if ((Val >= -65535) && (Val <= -1)) { 3935 Result = DAG.getTargetConstant(Val, DL, Type); 3936 break; 3937 } 3938 } 3939 return; 3940 case 'O': // signed 15 bit immediate 3941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3942 EVT Type = Op.getValueType(); 3943 int64_t Val = C->getSExtValue(); 3944 if ((isInt<15>(Val))) { 3945 Result = DAG.getTargetConstant(Val, DL, Type); 3946 break; 3947 } 3948 } 3949 return; 3950 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3952 EVT Type = Op.getValueType(); 3953 int64_t Val = C->getSExtValue(); 3954 if ((Val <= 65535) && (Val >= 1)) { 3955 Result = DAG.getTargetConstant(Val, DL, Type); 3956 break; 3957 } 3958 } 3959 return; 3960 } 3961 3962 if (Result.getNode()) { 3963 Ops.push_back(Result); 3964 return; 3965 } 3966 3967 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3968 } 3969 3970 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3971 const AddrMode &AM, Type *Ty, 3972 unsigned AS, Instruction *I) const { 3973 // No global is ever allowed as a base. 3974 if (AM.BaseGV) 3975 return false; 3976 3977 switch (AM.Scale) { 3978 case 0: // "r+i" or just "i", depending on HasBaseReg. 3979 break; 3980 case 1: 3981 if (!AM.HasBaseReg) // allow "r+i". 3982 break; 3983 return false; // disallow "r+r" or "r+r+i". 3984 default: 3985 return false; 3986 } 3987 3988 return true; 3989 } 3990 3991 bool 3992 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3993 // The Mips target isn't yet aware of offsets. 3994 return false; 3995 } 3996 3997 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3998 unsigned SrcAlign, 3999 bool IsMemset, bool ZeroMemset, 4000 bool MemcpyStrSrc, 4001 MachineFunction &MF) const { 4002 if (Subtarget.hasMips64()) 4003 return MVT::i64; 4004 4005 return MVT::i32; 4006 } 4007 4008 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 4009 if (VT != MVT::f32 && VT != MVT::f64) 4010 return false; 4011 if (Imm.isNegZero()) 4012 return false; 4013 return Imm.isZero(); 4014 } 4015 4016 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4017 4018 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4019 if (ABI.IsN64() && isPositionIndependent()) 4020 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4021 4022 return TargetLowering::getJumpTableEncoding(); 4023 } 4024 4025 bool MipsTargetLowering::useSoftFloat() const { 4026 return Subtarget.useSoftFloat(); 4027 } 4028 4029 void MipsTargetLowering::copyByValRegs( 4030 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4031 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4032 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4033 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4034 MipsCCState &State) const { 4035 MachineFunction &MF = DAG.getMachineFunction(); 4036 MachineFrameInfo &MFI = MF.getFrameInfo(); 4037 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4038 unsigned NumRegs = LastReg - FirstReg; 4039 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4040 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4041 int FrameObjOffset; 4042 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4043 4044 if (RegAreaSize) 4045 FrameObjOffset = 4046 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4047 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4048 else 4049 FrameObjOffset = VA.getLocMemOffset(); 4050 4051 // Create frame object. 4052 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4053 // Make the fixed object stored to mutable so that the load instructions 4054 // referencing it have their memory dependencies added. 4055 // Set the frame object as isAliased which clears the underlying objects 4056 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4057 // stores as dependencies for loads referencing this fixed object. 4058 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true); 4059 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4060 InVals.push_back(FIN); 4061 4062 if (!NumRegs) 4063 return; 4064 4065 // Copy arg registers. 4066 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4067 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4068 4069 for (unsigned I = 0; I < NumRegs; ++I) { 4070 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4071 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4072 unsigned Offset = I * GPRSizeInBytes; 4073 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4074 DAG.getConstant(Offset, DL, PtrTy)); 4075 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4076 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4077 OutChains.push_back(Store); 4078 } 4079 } 4080 4081 // Copy byVal arg to registers and stack. 4082 void MipsTargetLowering::passByValArg( 4083 SDValue Chain, const SDLoc &DL, 4084 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4085 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4086 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4087 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4088 const CCValAssign &VA) const { 4089 unsigned ByValSizeInBytes = Flags.getByValSize(); 4090 unsigned OffsetInBytes = 0; // From beginning of struct 4091 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4092 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 4093 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4094 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4095 unsigned NumRegs = LastReg - FirstReg; 4096 4097 if (NumRegs) { 4098 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4099 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4100 unsigned I = 0; 4101 4102 // Copy words to registers. 4103 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4104 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4105 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4106 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4107 MachinePointerInfo(), Alignment); 4108 MemOpChains.push_back(LoadVal.getValue(1)); 4109 unsigned ArgReg = ArgRegs[FirstReg + I]; 4110 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4111 } 4112 4113 // Return if the struct has been fully copied. 4114 if (ByValSizeInBytes == OffsetInBytes) 4115 return; 4116 4117 // Copy the remainder of the byval argument with sub-word loads and shifts. 4118 if (LeftoverBytes) { 4119 SDValue Val; 4120 4121 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4122 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4123 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4124 4125 if (RemainingSizeInBytes < LoadSizeInBytes) 4126 continue; 4127 4128 // Load subword. 4129 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4130 DAG.getConstant(OffsetInBytes, DL, 4131 PtrTy)); 4132 SDValue LoadVal = DAG.getExtLoad( 4133 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4134 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4135 MemOpChains.push_back(LoadVal.getValue(1)); 4136 4137 // Shift the loaded value. 4138 unsigned Shamt; 4139 4140 if (isLittle) 4141 Shamt = TotalBytesLoaded * 8; 4142 else 4143 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4144 4145 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4146 DAG.getConstant(Shamt, DL, MVT::i32)); 4147 4148 if (Val.getNode()) 4149 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4150 else 4151 Val = Shift; 4152 4153 OffsetInBytes += LoadSizeInBytes; 4154 TotalBytesLoaded += LoadSizeInBytes; 4155 Alignment = std::min(Alignment, LoadSizeInBytes); 4156 } 4157 4158 unsigned ArgReg = ArgRegs[FirstReg + I]; 4159 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4160 return; 4161 } 4162 } 4163 4164 // Copy remainder of byval arg to it with memcpy. 4165 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4166 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4167 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4168 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4169 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4170 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4171 DAG.getConstant(MemCpySize, DL, PtrTy), 4172 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 4173 /*isTailCall=*/false, 4174 MachinePointerInfo(), MachinePointerInfo()); 4175 MemOpChains.push_back(Chain); 4176 } 4177 4178 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4179 SDValue Chain, const SDLoc &DL, 4180 SelectionDAG &DAG, 4181 CCState &State) const { 4182 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4183 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4184 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4185 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4186 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4187 MachineFunction &MF = DAG.getMachineFunction(); 4188 MachineFrameInfo &MFI = MF.getFrameInfo(); 4189 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4190 4191 // Offset of the first variable argument from stack pointer. 4192 int VaArgOffset; 4193 4194 if (ArgRegs.size() == Idx) 4195 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4196 else { 4197 VaArgOffset = 4198 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4199 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4200 } 4201 4202 // Record the frame index of the first variable argument 4203 // which is a value necessary to VASTART. 4204 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4205 MipsFI->setVarArgsFrameIndex(FI); 4206 4207 // Copy the integer registers that have not been used for argument passing 4208 // to the argument register save area. For O32, the save area is allocated 4209 // in the caller's stack frame, while for N32/64, it is allocated in the 4210 // callee's stack frame. 4211 for (unsigned I = Idx; I < ArgRegs.size(); 4212 ++I, VaArgOffset += RegSizeInBytes) { 4213 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4214 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4215 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4216 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4217 SDValue Store = 4218 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4219 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4220 (Value *)nullptr); 4221 OutChains.push_back(Store); 4222 } 4223 } 4224 4225 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4226 unsigned Align) const { 4227 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4228 4229 assert(Size && "Byval argument's size shouldn't be 0."); 4230 4231 Align = std::min(Align, TFL->getStackAlignment()); 4232 4233 unsigned FirstReg = 0; 4234 unsigned NumRegs = 0; 4235 4236 if (State->getCallingConv() != CallingConv::Fast) { 4237 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4238 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4239 // FIXME: The O32 case actually describes no shadow registers. 4240 const MCPhysReg *ShadowRegs = 4241 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4242 4243 // We used to check the size as well but we can't do that anymore since 4244 // CCState::HandleByVal() rounds up the size after calling this function. 4245 assert(!(Align % RegSizeInBytes) && 4246 "Byval argument's alignment should be a multiple of" 4247 "RegSizeInBytes."); 4248 4249 FirstReg = State->getFirstUnallocated(IntArgRegs); 4250 4251 // If Align > RegSizeInBytes, the first arg register must be even. 4252 // FIXME: This condition happens to do the right thing but it's not the 4253 // right way to test it. We want to check that the stack frame offset 4254 // of the register is aligned. 4255 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 4256 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4257 ++FirstReg; 4258 } 4259 4260 // Mark the registers allocated. 4261 Size = alignTo(Size, RegSizeInBytes); 4262 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4263 Size -= RegSizeInBytes, ++I, ++NumRegs) 4264 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4265 } 4266 4267 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4268 } 4269 4270 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4271 MachineBasicBlock *BB, 4272 bool isFPCmp, 4273 unsigned Opc) const { 4274 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4275 "Subtarget already supports SELECT nodes with the use of" 4276 "conditional-move instructions."); 4277 4278 const TargetInstrInfo *TII = 4279 Subtarget.getInstrInfo(); 4280 DebugLoc DL = MI.getDebugLoc(); 4281 4282 // To "insert" a SELECT instruction, we actually have to insert the 4283 // diamond control-flow pattern. The incoming instruction knows the 4284 // destination vreg to set, the condition code register to branch on, the 4285 // true/false values to select between, and a branch opcode to use. 4286 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4287 MachineFunction::iterator It = ++BB->getIterator(); 4288 4289 // thisMBB: 4290 // ... 4291 // TrueVal = ... 4292 // setcc r1, r2, r3 4293 // bNE r1, r0, copy1MBB 4294 // fallthrough --> copy0MBB 4295 MachineBasicBlock *thisMBB = BB; 4296 MachineFunction *F = BB->getParent(); 4297 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4298 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4299 F->insert(It, copy0MBB); 4300 F->insert(It, sinkMBB); 4301 4302 // Transfer the remainder of BB and its successor edges to sinkMBB. 4303 sinkMBB->splice(sinkMBB->begin(), BB, 4304 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4305 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4306 4307 // Next, add the true and fallthrough blocks as its successors. 4308 BB->addSuccessor(copy0MBB); 4309 BB->addSuccessor(sinkMBB); 4310 4311 if (isFPCmp) { 4312 // bc1[tf] cc, sinkMBB 4313 BuildMI(BB, DL, TII->get(Opc)) 4314 .addReg(MI.getOperand(1).getReg()) 4315 .addMBB(sinkMBB); 4316 } else { 4317 // bne rs, $0, sinkMBB 4318 BuildMI(BB, DL, TII->get(Opc)) 4319 .addReg(MI.getOperand(1).getReg()) 4320 .addReg(Mips::ZERO) 4321 .addMBB(sinkMBB); 4322 } 4323 4324 // copy0MBB: 4325 // %FalseValue = ... 4326 // # fallthrough to sinkMBB 4327 BB = copy0MBB; 4328 4329 // Update machine-CFG edges 4330 BB->addSuccessor(sinkMBB); 4331 4332 // sinkMBB: 4333 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4334 // ... 4335 BB = sinkMBB; 4336 4337 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4338 .addReg(MI.getOperand(2).getReg()) 4339 .addMBB(thisMBB) 4340 .addReg(MI.getOperand(3).getReg()) 4341 .addMBB(copy0MBB); 4342 4343 MI.eraseFromParent(); // The pseudo instruction is gone now. 4344 4345 return BB; 4346 } 4347 4348 // FIXME? Maybe this could be a TableGen attribute on some registers and 4349 // this table could be generated automatically from RegInfo. 4350 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4351 SelectionDAG &DAG) const { 4352 // Named registers is expected to be fairly rare. For now, just support $28 4353 // since the linux kernel uses it. 4354 if (Subtarget.isGP64bit()) { 4355 unsigned Reg = StringSwitch<unsigned>(RegName) 4356 .Case("$28", Mips::GP_64) 4357 .Default(0); 4358 if (Reg) 4359 return Reg; 4360 } else { 4361 unsigned Reg = StringSwitch<unsigned>(RegName) 4362 .Case("$28", Mips::GP) 4363 .Default(0); 4364 if (Reg) 4365 return Reg; 4366 } 4367 report_fatal_error("Invalid register name global variable"); 4368 } 4369