1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MipsISelLowering.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MCTargetDesc/MipsBaseInfo.h" 17 #include "MipsCCState.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineJumpTableInfo.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/CodeGen/FunctionLoweringInfo.h" 31 #include "llvm/CodeGen/SelectionDAGISel.h" 32 #include "llvm/CodeGen/ValueTypes.h" 33 #include "llvm/IR/CallingConv.h" 34 #include "llvm/IR/DerivedTypes.h" 35 #include "llvm/IR/GlobalVariable.h" 36 #include "llvm/Support/CommandLine.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/ErrorHandling.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include <cctype> 41 42 using namespace llvm; 43 44 #define DEBUG_TYPE "mips-lower" 45 46 STATISTIC(NumTailCalls, "Number of tail calls"); 47 48 static cl::opt<bool> 49 LargeGOT("mxgot", cl::Hidden, 50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 51 52 static cl::opt<bool> 53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 54 cl::desc("MIPS: Don't trap on integer division by zero."), 55 cl::init(false)); 56 57 static const MCPhysReg Mips64DPRegs[8] = { 58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 60 }; 61 62 // If I is a shifted mask, set the size (Size) and the first bit of the 63 // mask (Pos), and return true. 64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 66 if (!isShiftedMask_64(I)) 67 return false; 68 69 Size = countPopulation(I); 70 Pos = countTrailingZeros(I); 71 return true; 72 } 73 74 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 75 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 76 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 77 } 78 79 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 80 SelectionDAG &DAG, 81 unsigned Flag) const { 82 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 83 } 84 85 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 86 SelectionDAG &DAG, 87 unsigned Flag) const { 88 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 89 } 90 91 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 92 SelectionDAG &DAG, 93 unsigned Flag) const { 94 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 95 } 96 97 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 98 SelectionDAG &DAG, 99 unsigned Flag) const { 100 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 101 } 102 103 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 104 SelectionDAG &DAG, 105 unsigned Flag) const { 106 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 107 N->getOffset(), Flag); 108 } 109 110 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 111 switch ((MipsISD::NodeType)Opcode) { 112 case MipsISD::FIRST_NUMBER: break; 113 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 114 case MipsISD::TailCall: return "MipsISD::TailCall"; 115 case MipsISD::Hi: return "MipsISD::Hi"; 116 case MipsISD::Lo: return "MipsISD::Lo"; 117 case MipsISD::GPRel: return "MipsISD::GPRel"; 118 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 119 case MipsISD::Ret: return "MipsISD::Ret"; 120 case MipsISD::ERet: return "MipsISD::ERet"; 121 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 122 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 123 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 124 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 125 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 126 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 127 case MipsISD::MFHI: return "MipsISD::MFHI"; 128 case MipsISD::MFLO: return "MipsISD::MFLO"; 129 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 130 case MipsISD::Mult: return "MipsISD::Mult"; 131 case MipsISD::Multu: return "MipsISD::Multu"; 132 case MipsISD::MAdd: return "MipsISD::MAdd"; 133 case MipsISD::MAddu: return "MipsISD::MAddu"; 134 case MipsISD::MSub: return "MipsISD::MSub"; 135 case MipsISD::MSubu: return "MipsISD::MSubu"; 136 case MipsISD::DivRem: return "MipsISD::DivRem"; 137 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 138 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 139 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 140 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 141 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 142 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 143 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 144 case MipsISD::Sync: return "MipsISD::Sync"; 145 case MipsISD::Ext: return "MipsISD::Ext"; 146 case MipsISD::Ins: return "MipsISD::Ins"; 147 case MipsISD::LWL: return "MipsISD::LWL"; 148 case MipsISD::LWR: return "MipsISD::LWR"; 149 case MipsISD::SWL: return "MipsISD::SWL"; 150 case MipsISD::SWR: return "MipsISD::SWR"; 151 case MipsISD::LDL: return "MipsISD::LDL"; 152 case MipsISD::LDR: return "MipsISD::LDR"; 153 case MipsISD::SDL: return "MipsISD::SDL"; 154 case MipsISD::SDR: return "MipsISD::SDR"; 155 case MipsISD::EXTP: return "MipsISD::EXTP"; 156 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 157 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 161 case MipsISD::SHILO: return "MipsISD::SHILO"; 162 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 163 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 164 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 165 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 166 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 167 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 168 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 169 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 170 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 171 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 172 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 173 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 174 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 175 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 176 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 177 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 178 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 179 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 180 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 181 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 182 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 183 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 184 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 185 case MipsISD::MULT: return "MipsISD::MULT"; 186 case MipsISD::MULTU: return "MipsISD::MULTU"; 187 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 188 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 189 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 190 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 191 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 192 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 193 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 194 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 195 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 196 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 197 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 198 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 199 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 200 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 201 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 202 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 203 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 204 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 205 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 206 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 207 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 208 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 209 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 210 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 211 case MipsISD::VNOR: return "MipsISD::VNOR"; 212 case MipsISD::VSHF: return "MipsISD::VSHF"; 213 case MipsISD::SHF: return "MipsISD::SHF"; 214 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 215 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 216 case MipsISD::ILVL: return "MipsISD::ILVL"; 217 case MipsISD::ILVR: return "MipsISD::ILVR"; 218 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 219 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 220 case MipsISD::INSVE: return "MipsISD::INSVE"; 221 } 222 return nullptr; 223 } 224 225 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 226 const MipsSubtarget &STI) 227 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 228 // Mips does not have i1 type, so use i32 for 229 // setcc operations results (slt, sgt, ...). 230 setBooleanContents(ZeroOrOneBooleanContent); 231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 232 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 233 // does. Integer booleans still use 0 and 1. 234 if (Subtarget.hasMips32r6()) 235 setBooleanContents(ZeroOrOneBooleanContent, 236 ZeroOrNegativeOneBooleanContent); 237 238 // Load extented operations for i1 types must be promoted 239 for (MVT VT : MVT::integer_valuetypes()) { 240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 241 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 242 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 243 } 244 245 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 246 // for f32, f16 247 for (MVT VT : MVT::fp_valuetypes()) { 248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 250 } 251 252 // Set LoadExtAction for f16 vectors to Expand 253 for (MVT VT : MVT::fp_vector_valuetypes()) { 254 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 255 if (F16VT.isValid()) 256 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 257 } 258 259 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 260 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 261 262 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 263 264 // Used by legalize types to correctly generate the setcc result. 265 // Without this, every float setcc comes with a AND/OR with the result, 266 // we don't want this, since the fpcmp result goes to a flag register, 267 // which is used implicitly by brcond and select operations. 268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 269 270 // Mips Custom Operations 271 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 272 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 273 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 274 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 275 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 276 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 277 setOperationAction(ISD::SELECT, MVT::f32, Custom); 278 setOperationAction(ISD::SELECT, MVT::f64, Custom); 279 setOperationAction(ISD::SELECT, MVT::i32, Custom); 280 setOperationAction(ISD::SETCC, MVT::f32, Custom); 281 setOperationAction(ISD::SETCC, MVT::f64, Custom); 282 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 284 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 285 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 286 287 if (Subtarget.isGP64bit()) { 288 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 289 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 290 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 291 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 292 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 293 setOperationAction(ISD::SELECT, MVT::i64, Custom); 294 setOperationAction(ISD::LOAD, MVT::i64, Custom); 295 setOperationAction(ISD::STORE, MVT::i64, Custom); 296 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 297 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 298 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 299 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 300 } 301 302 if (!Subtarget.isGP64bit()) { 303 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 304 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 305 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 306 } 307 308 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 309 if (Subtarget.isGP64bit()) 310 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 311 312 setOperationAction(ISD::SDIV, MVT::i32, Expand); 313 setOperationAction(ISD::SREM, MVT::i32, Expand); 314 setOperationAction(ISD::UDIV, MVT::i32, Expand); 315 setOperationAction(ISD::UREM, MVT::i32, Expand); 316 setOperationAction(ISD::SDIV, MVT::i64, Expand); 317 setOperationAction(ISD::SREM, MVT::i64, Expand); 318 setOperationAction(ISD::UDIV, MVT::i64, Expand); 319 setOperationAction(ISD::UREM, MVT::i64, Expand); 320 321 // Operations not directly supported by Mips. 322 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 323 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 324 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 325 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 326 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 327 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 328 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 329 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 330 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 331 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 335 if (Subtarget.hasCnMips()) { 336 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 337 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 338 } else { 339 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 340 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 341 } 342 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 343 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 344 setOperationAction(ISD::ROTL, MVT::i32, Expand); 345 setOperationAction(ISD::ROTL, MVT::i64, Expand); 346 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 348 349 if (!Subtarget.hasMips32r2()) 350 setOperationAction(ISD::ROTR, MVT::i32, Expand); 351 352 if (!Subtarget.hasMips64r2()) 353 setOperationAction(ISD::ROTR, MVT::i64, Expand); 354 355 setOperationAction(ISD::FSIN, MVT::f32, Expand); 356 setOperationAction(ISD::FSIN, MVT::f64, Expand); 357 setOperationAction(ISD::FCOS, MVT::f32, Expand); 358 setOperationAction(ISD::FCOS, MVT::f64, Expand); 359 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 360 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 361 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 362 setOperationAction(ISD::FPOW, MVT::f32, Expand); 363 setOperationAction(ISD::FPOW, MVT::f64, Expand); 364 setOperationAction(ISD::FLOG, MVT::f32, Expand); 365 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 366 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 367 setOperationAction(ISD::FEXP, MVT::f32, Expand); 368 setOperationAction(ISD::FMA, MVT::f32, Expand); 369 setOperationAction(ISD::FMA, MVT::f64, Expand); 370 setOperationAction(ISD::FREM, MVT::f32, Expand); 371 setOperationAction(ISD::FREM, MVT::f64, Expand); 372 373 // Lower f16 conversion operations into library calls 374 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 375 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 376 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 378 379 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 380 381 setOperationAction(ISD::VASTART, MVT::Other, Custom); 382 setOperationAction(ISD::VAARG, MVT::Other, Custom); 383 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 384 setOperationAction(ISD::VAEND, MVT::Other, Expand); 385 386 // Use the default for now 387 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 388 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 389 390 if (!Subtarget.isGP64bit()) { 391 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 392 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 393 } 394 395 396 if (!Subtarget.hasMips32r2()) { 397 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 398 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 399 } 400 401 // MIPS16 lacks MIPS32's clz and clo instructions. 402 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 403 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 404 if (!Subtarget.hasMips64()) 405 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 406 407 if (!Subtarget.hasMips32r2()) 408 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 409 if (!Subtarget.hasMips64r2()) 410 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 411 412 if (Subtarget.isGP64bit()) { 413 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 414 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 415 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 416 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 417 } 418 419 setOperationAction(ISD::TRAP, MVT::Other, Legal); 420 421 setTargetDAGCombine(ISD::SDIVREM); 422 setTargetDAGCombine(ISD::UDIVREM); 423 setTargetDAGCombine(ISD::SELECT); 424 setTargetDAGCombine(ISD::AND); 425 setTargetDAGCombine(ISD::OR); 426 setTargetDAGCombine(ISD::ADD); 427 setTargetDAGCombine(ISD::AssertZext); 428 429 if (ABI.IsO32()) { 430 // These libcalls are not available in 32-bit. 431 setLibcallName(RTLIB::SHL_I128, nullptr); 432 setLibcallName(RTLIB::SRL_I128, nullptr); 433 setLibcallName(RTLIB::SRA_I128, nullptr); 434 } 435 436 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 437 438 // The arguments on the stack are defined in terms of 4-byte slots on O32 439 // and 8-byte slots on N32/N64. 440 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 441 442 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 443 444 MaxStoresPerMemcpy = 16; 445 446 isMicroMips = Subtarget.inMicroMipsMode(); 447 } 448 449 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 450 const MipsSubtarget &STI) { 451 if (STI.inMips16Mode()) 452 return llvm::createMips16TargetLowering(TM, STI); 453 454 return llvm::createMipsSETargetLowering(TM, STI); 455 } 456 457 // Create a fast isel object. 458 FastISel * 459 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 460 const TargetLibraryInfo *libInfo) const { 461 const MipsTargetMachine &TM = 462 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 463 464 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 465 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 466 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 467 !Subtarget.inMicroMipsMode(); 468 469 // Disable if we don't generate PIC or the ABI isn't O32. 470 if (!TM.isPositionIndependent() || !TM.getABI().IsO32()) 471 UseFastISel = false; 472 473 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 474 } 475 476 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 477 EVT VT) const { 478 if (!VT.isVector()) 479 return MVT::i32; 480 return VT.changeVectorElementTypeToInteger(); 481 } 482 483 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 484 TargetLowering::DAGCombinerInfo &DCI, 485 const MipsSubtarget &Subtarget) { 486 if (DCI.isBeforeLegalizeOps()) 487 return SDValue(); 488 489 EVT Ty = N->getValueType(0); 490 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 491 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 492 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 493 MipsISD::DivRemU16; 494 SDLoc DL(N); 495 496 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 497 N->getOperand(0), N->getOperand(1)); 498 SDValue InChain = DAG.getEntryNode(); 499 SDValue InGlue = DivRem; 500 501 // insert MFLO 502 if (N->hasAnyUseOfValue(0)) { 503 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 504 InGlue); 505 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 506 InChain = CopyFromLo.getValue(1); 507 InGlue = CopyFromLo.getValue(2); 508 } 509 510 // insert MFHI 511 if (N->hasAnyUseOfValue(1)) { 512 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 513 HI, Ty, InGlue); 514 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 515 } 516 517 return SDValue(); 518 } 519 520 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 521 switch (CC) { 522 default: llvm_unreachable("Unknown fp condition code!"); 523 case ISD::SETEQ: 524 case ISD::SETOEQ: return Mips::FCOND_OEQ; 525 case ISD::SETUNE: return Mips::FCOND_UNE; 526 case ISD::SETLT: 527 case ISD::SETOLT: return Mips::FCOND_OLT; 528 case ISD::SETGT: 529 case ISD::SETOGT: return Mips::FCOND_OGT; 530 case ISD::SETLE: 531 case ISD::SETOLE: return Mips::FCOND_OLE; 532 case ISD::SETGE: 533 case ISD::SETOGE: return Mips::FCOND_OGE; 534 case ISD::SETULT: return Mips::FCOND_ULT; 535 case ISD::SETULE: return Mips::FCOND_ULE; 536 case ISD::SETUGT: return Mips::FCOND_UGT; 537 case ISD::SETUGE: return Mips::FCOND_UGE; 538 case ISD::SETUO: return Mips::FCOND_UN; 539 case ISD::SETO: return Mips::FCOND_OR; 540 case ISD::SETNE: 541 case ISD::SETONE: return Mips::FCOND_ONE; 542 case ISD::SETUEQ: return Mips::FCOND_UEQ; 543 } 544 } 545 546 547 /// This function returns true if the floating point conditional branches and 548 /// conditional moves which use condition code CC should be inverted. 549 static bool invertFPCondCodeUser(Mips::CondCode CC) { 550 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 551 return false; 552 553 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 554 "Illegal Condition Code"); 555 556 return true; 557 } 558 559 // Creates and returns an FPCmp node from a setcc node. 560 // Returns Op if setcc is not a floating point comparison. 561 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 562 // must be a SETCC node 563 if (Op.getOpcode() != ISD::SETCC) 564 return Op; 565 566 SDValue LHS = Op.getOperand(0); 567 568 if (!LHS.getValueType().isFloatingPoint()) 569 return Op; 570 571 SDValue RHS = Op.getOperand(1); 572 SDLoc DL(Op); 573 574 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 575 // node if necessary. 576 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 577 578 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 579 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 580 } 581 582 // Creates and returns a CMovFPT/F node. 583 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 584 SDValue False, const SDLoc &DL) { 585 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 586 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 587 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 588 589 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 590 True.getValueType(), True, FCC0, False, Cond); 591 } 592 593 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 594 TargetLowering::DAGCombinerInfo &DCI, 595 const MipsSubtarget &Subtarget) { 596 if (DCI.isBeforeLegalizeOps()) 597 return SDValue(); 598 599 SDValue SetCC = N->getOperand(0); 600 601 if ((SetCC.getOpcode() != ISD::SETCC) || 602 !SetCC.getOperand(0).getValueType().isInteger()) 603 return SDValue(); 604 605 SDValue False = N->getOperand(2); 606 EVT FalseTy = False.getValueType(); 607 608 if (!FalseTy.isInteger()) 609 return SDValue(); 610 611 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 612 613 // If the RHS (False) is 0, we swap the order of the operands 614 // of ISD::SELECT (obviously also inverting the condition) so that we can 615 // take advantage of conditional moves using the $0 register. 616 // Example: 617 // return (a != 0) ? x : 0; 618 // load $reg, x 619 // movz $reg, $0, a 620 if (!FalseC) 621 return SDValue(); 622 623 const SDLoc DL(N); 624 625 if (!FalseC->getZExtValue()) { 626 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 627 SDValue True = N->getOperand(1); 628 629 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 630 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 631 632 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 633 } 634 635 // If both operands are integer constants there's a possibility that we 636 // can do some interesting optimizations. 637 SDValue True = N->getOperand(1); 638 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 639 640 if (!TrueC || !True.getValueType().isInteger()) 641 return SDValue(); 642 643 // We'll also ignore MVT::i64 operands as this optimizations proves 644 // to be ineffective because of the required sign extensions as the result 645 // of a SETCC operator is always MVT::i32 for non-vector types. 646 if (True.getValueType() == MVT::i64) 647 return SDValue(); 648 649 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 650 651 // 1) (a < x) ? y : y-1 652 // slti $reg1, a, x 653 // addiu $reg2, $reg1, y-1 654 if (Diff == 1) 655 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 656 657 // 2) (a < x) ? y-1 : y 658 // slti $reg1, a, x 659 // xor $reg1, $reg1, 1 660 // addiu $reg2, $reg1, y-1 661 if (Diff == -1) { 662 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 663 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 664 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 665 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 666 } 667 668 // Couldn't optimize. 669 return SDValue(); 670 } 671 672 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 673 TargetLowering::DAGCombinerInfo &DCI, 674 const MipsSubtarget &Subtarget) { 675 if (DCI.isBeforeLegalizeOps()) 676 return SDValue(); 677 678 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 679 680 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 681 if (!FalseC || FalseC->getZExtValue()) 682 return SDValue(); 683 684 // Since RHS (False) is 0, we swap the order of the True/False operands 685 // (obviously also inverting the condition) so that we can 686 // take advantage of conditional moves using the $0 register. 687 // Example: 688 // return (a != 0) ? x : 0; 689 // load $reg, x 690 // movz $reg, $0, a 691 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 692 MipsISD::CMovFP_T; 693 694 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 695 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 696 ValueIfFalse, FCC, ValueIfTrue, Glue); 697 } 698 699 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 700 TargetLowering::DAGCombinerInfo &DCI, 701 const MipsSubtarget &Subtarget) { 702 // Pattern match EXT. 703 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 704 // => ext $dst, $src, size, pos 705 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 706 return SDValue(); 707 708 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 709 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 710 711 // Op's first operand must be a shift right. 712 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 713 return SDValue(); 714 715 // The second operand of the shift must be an immediate. 716 ConstantSDNode *CN; 717 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 718 return SDValue(); 719 720 uint64_t Pos = CN->getZExtValue(); 721 uint64_t SMPos, SMSize; 722 723 // Op's second operand must be a shifted mask. 724 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 725 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 726 return SDValue(); 727 728 // Return if the shifted mask does not start at bit 0 or the sum of its size 729 // and Pos exceeds the word's size. 730 EVT ValTy = N->getValueType(0); 731 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 732 return SDValue(); 733 734 SDLoc DL(N); 735 return DAG.getNode(MipsISD::Ext, DL, ValTy, 736 ShiftRight.getOperand(0), 737 DAG.getConstant(Pos, DL, MVT::i32), 738 DAG.getConstant(SMSize, DL, MVT::i32)); 739 } 740 741 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 742 TargetLowering::DAGCombinerInfo &DCI, 743 const MipsSubtarget &Subtarget) { 744 // Pattern match INS. 745 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 746 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 747 // => ins $dst, $src, size, pos, $src1 748 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 749 return SDValue(); 750 751 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 752 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 753 ConstantSDNode *CN; 754 755 // See if Op's first operand matches (and $src1 , mask0). 756 if (And0.getOpcode() != ISD::AND) 757 return SDValue(); 758 759 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 760 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 761 return SDValue(); 762 763 // See if Op's second operand matches (and (shl $src, pos), mask1). 764 if (And1.getOpcode() != ISD::AND) 765 return SDValue(); 766 767 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 768 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 769 return SDValue(); 770 771 // The shift masks must have the same position and size. 772 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 773 return SDValue(); 774 775 SDValue Shl = And1.getOperand(0); 776 if (Shl.getOpcode() != ISD::SHL) 777 return SDValue(); 778 779 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 780 return SDValue(); 781 782 unsigned Shamt = CN->getZExtValue(); 783 784 // Return if the shift amount and the first bit position of mask are not the 785 // same. 786 EVT ValTy = N->getValueType(0); 787 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 788 return SDValue(); 789 790 SDLoc DL(N); 791 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 792 DAG.getConstant(SMPos0, DL, MVT::i32), 793 DAG.getConstant(SMSize0, DL, MVT::i32), 794 And0.getOperand(0)); 795 } 796 797 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 798 TargetLowering::DAGCombinerInfo &DCI, 799 const MipsSubtarget &Subtarget) { 800 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 801 802 if (DCI.isBeforeLegalizeOps()) 803 return SDValue(); 804 805 SDValue Add = N->getOperand(1); 806 807 if (Add.getOpcode() != ISD::ADD) 808 return SDValue(); 809 810 SDValue Lo = Add.getOperand(1); 811 812 if ((Lo.getOpcode() != MipsISD::Lo) || 813 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 814 return SDValue(); 815 816 EVT ValTy = N->getValueType(0); 817 SDLoc DL(N); 818 819 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 820 Add.getOperand(0)); 821 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 822 } 823 824 static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG, 825 TargetLowering::DAGCombinerInfo &DCI, 826 const MipsSubtarget &Subtarget) { 827 SDValue N0 = N->getOperand(0); 828 EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 829 830 if (N0.getOpcode() != ISD::TRUNCATE) 831 return SDValue(); 832 833 if (N0.getOperand(0).getOpcode() != ISD::AssertZext) 834 return SDValue(); 835 836 // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x)) 837 // if the type of the extension of the innermost AssertZext node is 838 // smaller from that of the outermost node, eg: 839 // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) 840 // -> (trunc:i32 (AssertZext X, i8)) 841 SDValue WiderAssertZext = N0.getOperand(0); 842 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT(); 843 844 if (NarrowerVT.bitsLT(WiderVT)) { 845 SDValue NewAssertZext = DAG.getNode( 846 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(), 847 WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT)); 848 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), 849 NewAssertZext); 850 } 851 852 return SDValue(); 853 } 854 855 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 856 const { 857 SelectionDAG &DAG = DCI.DAG; 858 unsigned Opc = N->getOpcode(); 859 860 switch (Opc) { 861 default: break; 862 case ISD::SDIVREM: 863 case ISD::UDIVREM: 864 return performDivRemCombine(N, DAG, DCI, Subtarget); 865 case ISD::SELECT: 866 return performSELECTCombine(N, DAG, DCI, Subtarget); 867 case MipsISD::CMovFP_F: 868 case MipsISD::CMovFP_T: 869 return performCMovFPCombine(N, DAG, DCI, Subtarget); 870 case ISD::AND: 871 return performANDCombine(N, DAG, DCI, Subtarget); 872 case ISD::OR: 873 return performORCombine(N, DAG, DCI, Subtarget); 874 case ISD::ADD: 875 return performADDCombine(N, DAG, DCI, Subtarget); 876 case ISD::AssertZext: 877 return performAssertZextCombine(N, DAG, DCI, Subtarget); 878 } 879 880 return SDValue(); 881 } 882 883 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 884 return Subtarget.hasMips32(); 885 } 886 887 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 888 return Subtarget.hasMips32(); 889 } 890 891 void 892 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 893 SmallVectorImpl<SDValue> &Results, 894 SelectionDAG &DAG) const { 895 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 896 897 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 898 Results.push_back(Res.getValue(I)); 899 } 900 901 void 902 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 903 SmallVectorImpl<SDValue> &Results, 904 SelectionDAG &DAG) const { 905 return LowerOperationWrapper(N, Results, DAG); 906 } 907 908 SDValue MipsTargetLowering:: 909 LowerOperation(SDValue Op, SelectionDAG &DAG) const 910 { 911 switch (Op.getOpcode()) 912 { 913 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 914 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 915 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 916 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 917 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 918 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 919 case ISD::SELECT: return lowerSELECT(Op, DAG); 920 case ISD::SETCC: return lowerSETCC(Op, DAG); 921 case ISD::VASTART: return lowerVASTART(Op, DAG); 922 case ISD::VAARG: return lowerVAARG(Op, DAG); 923 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 924 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 925 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 926 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 927 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 928 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 929 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 930 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 931 case ISD::LOAD: return lowerLOAD(Op, DAG); 932 case ISD::STORE: return lowerSTORE(Op, DAG); 933 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 934 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 935 } 936 return SDValue(); 937 } 938 939 //===----------------------------------------------------------------------===// 940 // Lower helper functions 941 //===----------------------------------------------------------------------===// 942 943 // addLiveIn - This helper function adds the specified physical register to the 944 // MachineFunction as a live in value. It also creates a corresponding 945 // virtual register for it. 946 static unsigned 947 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 948 { 949 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 950 MF.getRegInfo().addLiveIn(PReg, VReg); 951 return VReg; 952 } 953 954 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 955 MachineBasicBlock &MBB, 956 const TargetInstrInfo &TII, 957 bool Is64Bit, bool IsMicroMips) { 958 if (NoZeroDivCheck) 959 return &MBB; 960 961 // Insert instruction "teq $divisor_reg, $zero, 7". 962 MachineBasicBlock::iterator I(MI); 963 MachineInstrBuilder MIB; 964 MachineOperand &Divisor = MI.getOperand(2); 965 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 966 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 967 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 968 .addReg(Mips::ZERO) 969 .addImm(7); 970 971 // Use the 32-bit sub-register if this is a 64-bit division. 972 if (Is64Bit) 973 MIB->getOperand(0).setSubReg(Mips::sub_32); 974 975 // Clear Divisor's kill flag. 976 Divisor.setIsKill(false); 977 978 // We would normally delete the original instruction here but in this case 979 // we only needed to inject an additional instruction rather than replace it. 980 981 return &MBB; 982 } 983 984 MachineBasicBlock * 985 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 986 MachineBasicBlock *BB) const { 987 switch (MI.getOpcode()) { 988 default: 989 llvm_unreachable("Unexpected instr type to insert"); 990 case Mips::ATOMIC_LOAD_ADD_I8: 991 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 992 case Mips::ATOMIC_LOAD_ADD_I16: 993 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 994 case Mips::ATOMIC_LOAD_ADD_I32: 995 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 996 case Mips::ATOMIC_LOAD_ADD_I64: 997 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 998 999 case Mips::ATOMIC_LOAD_AND_I8: 1000 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1001 case Mips::ATOMIC_LOAD_AND_I16: 1002 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1003 case Mips::ATOMIC_LOAD_AND_I32: 1004 return emitAtomicBinary(MI, BB, 4, Mips::AND); 1005 case Mips::ATOMIC_LOAD_AND_I64: 1006 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 1007 1008 case Mips::ATOMIC_LOAD_OR_I8: 1009 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1010 case Mips::ATOMIC_LOAD_OR_I16: 1011 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1012 case Mips::ATOMIC_LOAD_OR_I32: 1013 return emitAtomicBinary(MI, BB, 4, Mips::OR); 1014 case Mips::ATOMIC_LOAD_OR_I64: 1015 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 1016 1017 case Mips::ATOMIC_LOAD_XOR_I8: 1018 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1019 case Mips::ATOMIC_LOAD_XOR_I16: 1020 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1021 case Mips::ATOMIC_LOAD_XOR_I32: 1022 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1023 case Mips::ATOMIC_LOAD_XOR_I64: 1024 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1025 1026 case Mips::ATOMIC_LOAD_NAND_I8: 1027 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1028 case Mips::ATOMIC_LOAD_NAND_I16: 1029 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1030 case Mips::ATOMIC_LOAD_NAND_I32: 1031 return emitAtomicBinary(MI, BB, 4, 0, true); 1032 case Mips::ATOMIC_LOAD_NAND_I64: 1033 return emitAtomicBinary(MI, BB, 8, 0, true); 1034 1035 case Mips::ATOMIC_LOAD_SUB_I8: 1036 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1037 case Mips::ATOMIC_LOAD_SUB_I16: 1038 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1039 case Mips::ATOMIC_LOAD_SUB_I32: 1040 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1041 case Mips::ATOMIC_LOAD_SUB_I64: 1042 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1043 1044 case Mips::ATOMIC_SWAP_I8: 1045 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1046 case Mips::ATOMIC_SWAP_I16: 1047 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1048 case Mips::ATOMIC_SWAP_I32: 1049 return emitAtomicBinary(MI, BB, 4, 0); 1050 case Mips::ATOMIC_SWAP_I64: 1051 return emitAtomicBinary(MI, BB, 8, 0); 1052 1053 case Mips::ATOMIC_CMP_SWAP_I8: 1054 return emitAtomicCmpSwapPartword(MI, BB, 1); 1055 case Mips::ATOMIC_CMP_SWAP_I16: 1056 return emitAtomicCmpSwapPartword(MI, BB, 2); 1057 case Mips::ATOMIC_CMP_SWAP_I32: 1058 return emitAtomicCmpSwap(MI, BB, 4); 1059 case Mips::ATOMIC_CMP_SWAP_I64: 1060 return emitAtomicCmpSwap(MI, BB, 8); 1061 case Mips::PseudoSDIV: 1062 case Mips::PseudoUDIV: 1063 case Mips::DIV: 1064 case Mips::DIVU: 1065 case Mips::MOD: 1066 case Mips::MODU: 1067 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1068 false); 1069 case Mips::SDIV_MM_Pseudo: 1070 case Mips::UDIV_MM_Pseudo: 1071 case Mips::SDIV_MM: 1072 case Mips::UDIV_MM: 1073 case Mips::DIV_MMR6: 1074 case Mips::DIVU_MMR6: 1075 case Mips::MOD_MMR6: 1076 case Mips::MODU_MMR6: 1077 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1078 case Mips::PseudoDSDIV: 1079 case Mips::PseudoDUDIV: 1080 case Mips::DDIV: 1081 case Mips::DDIVU: 1082 case Mips::DMOD: 1083 case Mips::DMODU: 1084 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1085 case Mips::DDIV_MM64R6: 1086 case Mips::DDIVU_MM64R6: 1087 case Mips::DMOD_MM64R6: 1088 case Mips::DMODU_MM64R6: 1089 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); 1090 case Mips::SEL_D: 1091 case Mips::SEL_D_MMR6: 1092 return emitSEL_D(MI, BB); 1093 1094 case Mips::PseudoSELECT_I: 1095 case Mips::PseudoSELECT_I64: 1096 case Mips::PseudoSELECT_S: 1097 case Mips::PseudoSELECT_D32: 1098 case Mips::PseudoSELECT_D64: 1099 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1100 case Mips::PseudoSELECTFP_F_I: 1101 case Mips::PseudoSELECTFP_F_I64: 1102 case Mips::PseudoSELECTFP_F_S: 1103 case Mips::PseudoSELECTFP_F_D32: 1104 case Mips::PseudoSELECTFP_F_D64: 1105 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1106 case Mips::PseudoSELECTFP_T_I: 1107 case Mips::PseudoSELECTFP_T_I64: 1108 case Mips::PseudoSELECTFP_T_S: 1109 case Mips::PseudoSELECTFP_T_D32: 1110 case Mips::PseudoSELECTFP_T_D64: 1111 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1112 } 1113 } 1114 1115 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1116 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1117 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1118 MachineBasicBlock *BB, 1119 unsigned Size, 1120 unsigned BinOpcode, 1121 bool Nand) const { 1122 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1123 1124 MachineFunction *MF = BB->getParent(); 1125 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1126 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1127 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1128 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1129 DebugLoc DL = MI.getDebugLoc(); 1130 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1131 1132 if (Size == 4) { 1133 if (isMicroMips) { 1134 LL = Mips::LL_MM; 1135 SC = Mips::SC_MM; 1136 } else { 1137 LL = Subtarget.hasMips32r6() 1138 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1139 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1140 SC = Subtarget.hasMips32r6() 1141 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1142 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1143 } 1144 1145 AND = Mips::AND; 1146 NOR = Mips::NOR; 1147 ZERO = Mips::ZERO; 1148 BEQ = Mips::BEQ; 1149 } else { 1150 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1151 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1152 AND = Mips::AND64; 1153 NOR = Mips::NOR64; 1154 ZERO = Mips::ZERO_64; 1155 BEQ = Mips::BEQ64; 1156 } 1157 1158 unsigned OldVal = MI.getOperand(0).getReg(); 1159 unsigned Ptr = MI.getOperand(1).getReg(); 1160 unsigned Incr = MI.getOperand(2).getReg(); 1161 1162 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1163 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1164 unsigned Success = RegInfo.createVirtualRegister(RC); 1165 1166 // insert new blocks after the current block 1167 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1168 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1169 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1170 MachineFunction::iterator It = ++BB->getIterator(); 1171 MF->insert(It, loopMBB); 1172 MF->insert(It, exitMBB); 1173 1174 // Transfer the remainder of BB and its successor edges to exitMBB. 1175 exitMBB->splice(exitMBB->begin(), BB, 1176 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1177 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1178 1179 // thisMBB: 1180 // ... 1181 // fallthrough --> loopMBB 1182 BB->addSuccessor(loopMBB); 1183 loopMBB->addSuccessor(loopMBB); 1184 loopMBB->addSuccessor(exitMBB); 1185 1186 // loopMBB: 1187 // ll oldval, 0(ptr) 1188 // <binop> storeval, oldval, incr 1189 // sc success, storeval, 0(ptr) 1190 // beq success, $0, loopMBB 1191 BB = loopMBB; 1192 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1193 if (Nand) { 1194 // and andres, oldval, incr 1195 // nor storeval, $0, andres 1196 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1197 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1198 } else if (BinOpcode) { 1199 // <binop> storeval, oldval, incr 1200 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1201 } else { 1202 StoreVal = Incr; 1203 } 1204 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1205 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1206 1207 MI.eraseFromParent(); // The instruction is gone now. 1208 1209 return exitMBB; 1210 } 1211 1212 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1213 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1214 unsigned SrcReg) const { 1215 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1216 const DebugLoc &DL = MI.getDebugLoc(); 1217 1218 if (Subtarget.hasMips32r2() && Size == 1) { 1219 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1220 return BB; 1221 } 1222 1223 if (Subtarget.hasMips32r2() && Size == 2) { 1224 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1225 return BB; 1226 } 1227 1228 MachineFunction *MF = BB->getParent(); 1229 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1230 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1231 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1232 1233 assert(Size < 32); 1234 int64_t ShiftImm = 32 - (Size * 8); 1235 1236 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1237 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1238 1239 return BB; 1240 } 1241 1242 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1243 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1244 bool Nand) const { 1245 assert((Size == 1 || Size == 2) && 1246 "Unsupported size for EmitAtomicBinaryPartial."); 1247 1248 MachineFunction *MF = BB->getParent(); 1249 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1250 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1251 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1252 const TargetRegisterClass *RCp = 1253 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1254 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1255 DebugLoc DL = MI.getDebugLoc(); 1256 1257 unsigned Dest = MI.getOperand(0).getReg(); 1258 unsigned Ptr = MI.getOperand(1).getReg(); 1259 unsigned Incr = MI.getOperand(2).getReg(); 1260 1261 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1262 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1263 unsigned Mask = RegInfo.createVirtualRegister(RC); 1264 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1265 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1266 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1267 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1268 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1269 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1270 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1271 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1272 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1273 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1274 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1275 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1276 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1277 unsigned Success = RegInfo.createVirtualRegister(RC); 1278 1279 unsigned LL, SC; 1280 if (isMicroMips) { 1281 LL = Mips::LL_MM; 1282 SC = Mips::SC_MM; 1283 } else { 1284 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1285 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1286 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1287 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1288 } 1289 1290 // insert new blocks after the current block 1291 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1292 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1293 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1294 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1295 MachineFunction::iterator It = ++BB->getIterator(); 1296 MF->insert(It, loopMBB); 1297 MF->insert(It, sinkMBB); 1298 MF->insert(It, exitMBB); 1299 1300 // Transfer the remainder of BB and its successor edges to exitMBB. 1301 exitMBB->splice(exitMBB->begin(), BB, 1302 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1303 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1304 1305 BB->addSuccessor(loopMBB); 1306 loopMBB->addSuccessor(loopMBB); 1307 loopMBB->addSuccessor(sinkMBB); 1308 sinkMBB->addSuccessor(exitMBB); 1309 1310 // thisMBB: 1311 // addiu masklsb2,$0,-4 # 0xfffffffc 1312 // and alignedaddr,ptr,masklsb2 1313 // andi ptrlsb2,ptr,3 1314 // sll shiftamt,ptrlsb2,3 1315 // ori maskupper,$0,255 # 0xff 1316 // sll mask,maskupper,shiftamt 1317 // nor mask2,$0,mask 1318 // sll incr2,incr,shiftamt 1319 1320 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1321 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1322 .addReg(ABI.GetNullPtr()).addImm(-4); 1323 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1324 .addReg(Ptr).addReg(MaskLSB2); 1325 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1326 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1327 if (Subtarget.isLittle()) { 1328 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1329 } else { 1330 unsigned Off = RegInfo.createVirtualRegister(RC); 1331 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1332 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1333 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1334 } 1335 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1336 .addReg(Mips::ZERO).addImm(MaskImm); 1337 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1338 .addReg(MaskUpper).addReg(ShiftAmt); 1339 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1340 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1341 1342 // atomic.load.binop 1343 // loopMBB: 1344 // ll oldval,0(alignedaddr) 1345 // binop binopres,oldval,incr2 1346 // and newval,binopres,mask 1347 // and maskedoldval0,oldval,mask2 1348 // or storeval,maskedoldval0,newval 1349 // sc success,storeval,0(alignedaddr) 1350 // beq success,$0,loopMBB 1351 1352 // atomic.swap 1353 // loopMBB: 1354 // ll oldval,0(alignedaddr) 1355 // and newval,incr2,mask 1356 // and maskedoldval0,oldval,mask2 1357 // or storeval,maskedoldval0,newval 1358 // sc success,storeval,0(alignedaddr) 1359 // beq success,$0,loopMBB 1360 1361 BB = loopMBB; 1362 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1363 if (Nand) { 1364 // and andres, oldval, incr2 1365 // nor binopres, $0, andres 1366 // and newval, binopres, mask 1367 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1368 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1369 .addReg(Mips::ZERO).addReg(AndRes); 1370 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1371 } else if (BinOpcode) { 1372 // <binop> binopres, oldval, incr2 1373 // and newval, binopres, mask 1374 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1375 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1376 } else { // atomic.swap 1377 // and newval, incr2, mask 1378 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1379 } 1380 1381 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1382 .addReg(OldVal).addReg(Mask2); 1383 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1384 .addReg(MaskedOldVal0).addReg(NewVal); 1385 BuildMI(BB, DL, TII->get(SC), Success) 1386 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1387 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1388 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1389 1390 // sinkMBB: 1391 // and maskedoldval1,oldval,mask 1392 // srl srlres,maskedoldval1,shiftamt 1393 // sign_extend dest,srlres 1394 BB = sinkMBB; 1395 1396 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1397 .addReg(OldVal).addReg(Mask); 1398 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1399 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1400 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1401 1402 MI.eraseFromParent(); // The instruction is gone now. 1403 1404 return exitMBB; 1405 } 1406 1407 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1408 MachineBasicBlock *BB, 1409 unsigned Size) const { 1410 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1411 1412 MachineFunction *MF = BB->getParent(); 1413 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1414 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1415 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1416 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1417 DebugLoc DL = MI.getDebugLoc(); 1418 unsigned LL, SC, ZERO, BNE, BEQ; 1419 1420 if (Size == 4) { 1421 if (isMicroMips) { 1422 LL = Mips::LL_MM; 1423 SC = Mips::SC_MM; 1424 } else { 1425 LL = Subtarget.hasMips32r6() 1426 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1427 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1428 SC = Subtarget.hasMips32r6() 1429 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1430 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1431 } 1432 1433 ZERO = Mips::ZERO; 1434 BNE = Mips::BNE; 1435 BEQ = Mips::BEQ; 1436 } else { 1437 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1438 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1439 ZERO = Mips::ZERO_64; 1440 BNE = Mips::BNE64; 1441 BEQ = Mips::BEQ64; 1442 } 1443 1444 unsigned Dest = MI.getOperand(0).getReg(); 1445 unsigned Ptr = MI.getOperand(1).getReg(); 1446 unsigned OldVal = MI.getOperand(2).getReg(); 1447 unsigned NewVal = MI.getOperand(3).getReg(); 1448 1449 unsigned Success = RegInfo.createVirtualRegister(RC); 1450 1451 // insert new blocks after the current block 1452 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1453 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1454 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1455 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1456 MachineFunction::iterator It = ++BB->getIterator(); 1457 MF->insert(It, loop1MBB); 1458 MF->insert(It, loop2MBB); 1459 MF->insert(It, exitMBB); 1460 1461 // Transfer the remainder of BB and its successor edges to exitMBB. 1462 exitMBB->splice(exitMBB->begin(), BB, 1463 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1464 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1465 1466 // thisMBB: 1467 // ... 1468 // fallthrough --> loop1MBB 1469 BB->addSuccessor(loop1MBB); 1470 loop1MBB->addSuccessor(exitMBB); 1471 loop1MBB->addSuccessor(loop2MBB); 1472 loop2MBB->addSuccessor(loop1MBB); 1473 loop2MBB->addSuccessor(exitMBB); 1474 1475 // loop1MBB: 1476 // ll dest, 0(ptr) 1477 // bne dest, oldval, exitMBB 1478 BB = loop1MBB; 1479 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1480 BuildMI(BB, DL, TII->get(BNE)) 1481 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1482 1483 // loop2MBB: 1484 // sc success, newval, 0(ptr) 1485 // beq success, $0, loop1MBB 1486 BB = loop2MBB; 1487 BuildMI(BB, DL, TII->get(SC), Success) 1488 .addReg(NewVal).addReg(Ptr).addImm(0); 1489 BuildMI(BB, DL, TII->get(BEQ)) 1490 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1491 1492 MI.eraseFromParent(); // The instruction is gone now. 1493 1494 return exitMBB; 1495 } 1496 1497 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1498 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1499 assert((Size == 1 || Size == 2) && 1500 "Unsupported size for EmitAtomicCmpSwapPartial."); 1501 1502 MachineFunction *MF = BB->getParent(); 1503 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1504 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1505 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1506 const TargetRegisterClass *RCp = 1507 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1508 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1509 DebugLoc DL = MI.getDebugLoc(); 1510 1511 unsigned Dest = MI.getOperand(0).getReg(); 1512 unsigned Ptr = MI.getOperand(1).getReg(); 1513 unsigned CmpVal = MI.getOperand(2).getReg(); 1514 unsigned NewVal = MI.getOperand(3).getReg(); 1515 1516 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1517 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1518 unsigned Mask = RegInfo.createVirtualRegister(RC); 1519 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1520 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1521 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1522 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1523 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1524 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1525 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1526 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1527 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1528 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1529 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1530 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1531 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1532 unsigned Success = RegInfo.createVirtualRegister(RC); 1533 unsigned LL, SC; 1534 1535 if (isMicroMips) { 1536 LL = Mips::LL_MM; 1537 SC = Mips::SC_MM; 1538 } else { 1539 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1540 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1541 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1542 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1543 } 1544 1545 // insert new blocks after the current block 1546 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1547 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1548 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1549 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1550 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1551 MachineFunction::iterator It = ++BB->getIterator(); 1552 MF->insert(It, loop1MBB); 1553 MF->insert(It, loop2MBB); 1554 MF->insert(It, sinkMBB); 1555 MF->insert(It, exitMBB); 1556 1557 // Transfer the remainder of BB and its successor edges to exitMBB. 1558 exitMBB->splice(exitMBB->begin(), BB, 1559 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1560 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1561 1562 BB->addSuccessor(loop1MBB); 1563 loop1MBB->addSuccessor(sinkMBB); 1564 loop1MBB->addSuccessor(loop2MBB); 1565 loop2MBB->addSuccessor(loop1MBB); 1566 loop2MBB->addSuccessor(sinkMBB); 1567 sinkMBB->addSuccessor(exitMBB); 1568 1569 // FIXME: computation of newval2 can be moved to loop2MBB. 1570 // thisMBB: 1571 // addiu masklsb2,$0,-4 # 0xfffffffc 1572 // and alignedaddr,ptr,masklsb2 1573 // andi ptrlsb2,ptr,3 1574 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1575 // sll shiftamt,ptrlsb2,3 1576 // ori maskupper,$0,255 # 0xff 1577 // sll mask,maskupper,shiftamt 1578 // nor mask2,$0,mask 1579 // andi maskedcmpval,cmpval,255 1580 // sll shiftedcmpval,maskedcmpval,shiftamt 1581 // andi maskednewval,newval,255 1582 // sll shiftednewval,maskednewval,shiftamt 1583 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1584 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1585 .addReg(ABI.GetNullPtr()).addImm(-4); 1586 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1587 .addReg(Ptr).addReg(MaskLSB2); 1588 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1589 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1590 if (Subtarget.isLittle()) { 1591 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1592 } else { 1593 unsigned Off = RegInfo.createVirtualRegister(RC); 1594 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1595 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1596 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1597 } 1598 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1599 .addReg(Mips::ZERO).addImm(MaskImm); 1600 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1601 .addReg(MaskUpper).addReg(ShiftAmt); 1602 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1603 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1604 .addReg(CmpVal).addImm(MaskImm); 1605 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1606 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1607 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1608 .addReg(NewVal).addImm(MaskImm); 1609 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1610 .addReg(MaskedNewVal).addReg(ShiftAmt); 1611 1612 // loop1MBB: 1613 // ll oldval,0(alginedaddr) 1614 // and maskedoldval0,oldval,mask 1615 // bne maskedoldval0,shiftedcmpval,sinkMBB 1616 BB = loop1MBB; 1617 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1618 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1619 .addReg(OldVal).addReg(Mask); 1620 BuildMI(BB, DL, TII->get(Mips::BNE)) 1621 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1622 1623 // loop2MBB: 1624 // and maskedoldval1,oldval,mask2 1625 // or storeval,maskedoldval1,shiftednewval 1626 // sc success,storeval,0(alignedaddr) 1627 // beq success,$0,loop1MBB 1628 BB = loop2MBB; 1629 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1630 .addReg(OldVal).addReg(Mask2); 1631 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1632 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1633 BuildMI(BB, DL, TII->get(SC), Success) 1634 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1635 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1636 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1637 1638 // sinkMBB: 1639 // srl srlres,maskedoldval0,shiftamt 1640 // sign_extend dest,srlres 1641 BB = sinkMBB; 1642 1643 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1644 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1645 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1646 1647 MI.eraseFromParent(); // The instruction is gone now. 1648 1649 return exitMBB; 1650 } 1651 1652 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI, 1653 MachineBasicBlock *BB) const { 1654 MachineFunction *MF = BB->getParent(); 1655 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1656 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1657 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1658 DebugLoc DL = MI.getDebugLoc(); 1659 MachineBasicBlock::iterator II(MI); 1660 1661 unsigned Fc = MI.getOperand(1).getReg(); 1662 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); 1663 1664 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); 1665 1666 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2) 1667 .addImm(0) 1668 .addReg(Fc) 1669 .addImm(Mips::sub_lo); 1670 1671 // We don't erase the original instruction, we just replace the condition 1672 // register with the 64-bit super-register. 1673 MI.getOperand(1).setReg(Fc2); 1674 1675 return BB; 1676 } 1677 1678 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1679 // The first operand is the chain, the second is the condition, the third is 1680 // the block to branch to if the condition is true. 1681 SDValue Chain = Op.getOperand(0); 1682 SDValue Dest = Op.getOperand(2); 1683 SDLoc DL(Op); 1684 1685 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1686 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1687 1688 // Return if flag is not set by a floating point comparison. 1689 if (CondRes.getOpcode() != MipsISD::FPCmp) 1690 return Op; 1691 1692 SDValue CCNode = CondRes.getOperand(2); 1693 Mips::CondCode CC = 1694 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1695 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1696 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1697 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1698 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1699 FCC0, Dest, CondRes); 1700 } 1701 1702 SDValue MipsTargetLowering:: 1703 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1704 { 1705 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1706 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1707 1708 // Return if flag is not set by a floating point comparison. 1709 if (Cond.getOpcode() != MipsISD::FPCmp) 1710 return Op; 1711 1712 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1713 SDLoc(Op)); 1714 } 1715 1716 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1717 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1718 SDValue Cond = createFPCmp(DAG, Op); 1719 1720 assert(Cond.getOpcode() == MipsISD::FPCmp && 1721 "Floating point operand expected."); 1722 1723 SDLoc DL(Op); 1724 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1725 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1726 1727 return createCMovFP(DAG, Cond, True, False, DL); 1728 } 1729 1730 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1731 SelectionDAG &DAG) const { 1732 EVT Ty = Op.getValueType(); 1733 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1734 const GlobalValue *GV = N->getGlobal(); 1735 1736 if (!isPositionIndependent() && !ABI.IsN64()) { 1737 const MipsTargetObjectFile *TLOF = 1738 static_cast<const MipsTargetObjectFile *>( 1739 getTargetMachine().getObjFileLowering()); 1740 const GlobalObject *GO = GV->getBaseObject(); 1741 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 1742 // %gp_rel relocation 1743 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1744 1745 // %hi/%lo relocation 1746 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1747 } 1748 1749 // Every other architecture would use shouldAssumeDSOLocal in here, but 1750 // mips is special. 1751 // * In PIC code mips requires got loads even for local statics! 1752 // * To save on got entries, for local statics the got entry contains the 1753 // page and an additional add instruction takes care of the low bits. 1754 // * It is legal to access a hidden symbol with a non hidden undefined, 1755 // so one cannot guarantee that all access to a hidden symbol will know 1756 // it is hidden. 1757 // * Mips linkers don't support creating a page and a full got entry for 1758 // the same symbol. 1759 // * Given all that, we have to use a full got entry for hidden symbols :-( 1760 if (GV->hasLocalLinkage()) 1761 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1762 1763 if (LargeGOT) 1764 return getAddrGlobalLargeGOT( 1765 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 1766 DAG.getEntryNode(), 1767 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1768 1769 return getAddrGlobal( 1770 N, SDLoc(N), Ty, DAG, 1771 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 1772 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1773 } 1774 1775 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1776 SelectionDAG &DAG) const { 1777 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1778 EVT Ty = Op.getValueType(); 1779 1780 if (!isPositionIndependent() && !ABI.IsN64()) 1781 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1782 1783 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1784 } 1785 1786 SDValue MipsTargetLowering:: 1787 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1788 { 1789 // If the relocation model is PIC, use the General Dynamic TLS Model or 1790 // Local Dynamic TLS model, otherwise use the Initial Exec or 1791 // Local Exec TLS Model. 1792 1793 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1794 if (DAG.getTarget().Options.EmulatedTLS) 1795 return LowerToTLSEmulatedModel(GA, DAG); 1796 1797 SDLoc DL(GA); 1798 const GlobalValue *GV = GA->getGlobal(); 1799 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 1800 1801 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1802 1803 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1804 // General Dynamic and Local Dynamic TLS Model. 1805 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1806 : MipsII::MO_TLSGD; 1807 1808 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1809 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1810 getGlobalReg(DAG, PtrVT), TGA); 1811 unsigned PtrSize = PtrVT.getSizeInBits(); 1812 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1813 1814 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1815 1816 ArgListTy Args; 1817 ArgListEntry Entry; 1818 Entry.Node = Argument; 1819 Entry.Ty = PtrTy; 1820 Args.push_back(Entry); 1821 1822 TargetLowering::CallLoweringInfo CLI(DAG); 1823 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()) 1824 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 1825 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1826 1827 SDValue Ret = CallResult.first; 1828 1829 if (model != TLSModel::LocalDynamic) 1830 return Ret; 1831 1832 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1833 MipsII::MO_DTPREL_HI); 1834 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1835 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1836 MipsII::MO_DTPREL_LO); 1837 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1838 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1839 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1840 } 1841 1842 SDValue Offset; 1843 if (model == TLSModel::InitialExec) { 1844 // Initial Exec TLS Model 1845 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1846 MipsII::MO_GOTTPREL); 1847 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1848 TGA); 1849 Offset = 1850 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 1851 } else { 1852 // Local Exec TLS Model 1853 assert(model == TLSModel::LocalExec); 1854 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1855 MipsII::MO_TPREL_HI); 1856 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1857 MipsII::MO_TPREL_LO); 1858 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1859 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1860 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1861 } 1862 1863 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1864 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1865 } 1866 1867 SDValue MipsTargetLowering:: 1868 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1869 { 1870 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1871 EVT Ty = Op.getValueType(); 1872 1873 if (!isPositionIndependent() && !ABI.IsN64()) 1874 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1875 1876 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1877 } 1878 1879 SDValue MipsTargetLowering:: 1880 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1881 { 1882 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1883 EVT Ty = Op.getValueType(); 1884 1885 if (!isPositionIndependent() && !ABI.IsN64()) { 1886 const MipsTargetObjectFile *TLOF = 1887 static_cast<const MipsTargetObjectFile *>( 1888 getTargetMachine().getObjFileLowering()); 1889 1890 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 1891 getTargetMachine())) 1892 // %gp_rel relocation 1893 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1894 1895 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1896 } 1897 1898 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1899 } 1900 1901 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1902 MachineFunction &MF = DAG.getMachineFunction(); 1903 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1904 1905 SDLoc DL(Op); 1906 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1907 getPointerTy(MF.getDataLayout())); 1908 1909 // vastart just stores the address of the VarArgsFrameIndex slot into the 1910 // memory location argument. 1911 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1912 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1913 MachinePointerInfo(SV)); 1914 } 1915 1916 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 1917 SDNode *Node = Op.getNode(); 1918 EVT VT = Node->getValueType(0); 1919 SDValue Chain = Node->getOperand(0); 1920 SDValue VAListPtr = Node->getOperand(1); 1921 unsigned Align = Node->getConstantOperandVal(3); 1922 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1923 SDLoc DL(Node); 1924 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 1925 1926 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 1927 VAListPtr, MachinePointerInfo(SV)); 1928 SDValue VAList = VAListLoad; 1929 1930 // Re-align the pointer if necessary. 1931 // It should only ever be necessary for 64-bit types on O32 since the minimum 1932 // argument alignment is the same as the maximum type alignment for N32/N64. 1933 // 1934 // FIXME: We currently align too often. The code generator doesn't notice 1935 // when the pointer is still aligned from the last va_arg (or pair of 1936 // va_args for the i64 on O32 case). 1937 if (Align > getMinStackArgumentAlignment()) { 1938 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 1939 1940 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1941 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 1942 1943 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 1944 DAG.getConstant(-(int64_t)Align, DL, 1945 VAList.getValueType())); 1946 } 1947 1948 // Increment the pointer, VAList, to the next vaarg. 1949 auto &TD = DAG.getDataLayout(); 1950 unsigned ArgSizeInBytes = 1951 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 1952 SDValue Tmp3 = 1953 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1954 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 1955 DL, VAList.getValueType())); 1956 // Store the incremented VAList to the legalized pointer 1957 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 1958 MachinePointerInfo(SV)); 1959 1960 // In big-endian mode we must adjust the pointer when the load size is smaller 1961 // than the argument slot size. We must also reduce the known alignment to 1962 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 1963 // the correct half of the slot, and reduce the alignment from 8 (slot 1964 // alignment) down to 4 (type alignment). 1965 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 1966 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 1967 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 1968 DAG.getIntPtrConstant(Adjustment, DL)); 1969 } 1970 // Load the actual argument out of the pointer VAList 1971 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 1972 } 1973 1974 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 1975 bool HasExtractInsert) { 1976 EVT TyX = Op.getOperand(0).getValueType(); 1977 EVT TyY = Op.getOperand(1).getValueType(); 1978 SDLoc DL(Op); 1979 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 1980 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 1981 SDValue Res; 1982 1983 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1984 // to i32. 1985 SDValue X = (TyX == MVT::f32) ? 1986 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1987 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1988 Const1); 1989 SDValue Y = (TyY == MVT::f32) ? 1990 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1991 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1992 Const1); 1993 1994 if (HasExtractInsert) { 1995 // ext E, Y, 31, 1 ; extract bit31 of Y 1996 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1997 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1998 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1999 } else { 2000 // sll SllX, X, 1 2001 // srl SrlX, SllX, 1 2002 // srl SrlY, Y, 31 2003 // sll SllY, SrlX, 31 2004 // or Or, SrlX, SllY 2005 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2006 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2007 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2008 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2009 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2010 } 2011 2012 if (TyX == MVT::f32) 2013 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2014 2015 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2016 Op.getOperand(0), 2017 DAG.getConstant(0, DL, MVT::i32)); 2018 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2019 } 2020 2021 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2022 bool HasExtractInsert) { 2023 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2024 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2025 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2026 SDLoc DL(Op); 2027 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2028 2029 // Bitcast to integer nodes. 2030 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2031 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2032 2033 if (HasExtractInsert) { 2034 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2035 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2036 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2037 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2038 2039 if (WidthX > WidthY) 2040 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2041 else if (WidthY > WidthX) 2042 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2043 2044 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2045 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2046 X); 2047 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2048 } 2049 2050 // (d)sll SllX, X, 1 2051 // (d)srl SrlX, SllX, 1 2052 // (d)srl SrlY, Y, width(Y)-1 2053 // (d)sll SllY, SrlX, width(Y)-1 2054 // or Or, SrlX, SllY 2055 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2056 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2057 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2058 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2059 2060 if (WidthX > WidthY) 2061 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2062 else if (WidthY > WidthX) 2063 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2064 2065 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2066 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2067 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2068 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2069 } 2070 2071 SDValue 2072 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2073 if (Subtarget.isGP64bit()) 2074 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2075 2076 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2077 } 2078 2079 SDValue MipsTargetLowering:: 2080 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2081 // check the depth 2082 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2083 "Frame address can only be determined for current frame."); 2084 2085 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2086 MFI.setFrameAddressIsTaken(true); 2087 EVT VT = Op.getValueType(); 2088 SDLoc DL(Op); 2089 SDValue FrameAddr = DAG.getCopyFromReg( 2090 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2091 return FrameAddr; 2092 } 2093 2094 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2095 SelectionDAG &DAG) const { 2096 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2097 return SDValue(); 2098 2099 // check the depth 2100 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2101 "Return address can be determined only for current frame."); 2102 2103 MachineFunction &MF = DAG.getMachineFunction(); 2104 MachineFrameInfo &MFI = MF.getFrameInfo(); 2105 MVT VT = Op.getSimpleValueType(); 2106 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2107 MFI.setReturnAddressIsTaken(true); 2108 2109 // Return RA, which contains the return address. Mark it an implicit live-in. 2110 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2111 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2112 } 2113 2114 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2115 // generated from __builtin_eh_return (offset, handler) 2116 // The effect of this is to adjust the stack pointer by "offset" 2117 // and then branch to "handler". 2118 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2119 const { 2120 MachineFunction &MF = DAG.getMachineFunction(); 2121 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2122 2123 MipsFI->setCallsEhReturn(); 2124 SDValue Chain = Op.getOperand(0); 2125 SDValue Offset = Op.getOperand(1); 2126 SDValue Handler = Op.getOperand(2); 2127 SDLoc DL(Op); 2128 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2129 2130 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2131 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2132 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2133 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2134 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2135 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2136 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2137 DAG.getRegister(OffsetReg, Ty), 2138 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2139 Chain.getValue(1)); 2140 } 2141 2142 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2143 SelectionDAG &DAG) const { 2144 // FIXME: Need pseudo-fence for 'singlethread' fences 2145 // FIXME: Set SType for weaker fences where supported/appropriate. 2146 unsigned SType = 0; 2147 SDLoc DL(Op); 2148 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2149 DAG.getConstant(SType, DL, MVT::i32)); 2150 } 2151 2152 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2153 SelectionDAG &DAG) const { 2154 SDLoc DL(Op); 2155 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2156 2157 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2158 SDValue Shamt = Op.getOperand(2); 2159 // if shamt < (VT.bits): 2160 // lo = (shl lo, shamt) 2161 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2162 // else: 2163 // lo = 0 2164 // hi = (shl lo, shamt[4:0]) 2165 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2166 DAG.getConstant(-1, DL, MVT::i32)); 2167 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2168 DAG.getConstant(1, DL, VT)); 2169 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2170 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2171 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2172 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2173 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2174 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2175 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2176 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2177 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2178 2179 SDValue Ops[2] = {Lo, Hi}; 2180 return DAG.getMergeValues(Ops, DL); 2181 } 2182 2183 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2184 bool IsSRA) const { 2185 SDLoc DL(Op); 2186 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2187 SDValue Shamt = Op.getOperand(2); 2188 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2189 2190 // if shamt < (VT.bits): 2191 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2192 // if isSRA: 2193 // hi = (sra hi, shamt) 2194 // else: 2195 // hi = (srl hi, shamt) 2196 // else: 2197 // if isSRA: 2198 // lo = (sra hi, shamt[4:0]) 2199 // hi = (sra hi, 31) 2200 // else: 2201 // lo = (srl hi, shamt[4:0]) 2202 // hi = 0 2203 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2204 DAG.getConstant(-1, DL, MVT::i32)); 2205 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2206 DAG.getConstant(1, DL, VT)); 2207 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2208 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2209 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2210 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2211 DL, VT, Hi, Shamt); 2212 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2213 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2214 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2215 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2216 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2217 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2218 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2219 2220 SDValue Ops[2] = {Lo, Hi}; 2221 return DAG.getMergeValues(Ops, DL); 2222 } 2223 2224 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2225 SDValue Chain, SDValue Src, unsigned Offset) { 2226 SDValue Ptr = LD->getBasePtr(); 2227 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2228 EVT BasePtrVT = Ptr.getValueType(); 2229 SDLoc DL(LD); 2230 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2231 2232 if (Offset) 2233 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2234 DAG.getConstant(Offset, DL, BasePtrVT)); 2235 2236 SDValue Ops[] = { Chain, Ptr, Src }; 2237 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2238 LD->getMemOperand()); 2239 } 2240 2241 // Expand an unaligned 32 or 64-bit integer load node. 2242 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2243 LoadSDNode *LD = cast<LoadSDNode>(Op); 2244 EVT MemVT = LD->getMemoryVT(); 2245 2246 if (Subtarget.systemSupportsUnalignedAccess()) 2247 return Op; 2248 2249 // Return if load is aligned or if MemVT is neither i32 nor i64. 2250 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2251 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2252 return SDValue(); 2253 2254 bool IsLittle = Subtarget.isLittle(); 2255 EVT VT = Op.getValueType(); 2256 ISD::LoadExtType ExtType = LD->getExtensionType(); 2257 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2258 2259 assert((VT == MVT::i32) || (VT == MVT::i64)); 2260 2261 // Expand 2262 // (set dst, (i64 (load baseptr))) 2263 // to 2264 // (set tmp, (ldl (add baseptr, 7), undef)) 2265 // (set dst, (ldr baseptr, tmp)) 2266 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2267 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2268 IsLittle ? 7 : 0); 2269 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2270 IsLittle ? 0 : 7); 2271 } 2272 2273 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2274 IsLittle ? 3 : 0); 2275 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2276 IsLittle ? 0 : 3); 2277 2278 // Expand 2279 // (set dst, (i32 (load baseptr))) or 2280 // (set dst, (i64 (sextload baseptr))) or 2281 // (set dst, (i64 (extload baseptr))) 2282 // to 2283 // (set tmp, (lwl (add baseptr, 3), undef)) 2284 // (set dst, (lwr baseptr, tmp)) 2285 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2286 (ExtType == ISD::EXTLOAD)) 2287 return LWR; 2288 2289 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2290 2291 // Expand 2292 // (set dst, (i64 (zextload baseptr))) 2293 // to 2294 // (set tmp0, (lwl (add baseptr, 3), undef)) 2295 // (set tmp1, (lwr baseptr, tmp0)) 2296 // (set tmp2, (shl tmp1, 32)) 2297 // (set dst, (srl tmp2, 32)) 2298 SDLoc DL(LD); 2299 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2300 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2301 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2302 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2303 return DAG.getMergeValues(Ops, DL); 2304 } 2305 2306 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2307 SDValue Chain, unsigned Offset) { 2308 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2309 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2310 SDLoc DL(SD); 2311 SDVTList VTList = DAG.getVTList(MVT::Other); 2312 2313 if (Offset) 2314 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2315 DAG.getConstant(Offset, DL, BasePtrVT)); 2316 2317 SDValue Ops[] = { Chain, Value, Ptr }; 2318 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2319 SD->getMemOperand()); 2320 } 2321 2322 // Expand an unaligned 32 or 64-bit integer store node. 2323 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2324 bool IsLittle) { 2325 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2326 EVT VT = Value.getValueType(); 2327 2328 // Expand 2329 // (store val, baseptr) or 2330 // (truncstore val, baseptr) 2331 // to 2332 // (swl val, (add baseptr, 3)) 2333 // (swr val, baseptr) 2334 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2335 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2336 IsLittle ? 3 : 0); 2337 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2338 } 2339 2340 assert(VT == MVT::i64); 2341 2342 // Expand 2343 // (store val, baseptr) 2344 // to 2345 // (sdl val, (add baseptr, 7)) 2346 // (sdr val, baseptr) 2347 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2348 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2349 } 2350 2351 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2352 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2353 SDValue Val = SD->getValue(); 2354 2355 if (Val.getOpcode() != ISD::FP_TO_SINT) 2356 return SDValue(); 2357 2358 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2359 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2360 Val.getOperand(0)); 2361 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2362 SD->getPointerInfo(), SD->getAlignment(), 2363 SD->getMemOperand()->getFlags()); 2364 } 2365 2366 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2367 StoreSDNode *SD = cast<StoreSDNode>(Op); 2368 EVT MemVT = SD->getMemoryVT(); 2369 2370 // Lower unaligned integer stores. 2371 if (!Subtarget.systemSupportsUnalignedAccess() && 2372 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2373 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2374 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2375 2376 return lowerFP_TO_SINT_STORE(SD, DAG); 2377 } 2378 2379 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2380 SelectionDAG &DAG) const { 2381 2382 // Return a fixed StackObject with offset 0 which points to the old stack 2383 // pointer. 2384 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2385 EVT ValTy = Op->getValueType(0); 2386 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2387 return DAG.getFrameIndex(FI, ValTy); 2388 } 2389 2390 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2391 SelectionDAG &DAG) const { 2392 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2393 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2394 Op.getOperand(0)); 2395 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2396 } 2397 2398 //===----------------------------------------------------------------------===// 2399 // Calling Convention Implementation 2400 //===----------------------------------------------------------------------===// 2401 2402 //===----------------------------------------------------------------------===// 2403 // TODO: Implement a generic logic using tblgen that can support this. 2404 // Mips O32 ABI rules: 2405 // --- 2406 // i32 - Passed in A0, A1, A2, A3 and stack 2407 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2408 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2409 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2410 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2411 // not used, it must be shadowed. If only A3 is available, shadow it and 2412 // go to stack. 2413 // 2414 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2415 //===----------------------------------------------------------------------===// 2416 2417 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2418 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2419 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2420 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2421 State.getMachineFunction().getSubtarget()); 2422 2423 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2424 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2425 2426 // Do not process byval args here. 2427 if (ArgFlags.isByVal()) 2428 return true; 2429 2430 // Promote i8 and i16 2431 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2432 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2433 LocVT = MVT::i32; 2434 if (ArgFlags.isSExt()) 2435 LocInfo = CCValAssign::SExtUpper; 2436 else if (ArgFlags.isZExt()) 2437 LocInfo = CCValAssign::ZExtUpper; 2438 else 2439 LocInfo = CCValAssign::AExtUpper; 2440 } 2441 } 2442 2443 // Promote i8 and i16 2444 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2445 LocVT = MVT::i32; 2446 if (ArgFlags.isSExt()) 2447 LocInfo = CCValAssign::SExt; 2448 else if (ArgFlags.isZExt()) 2449 LocInfo = CCValAssign::ZExt; 2450 else 2451 LocInfo = CCValAssign::AExt; 2452 } 2453 2454 unsigned Reg; 2455 2456 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2457 // is true: function is vararg, argument is 3rd or higher, there is previous 2458 // argument which is not f32 or f64. 2459 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2460 State.getFirstUnallocated(F32Regs) != ValNo; 2461 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2462 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2463 2464 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2465 Reg = State.AllocateReg(IntRegs); 2466 // If this is the first part of an i64 arg, 2467 // the allocated register must be either A0 or A2. 2468 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2469 Reg = State.AllocateReg(IntRegs); 2470 LocVT = MVT::i32; 2471 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2472 // Allocate int register and shadow next int register. If first 2473 // available register is Mips::A1 or Mips::A3, shadow it too. 2474 Reg = State.AllocateReg(IntRegs); 2475 if (Reg == Mips::A1 || Reg == Mips::A3) 2476 Reg = State.AllocateReg(IntRegs); 2477 State.AllocateReg(IntRegs); 2478 LocVT = MVT::i32; 2479 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2480 // we are guaranteed to find an available float register 2481 if (ValVT == MVT::f32) { 2482 Reg = State.AllocateReg(F32Regs); 2483 // Shadow int register 2484 State.AllocateReg(IntRegs); 2485 } else { 2486 Reg = State.AllocateReg(F64Regs); 2487 // Shadow int registers 2488 unsigned Reg2 = State.AllocateReg(IntRegs); 2489 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2490 State.AllocateReg(IntRegs); 2491 State.AllocateReg(IntRegs); 2492 } 2493 } else 2494 llvm_unreachable("Cannot handle this ValVT."); 2495 2496 if (!Reg) { 2497 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2498 OrigAlign); 2499 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2500 } else 2501 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2502 2503 return false; 2504 } 2505 2506 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2507 MVT LocVT, CCValAssign::LocInfo LocInfo, 2508 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2509 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2510 2511 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2512 } 2513 2514 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2515 MVT LocVT, CCValAssign::LocInfo LocInfo, 2516 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2517 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2518 2519 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2520 } 2521 2522 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2523 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2524 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2525 2526 #include "MipsGenCallingConv.inc" 2527 2528 //===----------------------------------------------------------------------===// 2529 // Call Calling Convention Implementation 2530 //===----------------------------------------------------------------------===// 2531 2532 // Return next O32 integer argument register. 2533 static unsigned getNextIntArgReg(unsigned Reg) { 2534 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2535 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2536 } 2537 2538 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2539 SDValue Chain, SDValue Arg, 2540 const SDLoc &DL, bool IsTailCall, 2541 SelectionDAG &DAG) const { 2542 if (!IsTailCall) { 2543 SDValue PtrOff = 2544 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2545 DAG.getIntPtrConstant(Offset, DL)); 2546 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2547 } 2548 2549 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2550 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2551 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2552 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2553 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2554 } 2555 2556 void MipsTargetLowering:: 2557 getOpndList(SmallVectorImpl<SDValue> &Ops, 2558 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2559 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2560 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2561 SDValue Chain) const { 2562 // Insert node "GP copy globalreg" before call to function. 2563 // 2564 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2565 // in PIC mode) allow symbols to be resolved via lazy binding. 2566 // The lazy binding stub requires GP to point to the GOT. 2567 // Note that we don't need GP to point to the GOT for indirect calls 2568 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2569 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2570 // used for the function (that is, Mips linker doesn't generate lazy binding 2571 // stub for a function whose address is taken in the program). 2572 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2573 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2574 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2575 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2576 } 2577 2578 // Build a sequence of copy-to-reg nodes chained together with token 2579 // chain and flag operands which copy the outgoing args into registers. 2580 // The InFlag in necessary since all emitted instructions must be 2581 // stuck together. 2582 SDValue InFlag; 2583 2584 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2585 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2586 RegsToPass[i].second, InFlag); 2587 InFlag = Chain.getValue(1); 2588 } 2589 2590 // Add argument registers to the end of the list so that they are 2591 // known live into the call. 2592 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2593 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2594 RegsToPass[i].second.getValueType())); 2595 2596 // Add a register mask operand representing the call-preserved registers. 2597 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2598 const uint32_t *Mask = 2599 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2600 assert(Mask && "Missing call preserved mask for calling convention"); 2601 if (Subtarget.inMips16HardFloat()) { 2602 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2603 llvm::StringRef Sym = G->getGlobal()->getName(); 2604 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2605 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2606 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2607 } 2608 } 2609 } 2610 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2611 2612 if (InFlag.getNode()) 2613 Ops.push_back(InFlag); 2614 } 2615 2616 /// LowerCall - functions arguments are copied from virtual regs to 2617 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2618 SDValue 2619 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2620 SmallVectorImpl<SDValue> &InVals) const { 2621 SelectionDAG &DAG = CLI.DAG; 2622 SDLoc DL = CLI.DL; 2623 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2624 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2625 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2626 SDValue Chain = CLI.Chain; 2627 SDValue Callee = CLI.Callee; 2628 bool &IsTailCall = CLI.IsTailCall; 2629 CallingConv::ID CallConv = CLI.CallConv; 2630 bool IsVarArg = CLI.IsVarArg; 2631 2632 MachineFunction &MF = DAG.getMachineFunction(); 2633 MachineFrameInfo &MFI = MF.getFrameInfo(); 2634 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2635 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2636 bool IsPIC = isPositionIndependent(); 2637 2638 // Analyze operands of the call, assigning locations to each operand. 2639 SmallVector<CCValAssign, 16> ArgLocs; 2640 MipsCCState CCInfo( 2641 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2642 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2643 2644 // Allocate the reserved argument area. It seems strange to do this from the 2645 // caller side but removing it breaks the frame size calculation. 2646 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2647 2648 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode()); 2649 2650 // Get a count of how many bytes are to be pushed on the stack. 2651 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2652 2653 // Check if it's really possible to do a tail call. Restrict it to functions 2654 // that are part of this compilation unit. 2655 bool InternalLinkage = false; 2656 if (IsTailCall) { 2657 IsTailCall = isEligibleForTailCallOptimization( 2658 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2659 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2660 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 2661 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 2662 G->getGlobal()->hasPrivateLinkage() || 2663 G->getGlobal()->hasHiddenVisibility() || 2664 G->getGlobal()->hasProtectedVisibility()); 2665 } 2666 } 2667 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2668 report_fatal_error("failed to perform tail call elimination on a call " 2669 "site marked musttail"); 2670 2671 if (IsTailCall) 2672 ++NumTailCalls; 2673 2674 // Chain is the output chain of the last Load/Store or CopyToReg node. 2675 // ByValChain is the output chain of the last Memcpy node created for copying 2676 // byval arguments to the stack. 2677 unsigned StackAlignment = TFL->getStackAlignment(); 2678 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 2679 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 2680 2681 if (!IsTailCall) 2682 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2683 2684 SDValue StackPtr = 2685 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 2686 getPointerTy(DAG.getDataLayout())); 2687 2688 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2689 SmallVector<SDValue, 8> MemOpChains; 2690 2691 CCInfo.rewindByValRegsInfo(); 2692 2693 // Walk the register/memloc assignments, inserting copies/loads. 2694 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2695 SDValue Arg = OutVals[i]; 2696 CCValAssign &VA = ArgLocs[i]; 2697 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2698 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2699 bool UseUpperBits = false; 2700 2701 // ByVal Arg. 2702 if (Flags.isByVal()) { 2703 unsigned FirstByValReg, LastByValReg; 2704 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2705 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2706 2707 assert(Flags.getByValSize() && 2708 "ByVal args of size 0 should have been ignored by front-end."); 2709 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2710 assert(!IsTailCall && 2711 "Do not tail-call optimize if there is a byval argument."); 2712 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2713 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 2714 VA); 2715 CCInfo.nextInRegsParam(); 2716 continue; 2717 } 2718 2719 // Promote the value if needed. 2720 switch (VA.getLocInfo()) { 2721 default: 2722 llvm_unreachable("Unknown loc info!"); 2723 case CCValAssign::Full: 2724 if (VA.isRegLoc()) { 2725 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2726 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2727 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2728 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2729 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2730 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2731 Arg, DAG.getConstant(0, DL, MVT::i32)); 2732 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2733 Arg, DAG.getConstant(1, DL, MVT::i32)); 2734 if (!Subtarget.isLittle()) 2735 std::swap(Lo, Hi); 2736 unsigned LocRegLo = VA.getLocReg(); 2737 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2738 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2739 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2740 continue; 2741 } 2742 } 2743 break; 2744 case CCValAssign::BCvt: 2745 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2746 break; 2747 case CCValAssign::SExtUpper: 2748 UseUpperBits = true; 2749 LLVM_FALLTHROUGH; 2750 case CCValAssign::SExt: 2751 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2752 break; 2753 case CCValAssign::ZExtUpper: 2754 UseUpperBits = true; 2755 LLVM_FALLTHROUGH; 2756 case CCValAssign::ZExt: 2757 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2758 break; 2759 case CCValAssign::AExtUpper: 2760 UseUpperBits = true; 2761 LLVM_FALLTHROUGH; 2762 case CCValAssign::AExt: 2763 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2764 break; 2765 } 2766 2767 if (UseUpperBits) { 2768 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 2769 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2770 Arg = DAG.getNode( 2771 ISD::SHL, DL, VA.getLocVT(), Arg, 2772 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2773 } 2774 2775 // Arguments that can be passed on register must be kept at 2776 // RegsToPass vector 2777 if (VA.isRegLoc()) { 2778 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2779 continue; 2780 } 2781 2782 // Register can't get to this point... 2783 assert(VA.isMemLoc()); 2784 2785 // emit ISD::STORE whichs stores the 2786 // parameter value to a stack Location 2787 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2788 Chain, Arg, DL, IsTailCall, DAG)); 2789 } 2790 2791 // Transform all store nodes into one single node because all store 2792 // nodes are independent of each other. 2793 if (!MemOpChains.empty()) 2794 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 2795 2796 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2797 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2798 // node so that legalize doesn't hack it. 2799 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to 2800 // jalr $25 2801 SDValue CalleeLo; 2802 EVT Ty = Callee.getValueType(); 2803 bool GlobalOrExternal = false, IsCallReloc = false; 2804 2805 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2806 if (IsPICCall) { 2807 const GlobalValue *Val = G->getGlobal(); 2808 InternalLinkage = Val->hasInternalLinkage(); 2809 2810 if (InternalLinkage) 2811 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2812 else if (LargeGOT) { 2813 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2814 MipsII::MO_CALL_LO16, Chain, 2815 FuncInfo->callPtrInfo(Val)); 2816 IsCallReloc = true; 2817 } else { 2818 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2819 FuncInfo->callPtrInfo(Val)); 2820 IsCallReloc = true; 2821 } 2822 } else 2823 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 2824 getPointerTy(DAG.getDataLayout()), 0, 2825 MipsII::MO_NO_FLAG); 2826 GlobalOrExternal = true; 2827 } 2828 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2829 const char *Sym = S->getSymbol(); 2830 2831 if (!ABI.IsN64() && !IsPIC) // !N64 && static 2832 Callee = DAG.getTargetExternalSymbol( 2833 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 2834 else if (LargeGOT) { 2835 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2836 MipsII::MO_CALL_LO16, Chain, 2837 FuncInfo->callPtrInfo(Sym)); 2838 IsCallReloc = true; 2839 } else { // N64 || PIC 2840 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2841 FuncInfo->callPtrInfo(Sym)); 2842 IsCallReloc = true; 2843 } 2844 2845 GlobalOrExternal = true; 2846 } 2847 2848 SmallVector<SDValue, 8> Ops(1, Chain); 2849 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2850 2851 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2852 IsCallReloc, CLI, Callee, Chain); 2853 2854 if (IsTailCall) { 2855 MF.getFrameInfo().setHasTailCall(); 2856 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 2857 } 2858 2859 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 2860 SDValue InFlag = Chain.getValue(1); 2861 2862 // Create the CALLSEQ_END node. 2863 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2864 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 2865 InFlag = Chain.getValue(1); 2866 2867 // Handle result values, copying them out of physregs into vregs that we 2868 // return. 2869 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 2870 InVals, CLI); 2871 } 2872 2873 /// LowerCallResult - Lower the result values of a call into the 2874 /// appropriate copies out of appropriate physical registers. 2875 SDValue MipsTargetLowering::LowerCallResult( 2876 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 2877 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 2878 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 2879 TargetLowering::CallLoweringInfo &CLI) const { 2880 // Assign locations to each value returned by this call. 2881 SmallVector<CCValAssign, 16> RVLocs; 2882 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 2883 *DAG.getContext()); 2884 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI); 2885 2886 // Copy all of the result registers out of their specified physreg. 2887 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2888 CCValAssign &VA = RVLocs[i]; 2889 assert(VA.isRegLoc() && "Can only return in registers!"); 2890 2891 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2892 RVLocs[i].getLocVT(), InFlag); 2893 Chain = Val.getValue(1); 2894 InFlag = Val.getValue(2); 2895 2896 if (VA.isUpperBitsInLoc()) { 2897 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 2898 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2899 unsigned Shift = 2900 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2901 Val = DAG.getNode( 2902 Shift, DL, VA.getLocVT(), Val, 2903 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2904 } 2905 2906 switch (VA.getLocInfo()) { 2907 default: 2908 llvm_unreachable("Unknown loc info!"); 2909 case CCValAssign::Full: 2910 break; 2911 case CCValAssign::BCvt: 2912 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 2913 break; 2914 case CCValAssign::AExt: 2915 case CCValAssign::AExtUpper: 2916 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2917 break; 2918 case CCValAssign::ZExt: 2919 case CCValAssign::ZExtUpper: 2920 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 2921 DAG.getValueType(VA.getValVT())); 2922 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2923 break; 2924 case CCValAssign::SExt: 2925 case CCValAssign::SExtUpper: 2926 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 2927 DAG.getValueType(VA.getValVT())); 2928 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2929 break; 2930 } 2931 2932 InVals.push_back(Val); 2933 } 2934 2935 return Chain; 2936 } 2937 2938 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 2939 EVT ArgVT, const SDLoc &DL, 2940 SelectionDAG &DAG) { 2941 MVT LocVT = VA.getLocVT(); 2942 EVT ValVT = VA.getValVT(); 2943 2944 // Shift into the upper bits if necessary. 2945 switch (VA.getLocInfo()) { 2946 default: 2947 break; 2948 case CCValAssign::AExtUpper: 2949 case CCValAssign::SExtUpper: 2950 case CCValAssign::ZExtUpper: { 2951 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 2952 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2953 unsigned Opcode = 2954 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2955 Val = DAG.getNode( 2956 Opcode, DL, VA.getLocVT(), Val, 2957 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2958 break; 2959 } 2960 } 2961 2962 // If this is an value smaller than the argument slot size (32-bit for O32, 2963 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 2964 // size. Extract the value and insert any appropriate assertions regarding 2965 // sign/zero extension. 2966 switch (VA.getLocInfo()) { 2967 default: 2968 llvm_unreachable("Unknown loc info!"); 2969 case CCValAssign::Full: 2970 break; 2971 case CCValAssign::AExtUpper: 2972 case CCValAssign::AExt: 2973 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2974 break; 2975 case CCValAssign::SExtUpper: 2976 case CCValAssign::SExt: 2977 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2978 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2979 break; 2980 case CCValAssign::ZExtUpper: 2981 case CCValAssign::ZExt: 2982 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2983 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2984 break; 2985 case CCValAssign::BCvt: 2986 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 2987 break; 2988 } 2989 2990 return Val; 2991 } 2992 2993 //===----------------------------------------------------------------------===// 2994 // Formal Arguments Calling Convention Implementation 2995 //===----------------------------------------------------------------------===// 2996 /// LowerFormalArguments - transform physical registers into virtual registers 2997 /// and generate load operations for arguments places on the stack. 2998 SDValue MipsTargetLowering::LowerFormalArguments( 2999 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3000 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3001 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3002 MachineFunction &MF = DAG.getMachineFunction(); 3003 MachineFrameInfo &MFI = MF.getFrameInfo(); 3004 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3005 3006 MipsFI->setVarArgsFrameIndex(0); 3007 3008 // Used with vargs to acumulate store chains. 3009 std::vector<SDValue> OutChains; 3010 3011 // Assign locations to all of the incoming arguments. 3012 SmallVector<CCValAssign, 16> ArgLocs; 3013 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3014 *DAG.getContext()); 3015 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3016 const Function *Func = DAG.getMachineFunction().getFunction(); 3017 Function::const_arg_iterator FuncArg = Func->arg_begin(); 3018 3019 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty()) 3020 report_fatal_error( 3021 "Functions with the interrupt attribute cannot have arguments!"); 3022 3023 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3024 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3025 CCInfo.getInRegsParamsCount() > 0); 3026 3027 unsigned CurArgIdx = 0; 3028 CCInfo.rewindByValRegsInfo(); 3029 3030 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3031 CCValAssign &VA = ArgLocs[i]; 3032 if (Ins[i].isOrigArg()) { 3033 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3034 CurArgIdx = Ins[i].getOrigArgIndex(); 3035 } 3036 EVT ValVT = VA.getValVT(); 3037 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3038 bool IsRegLoc = VA.isRegLoc(); 3039 3040 if (Flags.isByVal()) { 3041 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3042 unsigned FirstByValReg, LastByValReg; 3043 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3044 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3045 3046 assert(Flags.getByValSize() && 3047 "ByVal args of size 0 should have been ignored by front-end."); 3048 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3049 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3050 FirstByValReg, LastByValReg, VA, CCInfo); 3051 CCInfo.nextInRegsParam(); 3052 continue; 3053 } 3054 3055 // Arguments stored on registers 3056 if (IsRegLoc) { 3057 MVT RegVT = VA.getLocVT(); 3058 unsigned ArgReg = VA.getLocReg(); 3059 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3060 3061 // Transform the arguments stored on 3062 // physical registers into virtual ones 3063 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3064 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3065 3066 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3067 3068 // Handle floating point arguments passed in integer registers and 3069 // long double arguments passed in floating point registers. 3070 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3071 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3072 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3073 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3074 else if (ABI.IsO32() && RegVT == MVT::i32 && 3075 ValVT == MVT::f64) { 3076 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3077 getNextIntArgReg(ArgReg), RC); 3078 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3079 if (!Subtarget.isLittle()) 3080 std::swap(ArgValue, ArgValue2); 3081 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3082 ArgValue, ArgValue2); 3083 } 3084 3085 InVals.push_back(ArgValue); 3086 } else { // VA.isRegLoc() 3087 MVT LocVT = VA.getLocVT(); 3088 3089 if (ABI.IsO32()) { 3090 // We ought to be able to use LocVT directly but O32 sets it to i32 3091 // when allocating floating point values to integer registers. 3092 // This shouldn't influence how we load the value into registers unless 3093 // we are targeting softfloat. 3094 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3095 LocVT = VA.getValVT(); 3096 } 3097 3098 // sanity check 3099 assert(VA.isMemLoc()); 3100 3101 // The stack pointer offset is relative to the caller stack frame. 3102 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3103 VA.getLocMemOffset(), true); 3104 3105 // Create load nodes to retrieve arguments from the stack 3106 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3107 SDValue ArgValue = DAG.getLoad( 3108 LocVT, DL, Chain, FIN, 3109 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3110 OutChains.push_back(ArgValue.getValue(1)); 3111 3112 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3113 3114 InVals.push_back(ArgValue); 3115 } 3116 } 3117 3118 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3119 // The mips ABIs for returning structs by value requires that we copy 3120 // the sret argument into $v0 for the return. Save the argument into 3121 // a virtual register so that we can access it from the return points. 3122 if (Ins[i].Flags.isSRet()) { 3123 unsigned Reg = MipsFI->getSRetReturnReg(); 3124 if (!Reg) { 3125 Reg = MF.getRegInfo().createVirtualRegister( 3126 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3127 MipsFI->setSRetReturnReg(Reg); 3128 } 3129 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3130 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3131 break; 3132 } 3133 } 3134 3135 if (IsVarArg) 3136 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3137 3138 // All stores are grouped in one node to allow the matching between 3139 // the size of Ins and InVals. This only happens when on varg functions 3140 if (!OutChains.empty()) { 3141 OutChains.push_back(Chain); 3142 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3143 } 3144 3145 return Chain; 3146 } 3147 3148 //===----------------------------------------------------------------------===// 3149 // Return Value Calling Convention Implementation 3150 //===----------------------------------------------------------------------===// 3151 3152 bool 3153 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3154 MachineFunction &MF, bool IsVarArg, 3155 const SmallVectorImpl<ISD::OutputArg> &Outs, 3156 LLVMContext &Context) const { 3157 SmallVector<CCValAssign, 16> RVLocs; 3158 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3159 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3160 } 3161 3162 bool 3163 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3164 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { 3165 if (Type == MVT::i32) 3166 return true; 3167 } 3168 return IsSigned; 3169 } 3170 3171 SDValue 3172 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3173 const SDLoc &DL, 3174 SelectionDAG &DAG) const { 3175 3176 MachineFunction &MF = DAG.getMachineFunction(); 3177 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3178 3179 MipsFI->setISR(); 3180 3181 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3182 } 3183 3184 SDValue 3185 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3186 bool IsVarArg, 3187 const SmallVectorImpl<ISD::OutputArg> &Outs, 3188 const SmallVectorImpl<SDValue> &OutVals, 3189 const SDLoc &DL, SelectionDAG &DAG) const { 3190 // CCValAssign - represent the assignment of 3191 // the return value to a location 3192 SmallVector<CCValAssign, 16> RVLocs; 3193 MachineFunction &MF = DAG.getMachineFunction(); 3194 3195 // CCState - Info about the registers and stack slot. 3196 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3197 3198 // Analyze return values. 3199 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3200 3201 SDValue Flag; 3202 SmallVector<SDValue, 4> RetOps(1, Chain); 3203 3204 // Copy the result values into the output registers. 3205 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3206 SDValue Val = OutVals[i]; 3207 CCValAssign &VA = RVLocs[i]; 3208 assert(VA.isRegLoc() && "Can only return in registers!"); 3209 bool UseUpperBits = false; 3210 3211 switch (VA.getLocInfo()) { 3212 default: 3213 llvm_unreachable("Unknown loc info!"); 3214 case CCValAssign::Full: 3215 break; 3216 case CCValAssign::BCvt: 3217 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3218 break; 3219 case CCValAssign::AExtUpper: 3220 UseUpperBits = true; 3221 LLVM_FALLTHROUGH; 3222 case CCValAssign::AExt: 3223 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3224 break; 3225 case CCValAssign::ZExtUpper: 3226 UseUpperBits = true; 3227 LLVM_FALLTHROUGH; 3228 case CCValAssign::ZExt: 3229 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3230 break; 3231 case CCValAssign::SExtUpper: 3232 UseUpperBits = true; 3233 LLVM_FALLTHROUGH; 3234 case CCValAssign::SExt: 3235 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3236 break; 3237 } 3238 3239 if (UseUpperBits) { 3240 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3241 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3242 Val = DAG.getNode( 3243 ISD::SHL, DL, VA.getLocVT(), Val, 3244 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3245 } 3246 3247 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3248 3249 // Guarantee that all emitted copies are stuck together with flags. 3250 Flag = Chain.getValue(1); 3251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3252 } 3253 3254 // The mips ABIs for returning structs by value requires that we copy 3255 // the sret argument into $v0 for the return. We saved the argument into 3256 // a virtual register in the entry block, so now we copy the value out 3257 // and into $v0. 3258 if (MF.getFunction()->hasStructRetAttr()) { 3259 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3260 unsigned Reg = MipsFI->getSRetReturnReg(); 3261 3262 if (!Reg) 3263 llvm_unreachable("sret virtual register not created in the entry block"); 3264 SDValue Val = 3265 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3266 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3267 3268 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3269 Flag = Chain.getValue(1); 3270 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3271 } 3272 3273 RetOps[0] = Chain; // Update chain. 3274 3275 // Add the flag if we have it. 3276 if (Flag.getNode()) 3277 RetOps.push_back(Flag); 3278 3279 // ISRs must use "eret". 3280 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt")) 3281 return LowerInterruptReturn(RetOps, DL, DAG); 3282 3283 // Standard return on Mips is a "jr $ra" 3284 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3285 } 3286 3287 //===----------------------------------------------------------------------===// 3288 // Mips Inline Assembly Support 3289 //===----------------------------------------------------------------------===// 3290 3291 /// getConstraintType - Given a constraint letter, return the type of 3292 /// constraint it is for this target. 3293 MipsTargetLowering::ConstraintType 3294 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3295 // Mips specific constraints 3296 // GCC config/mips/constraints.md 3297 // 3298 // 'd' : An address register. Equivalent to r 3299 // unless generating MIPS16 code. 3300 // 'y' : Equivalent to r; retained for 3301 // backwards compatibility. 3302 // 'c' : A register suitable for use in an indirect 3303 // jump. This will always be $25 for -mabicalls. 3304 // 'l' : The lo register. 1 word storage. 3305 // 'x' : The hilo register pair. Double word storage. 3306 if (Constraint.size() == 1) { 3307 switch (Constraint[0]) { 3308 default : break; 3309 case 'd': 3310 case 'y': 3311 case 'f': 3312 case 'c': 3313 case 'l': 3314 case 'x': 3315 return C_RegisterClass; 3316 case 'R': 3317 return C_Memory; 3318 } 3319 } 3320 3321 if (Constraint == "ZC") 3322 return C_Memory; 3323 3324 return TargetLowering::getConstraintType(Constraint); 3325 } 3326 3327 /// Examine constraint type and operand type and determine a weight value. 3328 /// This object must already have been set up with the operand type 3329 /// and the current alternative constraint selected. 3330 TargetLowering::ConstraintWeight 3331 MipsTargetLowering::getSingleConstraintMatchWeight( 3332 AsmOperandInfo &info, const char *constraint) const { 3333 ConstraintWeight weight = CW_Invalid; 3334 Value *CallOperandVal = info.CallOperandVal; 3335 // If we don't have a value, we can't do a match, 3336 // but allow it at the lowest weight. 3337 if (!CallOperandVal) 3338 return CW_Default; 3339 Type *type = CallOperandVal->getType(); 3340 // Look at the constraint type. 3341 switch (*constraint) { 3342 default: 3343 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3344 break; 3345 case 'd': 3346 case 'y': 3347 if (type->isIntegerTy()) 3348 weight = CW_Register; 3349 break; 3350 case 'f': // FPU or MSA register 3351 if (Subtarget.hasMSA() && type->isVectorTy() && 3352 cast<VectorType>(type)->getBitWidth() == 128) 3353 weight = CW_Register; 3354 else if (type->isFloatTy()) 3355 weight = CW_Register; 3356 break; 3357 case 'c': // $25 for indirect jumps 3358 case 'l': // lo register 3359 case 'x': // hilo register pair 3360 if (type->isIntegerTy()) 3361 weight = CW_SpecificReg; 3362 break; 3363 case 'I': // signed 16 bit immediate 3364 case 'J': // integer zero 3365 case 'K': // unsigned 16 bit immediate 3366 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3367 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3368 case 'O': // signed 15 bit immediate (+- 16383) 3369 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3370 if (isa<ConstantInt>(CallOperandVal)) 3371 weight = CW_Constant; 3372 break; 3373 case 'R': 3374 weight = CW_Memory; 3375 break; 3376 } 3377 return weight; 3378 } 3379 3380 /// This is a helper function to parse a physical register string and split it 3381 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3382 /// that is returned indicates whether parsing was successful. The second flag 3383 /// is true if the numeric part exists. 3384 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3385 unsigned long long &Reg) { 3386 if (C.front() != '{' || C.back() != '}') 3387 return std::make_pair(false, false); 3388 3389 // Search for the first numeric character. 3390 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3391 I = std::find_if(B, E, isdigit); 3392 3393 Prefix = StringRef(B, I - B); 3394 3395 // The second flag is set to false if no numeric characters were found. 3396 if (I == E) 3397 return std::make_pair(true, false); 3398 3399 // Parse the numeric characters. 3400 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3401 true); 3402 } 3403 3404 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3405 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3406 const TargetRegisterInfo *TRI = 3407 Subtarget.getRegisterInfo(); 3408 const TargetRegisterClass *RC; 3409 StringRef Prefix; 3410 unsigned long long Reg; 3411 3412 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3413 3414 if (!R.first) 3415 return std::make_pair(0U, nullptr); 3416 3417 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3418 // No numeric characters follow "hi" or "lo". 3419 if (R.second) 3420 return std::make_pair(0U, nullptr); 3421 3422 RC = TRI->getRegClass(Prefix == "hi" ? 3423 Mips::HI32RegClassID : Mips::LO32RegClassID); 3424 return std::make_pair(*(RC->begin()), RC); 3425 } else if (Prefix.startswith("$msa")) { 3426 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3427 3428 // No numeric characters follow the name. 3429 if (R.second) 3430 return std::make_pair(0U, nullptr); 3431 3432 Reg = StringSwitch<unsigned long long>(Prefix) 3433 .Case("$msair", Mips::MSAIR) 3434 .Case("$msacsr", Mips::MSACSR) 3435 .Case("$msaaccess", Mips::MSAAccess) 3436 .Case("$msasave", Mips::MSASave) 3437 .Case("$msamodify", Mips::MSAModify) 3438 .Case("$msarequest", Mips::MSARequest) 3439 .Case("$msamap", Mips::MSAMap) 3440 .Case("$msaunmap", Mips::MSAUnmap) 3441 .Default(0); 3442 3443 if (!Reg) 3444 return std::make_pair(0U, nullptr); 3445 3446 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3447 return std::make_pair(Reg, RC); 3448 } 3449 3450 if (!R.second) 3451 return std::make_pair(0U, nullptr); 3452 3453 if (Prefix == "$f") { // Parse $f0-$f31. 3454 // If the size of FP registers is 64-bit or Reg is an even number, select 3455 // the 64-bit register class. Otherwise, select the 32-bit register class. 3456 if (VT == MVT::Other) 3457 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3458 3459 RC = getRegClassFor(VT); 3460 3461 if (RC == &Mips::AFGR64RegClass) { 3462 assert(Reg % 2 == 0); 3463 Reg >>= 1; 3464 } 3465 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3466 RC = TRI->getRegClass(Mips::FCCRegClassID); 3467 else if (Prefix == "$w") { // Parse $w0-$w31. 3468 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3469 } else { // Parse $0-$31. 3470 assert(Prefix == "$"); 3471 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3472 } 3473 3474 assert(Reg < RC->getNumRegs()); 3475 return std::make_pair(*(RC->begin() + Reg), RC); 3476 } 3477 3478 /// Given a register class constraint, like 'r', if this corresponds directly 3479 /// to an LLVM register class, return a register of 0 and the register class 3480 /// pointer. 3481 std::pair<unsigned, const TargetRegisterClass *> 3482 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3483 StringRef Constraint, 3484 MVT VT) const { 3485 if (Constraint.size() == 1) { 3486 switch (Constraint[0]) { 3487 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3488 case 'y': // Same as 'r'. Exists for compatibility. 3489 case 'r': 3490 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3491 if (Subtarget.inMips16Mode()) 3492 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3493 return std::make_pair(0U, &Mips::GPR32RegClass); 3494 } 3495 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3496 return std::make_pair(0U, &Mips::GPR32RegClass); 3497 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3498 return std::make_pair(0U, &Mips::GPR64RegClass); 3499 // This will generate an error message 3500 return std::make_pair(0U, nullptr); 3501 case 'f': // FPU or MSA register 3502 if (VT == MVT::v16i8) 3503 return std::make_pair(0U, &Mips::MSA128BRegClass); 3504 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3505 return std::make_pair(0U, &Mips::MSA128HRegClass); 3506 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3507 return std::make_pair(0U, &Mips::MSA128WRegClass); 3508 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3509 return std::make_pair(0U, &Mips::MSA128DRegClass); 3510 else if (VT == MVT::f32) 3511 return std::make_pair(0U, &Mips::FGR32RegClass); 3512 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3513 if (Subtarget.isFP64bit()) 3514 return std::make_pair(0U, &Mips::FGR64RegClass); 3515 return std::make_pair(0U, &Mips::AFGR64RegClass); 3516 } 3517 break; 3518 case 'c': // register suitable for indirect jump 3519 if (VT == MVT::i32) 3520 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3521 assert(VT == MVT::i64 && "Unexpected type."); 3522 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3523 case 'l': // register suitable for indirect jump 3524 if (VT == MVT::i32) 3525 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3526 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3527 case 'x': // register suitable for indirect jump 3528 // Fixme: Not triggering the use of both hi and low 3529 // This will generate an error message 3530 return std::make_pair(0U, nullptr); 3531 } 3532 } 3533 3534 std::pair<unsigned, const TargetRegisterClass *> R; 3535 R = parseRegForInlineAsmConstraint(Constraint, VT); 3536 3537 if (R.second) 3538 return R; 3539 3540 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3541 } 3542 3543 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3544 /// vector. If it is invalid, don't add anything to Ops. 3545 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3546 std::string &Constraint, 3547 std::vector<SDValue>&Ops, 3548 SelectionDAG &DAG) const { 3549 SDLoc DL(Op); 3550 SDValue Result; 3551 3552 // Only support length 1 constraints for now. 3553 if (Constraint.length() > 1) return; 3554 3555 char ConstraintLetter = Constraint[0]; 3556 switch (ConstraintLetter) { 3557 default: break; // This will fall through to the generic implementation 3558 case 'I': // Signed 16 bit constant 3559 // If this fails, the parent routine will give an error 3560 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3561 EVT Type = Op.getValueType(); 3562 int64_t Val = C->getSExtValue(); 3563 if (isInt<16>(Val)) { 3564 Result = DAG.getTargetConstant(Val, DL, Type); 3565 break; 3566 } 3567 } 3568 return; 3569 case 'J': // integer zero 3570 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3571 EVT Type = Op.getValueType(); 3572 int64_t Val = C->getZExtValue(); 3573 if (Val == 0) { 3574 Result = DAG.getTargetConstant(0, DL, Type); 3575 break; 3576 } 3577 } 3578 return; 3579 case 'K': // unsigned 16 bit immediate 3580 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3581 EVT Type = Op.getValueType(); 3582 uint64_t Val = (uint64_t)C->getZExtValue(); 3583 if (isUInt<16>(Val)) { 3584 Result = DAG.getTargetConstant(Val, DL, Type); 3585 break; 3586 } 3587 } 3588 return; 3589 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3590 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3591 EVT Type = Op.getValueType(); 3592 int64_t Val = C->getSExtValue(); 3593 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3594 Result = DAG.getTargetConstant(Val, DL, Type); 3595 break; 3596 } 3597 } 3598 return; 3599 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3600 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3601 EVT Type = Op.getValueType(); 3602 int64_t Val = C->getSExtValue(); 3603 if ((Val >= -65535) && (Val <= -1)) { 3604 Result = DAG.getTargetConstant(Val, DL, Type); 3605 break; 3606 } 3607 } 3608 return; 3609 case 'O': // signed 15 bit immediate 3610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3611 EVT Type = Op.getValueType(); 3612 int64_t Val = C->getSExtValue(); 3613 if ((isInt<15>(Val))) { 3614 Result = DAG.getTargetConstant(Val, DL, Type); 3615 break; 3616 } 3617 } 3618 return; 3619 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3620 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3621 EVT Type = Op.getValueType(); 3622 int64_t Val = C->getSExtValue(); 3623 if ((Val <= 65535) && (Val >= 1)) { 3624 Result = DAG.getTargetConstant(Val, DL, Type); 3625 break; 3626 } 3627 } 3628 return; 3629 } 3630 3631 if (Result.getNode()) { 3632 Ops.push_back(Result); 3633 return; 3634 } 3635 3636 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3637 } 3638 3639 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3640 const AddrMode &AM, Type *Ty, 3641 unsigned AS) const { 3642 // No global is ever allowed as a base. 3643 if (AM.BaseGV) 3644 return false; 3645 3646 switch (AM.Scale) { 3647 case 0: // "r+i" or just "i", depending on HasBaseReg. 3648 break; 3649 case 1: 3650 if (!AM.HasBaseReg) // allow "r+i". 3651 break; 3652 return false; // disallow "r+r" or "r+r+i". 3653 default: 3654 return false; 3655 } 3656 3657 return true; 3658 } 3659 3660 bool 3661 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3662 // The Mips target isn't yet aware of offsets. 3663 return false; 3664 } 3665 3666 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3667 unsigned SrcAlign, 3668 bool IsMemset, bool ZeroMemset, 3669 bool MemcpyStrSrc, 3670 MachineFunction &MF) const { 3671 if (Subtarget.hasMips64()) 3672 return MVT::i64; 3673 3674 return MVT::i32; 3675 } 3676 3677 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3678 if (VT != MVT::f32 && VT != MVT::f64) 3679 return false; 3680 if (Imm.isNegZero()) 3681 return false; 3682 return Imm.isZero(); 3683 } 3684 3685 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3686 if (ABI.IsN64()) 3687 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3688 3689 return TargetLowering::getJumpTableEncoding(); 3690 } 3691 3692 bool MipsTargetLowering::useSoftFloat() const { 3693 return Subtarget.useSoftFloat(); 3694 } 3695 3696 void MipsTargetLowering::copyByValRegs( 3697 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 3698 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3699 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3700 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 3701 MipsCCState &State) const { 3702 MachineFunction &MF = DAG.getMachineFunction(); 3703 MachineFrameInfo &MFI = MF.getFrameInfo(); 3704 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 3705 unsigned NumRegs = LastReg - FirstReg; 3706 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 3707 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3708 int FrameObjOffset; 3709 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 3710 3711 if (RegAreaSize) 3712 FrameObjOffset = 3713 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3714 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 3715 else 3716 FrameObjOffset = VA.getLocMemOffset(); 3717 3718 // Create frame object. 3719 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 3720 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3721 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3722 InVals.push_back(FIN); 3723 3724 if (!NumRegs) 3725 return; 3726 3727 // Copy arg registers. 3728 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 3729 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3730 3731 for (unsigned I = 0; I < NumRegs; ++I) { 3732 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 3733 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3734 unsigned Offset = I * GPRSizeInBytes; 3735 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3736 DAG.getConstant(Offset, DL, PtrTy)); 3737 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3738 StorePtr, MachinePointerInfo(FuncArg, Offset)); 3739 OutChains.push_back(Store); 3740 } 3741 } 3742 3743 // Copy byVal arg to registers and stack. 3744 void MipsTargetLowering::passByValArg( 3745 SDValue Chain, const SDLoc &DL, 3746 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3747 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3748 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 3749 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 3750 const CCValAssign &VA) const { 3751 unsigned ByValSizeInBytes = Flags.getByValSize(); 3752 unsigned OffsetInBytes = 0; // From beginning of struct 3753 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3754 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 3755 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 3756 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3757 unsigned NumRegs = LastReg - FirstReg; 3758 3759 if (NumRegs) { 3760 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 3761 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 3762 unsigned I = 0; 3763 3764 // Copy words to registers. 3765 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 3766 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3767 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3768 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3769 MachinePointerInfo(), Alignment); 3770 MemOpChains.push_back(LoadVal.getValue(1)); 3771 unsigned ArgReg = ArgRegs[FirstReg + I]; 3772 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3773 } 3774 3775 // Return if the struct has been fully copied. 3776 if (ByValSizeInBytes == OffsetInBytes) 3777 return; 3778 3779 // Copy the remainder of the byval argument with sub-word loads and shifts. 3780 if (LeftoverBytes) { 3781 SDValue Val; 3782 3783 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 3784 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 3785 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 3786 3787 if (RemainingSizeInBytes < LoadSizeInBytes) 3788 continue; 3789 3790 // Load subword. 3791 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3792 DAG.getConstant(OffsetInBytes, DL, 3793 PtrTy)); 3794 SDValue LoadVal = DAG.getExtLoad( 3795 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 3796 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 3797 MemOpChains.push_back(LoadVal.getValue(1)); 3798 3799 // Shift the loaded value. 3800 unsigned Shamt; 3801 3802 if (isLittle) 3803 Shamt = TotalBytesLoaded * 8; 3804 else 3805 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 3806 3807 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3808 DAG.getConstant(Shamt, DL, MVT::i32)); 3809 3810 if (Val.getNode()) 3811 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3812 else 3813 Val = Shift; 3814 3815 OffsetInBytes += LoadSizeInBytes; 3816 TotalBytesLoaded += LoadSizeInBytes; 3817 Alignment = std::min(Alignment, LoadSizeInBytes); 3818 } 3819 3820 unsigned ArgReg = ArgRegs[FirstReg + I]; 3821 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3822 return; 3823 } 3824 } 3825 3826 // Copy remainder of byval arg to it with memcpy. 3827 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 3828 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3829 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3830 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3831 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 3832 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3833 DAG.getConstant(MemCpySize, DL, PtrTy), 3834 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3835 /*isTailCall=*/false, 3836 MachinePointerInfo(), MachinePointerInfo()); 3837 MemOpChains.push_back(Chain); 3838 } 3839 3840 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3841 SDValue Chain, const SDLoc &DL, 3842 SelectionDAG &DAG, 3843 CCState &State) const { 3844 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 3845 unsigned Idx = State.getFirstUnallocated(ArgRegs); 3846 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3847 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3848 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3849 MachineFunction &MF = DAG.getMachineFunction(); 3850 MachineFrameInfo &MFI = MF.getFrameInfo(); 3851 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3852 3853 // Offset of the first variable argument from stack pointer. 3854 int VaArgOffset; 3855 3856 if (ArgRegs.size() == Idx) 3857 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 3858 else { 3859 VaArgOffset = 3860 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3861 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 3862 } 3863 3864 // Record the frame index of the first variable argument 3865 // which is a value necessary to VASTART. 3866 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3867 MipsFI->setVarArgsFrameIndex(FI); 3868 3869 // Copy the integer registers that have not been used for argument passing 3870 // to the argument register save area. For O32, the save area is allocated 3871 // in the caller's stack frame, while for N32/64, it is allocated in the 3872 // callee's stack frame. 3873 for (unsigned I = Idx; I < ArgRegs.size(); 3874 ++I, VaArgOffset += RegSizeInBytes) { 3875 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3876 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3877 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3878 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3879 SDValue Store = 3880 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 3881 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 3882 (Value *)nullptr); 3883 OutChains.push_back(Store); 3884 } 3885 } 3886 3887 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 3888 unsigned Align) const { 3889 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3890 3891 assert(Size && "Byval argument's size shouldn't be 0."); 3892 3893 Align = std::min(Align, TFL->getStackAlignment()); 3894 3895 unsigned FirstReg = 0; 3896 unsigned NumRegs = 0; 3897 3898 if (State->getCallingConv() != CallingConv::Fast) { 3899 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3900 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 3901 // FIXME: The O32 case actually describes no shadow registers. 3902 const MCPhysReg *ShadowRegs = 3903 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 3904 3905 // We used to check the size as well but we can't do that anymore since 3906 // CCState::HandleByVal() rounds up the size after calling this function. 3907 assert(!(Align % RegSizeInBytes) && 3908 "Byval argument's alignment should be a multiple of" 3909 "RegSizeInBytes."); 3910 3911 FirstReg = State->getFirstUnallocated(IntArgRegs); 3912 3913 // If Align > RegSizeInBytes, the first arg register must be even. 3914 // FIXME: This condition happens to do the right thing but it's not the 3915 // right way to test it. We want to check that the stack frame offset 3916 // of the register is aligned. 3917 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 3918 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 3919 ++FirstReg; 3920 } 3921 3922 // Mark the registers allocated. 3923 Size = alignTo(Size, RegSizeInBytes); 3924 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 3925 Size -= RegSizeInBytes, ++I, ++NumRegs) 3926 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3927 } 3928 3929 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 3930 } 3931 3932 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 3933 MachineBasicBlock *BB, 3934 bool isFPCmp, 3935 unsigned Opc) const { 3936 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 3937 "Subtarget already supports SELECT nodes with the use of" 3938 "conditional-move instructions."); 3939 3940 const TargetInstrInfo *TII = 3941 Subtarget.getInstrInfo(); 3942 DebugLoc DL = MI.getDebugLoc(); 3943 3944 // To "insert" a SELECT instruction, we actually have to insert the 3945 // diamond control-flow pattern. The incoming instruction knows the 3946 // destination vreg to set, the condition code register to branch on, the 3947 // true/false values to select between, and a branch opcode to use. 3948 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3949 MachineFunction::iterator It = ++BB->getIterator(); 3950 3951 // thisMBB: 3952 // ... 3953 // TrueVal = ... 3954 // setcc r1, r2, r3 3955 // bNE r1, r0, copy1MBB 3956 // fallthrough --> copy0MBB 3957 MachineBasicBlock *thisMBB = BB; 3958 MachineFunction *F = BB->getParent(); 3959 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 3960 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 3961 F->insert(It, copy0MBB); 3962 F->insert(It, sinkMBB); 3963 3964 // Transfer the remainder of BB and its successor edges to sinkMBB. 3965 sinkMBB->splice(sinkMBB->begin(), BB, 3966 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 3967 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 3968 3969 // Next, add the true and fallthrough blocks as its successors. 3970 BB->addSuccessor(copy0MBB); 3971 BB->addSuccessor(sinkMBB); 3972 3973 if (isFPCmp) { 3974 // bc1[tf] cc, sinkMBB 3975 BuildMI(BB, DL, TII->get(Opc)) 3976 .addReg(MI.getOperand(1).getReg()) 3977 .addMBB(sinkMBB); 3978 } else { 3979 // bne rs, $0, sinkMBB 3980 BuildMI(BB, DL, TII->get(Opc)) 3981 .addReg(MI.getOperand(1).getReg()) 3982 .addReg(Mips::ZERO) 3983 .addMBB(sinkMBB); 3984 } 3985 3986 // copy0MBB: 3987 // %FalseValue = ... 3988 // # fallthrough to sinkMBB 3989 BB = copy0MBB; 3990 3991 // Update machine-CFG edges 3992 BB->addSuccessor(sinkMBB); 3993 3994 // sinkMBB: 3995 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 3996 // ... 3997 BB = sinkMBB; 3998 3999 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4000 .addReg(MI.getOperand(2).getReg()) 4001 .addMBB(thisMBB) 4002 .addReg(MI.getOperand(3).getReg()) 4003 .addMBB(copy0MBB); 4004 4005 MI.eraseFromParent(); // The pseudo instruction is gone now. 4006 4007 return BB; 4008 } 4009 4010 // FIXME? Maybe this could be a TableGen attribute on some registers and 4011 // this table could be generated automatically from RegInfo. 4012 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4013 SelectionDAG &DAG) const { 4014 // Named registers is expected to be fairly rare. For now, just support $28 4015 // since the linux kernel uses it. 4016 if (Subtarget.isGP64bit()) { 4017 unsigned Reg = StringSwitch<unsigned>(RegName) 4018 .Case("$28", Mips::GP_64) 4019 .Default(0); 4020 if (Reg) 4021 return Reg; 4022 } else { 4023 unsigned Reg = StringSwitch<unsigned>(RegName) 4024 .Case("$28", Mips::GP) 4025 .Default(0); 4026 if (Reg) 4027 return Reg; 4028 } 4029 report_fatal_error("Invalid register name global variable"); 4030 } 4031