1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines an instruction selector for the MIPS target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mips-isel"
15 #include "MipsISelDAGToDAG.h"
16 #include "Mips16ISelDAGToDAG.h"
17 #include "MipsSEISelDAGToDAG.h"
18 #include "Mips.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsRegisterInfo.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Instructions.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/CFG.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetMachine.h"
37 using namespace llvm;
38 
39 //===----------------------------------------------------------------------===//
40 // Instruction Selector Implementation
41 //===----------------------------------------------------------------------===//
42 
43 //===----------------------------------------------------------------------===//
44 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
45 // instructions for SelectionDAG operations.
46 //===----------------------------------------------------------------------===//
47 
48 bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
49   bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
50 
51   processFunctionAfterISel(MF);
52 
53   return Ret;
54 }
55 
56 /// getGlobalBaseReg - Output the instructions required to put the
57 /// GOT address into a register.
58 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
59   unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
60   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
61 }
62 
63 /// ComplexPattern used on MipsInstrInfo
64 /// Used on Mips Load/Store instructions
65 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
66                                         SDValue &Offset) const {
67   llvm_unreachable("Unimplemented function.");
68   return false;
69 }
70 
71 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
72                                          SDValue &Offset) const {
73   llvm_unreachable("Unimplemented function.");
74   return false;
75 }
76 
77 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
78                                      SDValue &Offset) const {
79   llvm_unreachable("Unimplemented function.");
80   return false;
81 }
82 
83 bool MipsDAGToDAGISel::selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
84                                     SDValue &Offset, SDValue &Alias) {
85   llvm_unreachable("Unimplemented function.");
86   return false;
87 }
88 
89 /// Select instructions not customized! Used for
90 /// expanded, promoted and normal instructions
91 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
92   unsigned Opcode = Node->getOpcode();
93 
94   // Dump information about the Node being selected
95   DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
96 
97   // If we have a custom node, we already have selected!
98   if (Node->isMachineOpcode()) {
99     DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
100     return NULL;
101   }
102 
103   // See if subclasses can handle this node.
104   std::pair<bool, SDNode*> Ret = selectNode(Node);
105 
106   if (Ret.first)
107     return Ret.second;
108 
109   switch(Opcode) {
110   default: break;
111 
112   // Get target GOT address.
113   case ISD::GLOBAL_OFFSET_TABLE:
114     return getGlobalBaseReg();
115 
116 #ifndef NDEBUG
117   case ISD::LOAD:
118   case ISD::STORE:
119     assert(cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
120            cast<MemSDNode>(Node)->getAlignment() &&
121            "Unexpected unaligned loads/stores.");
122     break;
123 #endif
124   }
125 
126   // Select the default instruction
127   SDNode *ResNode = SelectCode(Node);
128 
129   DEBUG(errs() << "=> ");
130   if (ResNode == NULL || ResNode == Node)
131     DEBUG(Node->dump(CurDAG));
132   else
133     DEBUG(ResNode->dump(CurDAG));
134   DEBUG(errs() << "\n");
135   return ResNode;
136 }
137 
138 bool MipsDAGToDAGISel::
139 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
140                              std::vector<SDValue> &OutOps) {
141   assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
142   OutOps.push_back(Op);
143   return false;
144 }
145 
146 /// createMipsISelDag - This pass converts a legalized DAG into a
147 /// MIPS-specific DAG, ready for instruction scheduling.
148 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
149   if (TM.getSubtargetImpl()->inMips16Mode())
150     return llvm::createMips16ISelDag(TM);
151 
152   return llvm::createMipsSEISelDag(TM);
153 }
154