1 //===-- MipsFrameLowering.cpp - Mips Frame Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsFrameLowering.h" 15 #include "MipsAnalyzeImmediate.h" 16 #include "MipsInstrInfo.h" 17 #include "MipsMachineFunction.h" 18 #include "MCTargetDesc/MipsBaseInfo.h" 19 #include "llvm/Function.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/Target/TargetData.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Support/CommandLine.h" 28 29 using namespace llvm; 30 31 32 //===----------------------------------------------------------------------===// 33 // 34 // Stack Frame Processing methods 35 // +----------------------------+ 36 // 37 // The stack is allocated decrementing the stack pointer on 38 // the first instruction of a function prologue. Once decremented, 39 // all stack references are done thought a positive offset 40 // from the stack/frame pointer, so the stack is considering 41 // to grow up! Otherwise terrible hacks would have to be made 42 // to get this stack ABI compliant :) 43 // 44 // The stack frame required by the ABI (after call): 45 // Offset 46 // 47 // 0 ---------- 48 // 4 Args to pass 49 // . saved $GP (used in PIC) 50 // . Alloca allocations 51 // . Local Area 52 // . CPU "Callee Saved" Registers 53 // . saved FP 54 // . saved RA 55 // . FPU "Callee Saved" Registers 56 // StackSize ----------- 57 // 58 // Offset - offset from sp after stack allocation on function prologue 59 // 60 // The sp is the stack pointer subtracted/added from the stack size 61 // at the Prologue/Epilogue 62 // 63 // References to the previous stack (to obtain arguments) are done 64 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) 65 // 66 // Examples: 67 // - reference to the actual stack frame 68 // for any local area var there is smt like : FI >= 0, StackOffset: 4 69 // sw REGX, 4(SP) 70 // 71 // - reference to previous stack frame 72 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. 73 // The emitted instruction will be something like: 74 // lw REGX, 16+StackSize(SP) 75 // 76 // Since the total stack size is unknown on LowerFormalArguments, all 77 // stack references (ObjectOffset) created to reference the function 78 // arguments, are negative numbers. This way, on eliminateFrameIndex it's 79 // possible to detect those references and the offsets are adjusted to 80 // their real location. 81 // 82 //===----------------------------------------------------------------------===// 83 84 // hasFP - Return true if the specified function should have a dedicated frame 85 // pointer register. This is true if the function has variable sized allocas or 86 // if frame pointer elimination is disabled. 87 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { 88 const MachineFrameInfo *MFI = MF.getFrameInfo(); 89 return MF.getTarget().Options.DisableFramePointerElim(MF) || 90 MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 91 } 92 93 bool MipsFrameLowering::targetHandlesStackFrameRounding() const { 94 return true; 95 } 96 97 // Build an instruction sequence to load an immediate that is too large to fit 98 // in 16-bit and add the result to Reg. 99 static void expandLargeImm(unsigned Reg, int64_t Imm, bool IsN64, 100 const MipsInstrInfo &TII, MachineBasicBlock& MBB, 101 MachineBasicBlock::iterator II, DebugLoc DL) { 102 unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi; 103 unsigned ADDu = IsN64 ? Mips::DADDu : Mips::ADDu; 104 unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO; 105 unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT; 106 MipsAnalyzeImmediate AnalyzeImm; 107 const MipsAnalyzeImmediate::InstSeq &Seq = 108 AnalyzeImm.Analyze(Imm, IsN64 ? 64 : 32, false /* LastInstrIsADDiu */); 109 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 110 111 // The first instruction can be a LUi, which is different from other 112 // instructions (ADDiu, ORI and SLL) in that it does not have a register 113 // operand. 114 if (Inst->Opc == LUi) 115 BuildMI(MBB, II, DL, TII.get(LUi), ATReg) 116 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 117 else 118 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg) 119 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 120 121 // Build the remaining instructions in Seq. 122 for (++Inst; Inst != Seq.end(); ++Inst) 123 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg) 124 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 125 126 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(Reg).addReg(ATReg); 127 } 128 129 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { 130 MachineBasicBlock &MBB = MF.front(); 131 MachineFrameInfo *MFI = MF.getFrameInfo(); 132 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 133 const MipsRegisterInfo *RegInfo = 134 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); 135 const MipsInstrInfo &TII = 136 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 137 MachineBasicBlock::iterator MBBI = MBB.begin(); 138 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 139 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 140 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 141 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 142 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 143 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 144 145 // First, compute final stack size. 146 unsigned StackAlign = getStackAlignment(); 147 uint64_t StackSize = 148 RoundUpToAlignment(MipsFI->getMaxCallFrameSize(), StackAlign) + 149 RoundUpToAlignment(MFI->getStackSize(), StackAlign); 150 151 // Update stack size 152 MFI->setStackSize(StackSize); 153 154 // No need to allocate space on the stack. 155 if (StackSize == 0 && !MFI->adjustsStack()) return; 156 157 MachineModuleInfo &MMI = MF.getMMI(); 158 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 159 MachineLocation DstML, SrcML; 160 161 // Adjust stack. 162 if (isInt<16>(-StackSize)) // addi sp, sp, (-stacksize) 163 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize); 164 else { // Expand immediate that doesn't fit in 16-bit. 165 MipsFI->setEmitNOAT(); 166 expandLargeImm(SP, -StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl); 167 } 168 169 // emit ".cfi_def_cfa_offset StackSize" 170 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); 171 BuildMI(MBB, MBBI, dl, 172 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); 173 DstML = MachineLocation(MachineLocation::VirtualFP); 174 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); 175 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); 176 177 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 178 179 if (CSI.size()) { 180 // Find the instruction past the last instruction that saves a callee-saved 181 // register to the stack. 182 for (unsigned i = 0; i < CSI.size(); ++i) 183 ++MBBI; 184 185 // Iterate over list of callee-saved registers and emit .cfi_offset 186 // directives. 187 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol(); 188 BuildMI(MBB, MBBI, dl, 189 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); 190 191 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 192 E = CSI.end(); I != E; ++I) { 193 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 194 unsigned Reg = I->getReg(); 195 196 // If Reg is a double precision register, emit two cfa_offsets, 197 // one for each of the paired single precision registers. 198 if (Mips::AFGR64RegClass.contains(Reg)) { 199 const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg); 200 MachineLocation DstML0(MachineLocation::VirtualFP, Offset); 201 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); 202 MachineLocation SrcML0(*SubRegs); 203 MachineLocation SrcML1(*(SubRegs + 1)); 204 205 if (!STI.isLittle()) 206 std::swap(SrcML0, SrcML1); 207 208 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0)); 209 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1)); 210 } else { 211 // Reg is either in CPURegs or FGR32. 212 DstML = MachineLocation(MachineLocation::VirtualFP, Offset); 213 SrcML = MachineLocation(Reg); 214 Moves.push_back(MachineMove(CSLabel, DstML, SrcML)); 215 } 216 } 217 } 218 219 // if framepointer enabled, set it to point to the stack pointer. 220 if (hasFP(MF)) { 221 // Insert instruction "move $fp, $sp" at this location. 222 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); 223 224 // emit ".cfi_def_cfa_register $fp" 225 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); 226 BuildMI(MBB, MBBI, dl, 227 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); 228 DstML = MachineLocation(FP); 229 SrcML = MachineLocation(MachineLocation::VirtualFP); 230 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML)); 231 } 232 } 233 234 void MipsFrameLowering::emitEpilogue(MachineFunction &MF, 235 MachineBasicBlock &MBB) const { 236 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 237 MachineFrameInfo *MFI = MF.getFrameInfo(); 238 const MipsInstrInfo &TII = 239 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo()); 240 DebugLoc dl = MBBI->getDebugLoc(); 241 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 242 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 243 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 244 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 245 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 246 247 // if framepointer enabled, restore the stack pointer. 248 if (hasFP(MF)) { 249 // Find the first instruction that restores a callee-saved register. 250 MachineBasicBlock::iterator I = MBBI; 251 252 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) 253 --I; 254 255 // Insert instruction "move $sp, $fp" at this location. 256 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); 257 } 258 259 // Get the number of bytes from FrameInfo 260 uint64_t StackSize = MFI->getStackSize(); 261 262 if (!StackSize) 263 return; 264 265 // Adjust stack. 266 if (isInt<16>(StackSize)) // addi sp, sp, (-stacksize) 267 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize); 268 else // Expand immediate that doesn't fit in 16-bit. 269 expandLargeImm(SP, StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl); 270 } 271 272 void MipsFrameLowering:: 273 processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 274 RegScavenger *RS) const { 275 MachineRegisterInfo& MRI = MF.getRegInfo(); 276 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 277 278 // FIXME: remove this code if register allocator can correctly mark 279 // $fp and $ra used or unused. 280 281 // Mark $fp and $ra as used or unused. 282 if (hasFP(MF)) 283 MRI.setPhysRegUsed(FP); 284 285 // The register allocator might determine $ra is used after seeing 286 // instruction "jr $ra", but we do not want PrologEpilogInserter to insert 287 // instructions to save/restore $ra unless there is a function call. 288 // To correct this, $ra is explicitly marked unused if there is no 289 // function call. 290 if (MF.getFrameInfo()->hasCalls()) 291 MRI.setPhysRegUsed(Mips::RA); 292 else { 293 MRI.setPhysRegUnused(Mips::RA); 294 MRI.setPhysRegUnused(Mips::RA_64); 295 } 296 } 297