1 //=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsFrameLowering.h"
15 #include "MipsInstrInfo.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Support/CommandLine.h"
26 
27 using namespace llvm;
28 
29 
30 //===----------------------------------------------------------------------===//
31 //
32 // Stack Frame Processing methods
33 // +----------------------------+
34 //
35 // The stack is allocated decrementing the stack pointer on
36 // the first instruction of a function prologue. Once decremented,
37 // all stack references are done thought a positive offset
38 // from the stack/frame pointer, so the stack is considering
39 // to grow up! Otherwise terrible hacks would have to be made
40 // to get this stack ABI compliant :)
41 //
42 //  The stack frame required by the ABI (after call):
43 //  Offset
44 //
45 //  0                 ----------
46 //  4                 Args to pass
47 //  .                 saved $GP  (used in PIC)
48 //  .                 Alloca allocations
49 //  .                 Local Area
50 //  .                 CPU "Callee Saved" Registers
51 //  .                 saved FP
52 //  .                 saved RA
53 //  .                 FPU "Callee Saved" Registers
54 //  StackSize         -----------
55 //
56 // Offset - offset from sp after stack allocation on function prologue
57 //
58 // The sp is the stack pointer subtracted/added from the stack size
59 // at the Prologue/Epilogue
60 //
61 // References to the previous stack (to obtain arguments) are done
62 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
63 //
64 // Examples:
65 // - reference to the actual stack frame
66 //   for any local area var there is smt like : FI >= 0, StackOffset: 4
67 //     sw REGX, 4(SP)
68 //
69 // - reference to previous stack frame
70 //   suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
71 //   The emitted instruction will be something like:
72 //     lw REGX, 16+StackSize(SP)
73 //
74 // Since the total stack size is unknown on LowerFormalArguments, all
75 // stack references (ObjectOffset) created to reference the function
76 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
77 // possible to detect those references and the offsets are adjusted to
78 // their real location.
79 //
80 //===----------------------------------------------------------------------===//
81 
82 // hasFP - Return true if the specified function should have a dedicated frame
83 // pointer register.  This is true if the function has variable sized allocas or
84 // if frame pointer elimination is disabled.
85 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
86   const MachineFrameInfo *MFI = MF.getFrameInfo();
87   return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
88 }
89 
90 void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const {
91   MachineFrameInfo *MFI = MF.getFrameInfo();
92   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
93   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
94   unsigned StackAlign = getStackAlignment();
95   unsigned RegSize = STI.isGP32bit() ? 4 : 8;
96   bool HasGP = MipsFI->needGPSaveRestore();
97 
98   // Min and Max CSI FrameIndex.
99   int MinCSFI = -1, MaxCSFI = -1;
100 
101   // See the description at MipsMachineFunction.h
102   int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
103 
104   // Replace the dummy '0' SPOffset by the negative offsets, as explained on
105   // LowerFormalArguments. Leaving '0' for while is necessary to avoid the
106   // approach done by calculateFrameObjectOffsets to the stack frame.
107   MipsFI->adjustLoadArgsFI(MFI);
108   MipsFI->adjustStoreVarArgsFI(MFI);
109 
110   // It happens that the default stack frame allocation order does not directly
111   // map to the convention used for mips. So we must fix it. We move the callee
112   // save register slots after the local variables area, as described in the
113   // stack frame above.
114   unsigned CalleeSavedAreaSize = 0;
115   if (!CSI.empty()) {
116     MinCSFI = CSI[0].getFrameIdx();
117     MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
118   }
119   for (unsigned i = 0, e = CSI.size(); i != e; ++i)
120     CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
121 
122   unsigned StackOffset = HasGP ? (MipsFI->getGPStackOffset()+RegSize)
123                 : (STI.isABI_O32() ? 16 : 0);
124 
125   // Adjust local variables. They should come on the stack right
126   // after the arguments.
127   int LastOffsetFI = -1;
128   for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
129     if (i >= MinCSFI && i <= MaxCSFI)
130       continue;
131     if (MFI->isDeadObjectIndex(i))
132       continue;
133     unsigned Offset =
134       StackOffset + MFI->getObjectOffset(i) - CalleeSavedAreaSize;
135     if (LastOffsetFI == -1)
136       LastOffsetFI = i;
137     if (Offset > MFI->getObjectOffset(LastOffsetFI))
138       LastOffsetFI = i;
139     MFI->setObjectOffset(i, Offset);
140   }
141 
142   // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
143   // be saved in this CPU Area. This whole area must be aligned to the
144   // default Stack Alignment requirements.
145   if (LastOffsetFI >= 0)
146     StackOffset = MFI->getObjectOffset(LastOffsetFI)+
147                   MFI->getObjectSize(LastOffsetFI);
148   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
149 
150   for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
151     unsigned Reg = CSI[i].getReg();
152     if (!Mips::CPURegsRegisterClass->contains(Reg))
153       break;
154     MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
155     TopCPUSavedRegOff = StackOffset;
156     StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
157   }
158 
159   // Stack locations for FP and RA. If only one of them is used,
160   // the space must be allocated for both, otherwise no space at all.
161   if (hasFP(MF) || MFI->adjustsStack()) {
162     // FP stack location
163     MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
164                          StackOffset);
165     MipsFI->setFPStackOffset(StackOffset);
166     TopCPUSavedRegOff = StackOffset;
167     StackOffset += RegSize;
168 
169     // SP stack location
170     MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
171                          StackOffset);
172     MipsFI->setRAStackOffset(StackOffset);
173     StackOffset += RegSize;
174 
175     if (MFI->adjustsStack())
176       TopCPUSavedRegOff += RegSize;
177   }
178 
179   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
180 
181   // Adjust FPU Callee Saved Registers Area. This Area must be
182   // aligned to the default Stack Alignment requirements.
183   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
184     unsigned Reg = CSI[i].getReg();
185     if (Mips::CPURegsRegisterClass->contains(Reg))
186       continue;
187     MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
188     TopFPUSavedRegOff = StackOffset;
189     StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
190   }
191   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
192 
193   // Update frame info
194   MFI->setStackSize(StackOffset);
195 
196   // Recalculate the final tops offset. The final values must be '0'
197   // if there isn't a callee saved register for CPU or FPU, otherwise
198   // a negative offset is needed.
199   if (TopCPUSavedRegOff >= 0)
200     MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
201 
202   if (TopFPUSavedRegOff >= 0)
203     MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
204 }
205 
206 
207 // expand pair of register and immediate if the immediate doesn't fit in the
208 // 16-bit offset field.
209 // e.g.
210 //  if OrigImm = 0x10000, OrigReg = $sp:
211 //    generate the following sequence of instrs:
212 //      lui  $at, hi(0x10000)
213 //      addu $at, $sp, $at
214 //
215 //    (NewReg, NewImm) = ($at, lo(Ox10000))
216 //    return true
217 static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm,
218                                   unsigned& NewReg, int& NewImm,
219                                   MachineBasicBlock& MBB,
220                                   MachineBasicBlock::iterator I) {
221   // OrigImm fits in the 16-bit field
222   if (OrigImm < 0x8000 && OrigImm >= -0x8000) {
223     NewReg = OrigReg;
224     NewImm = OrigImm;
225     return false;
226   }
227 
228   MachineFunction* MF = MBB.getParent();
229   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
230   DebugLoc DL = I->getDebugLoc();
231   int ImmLo = OrigImm & 0xffff;
232   int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
233               ((OrigImm & 0x8000) != 0);
234 
235   // FIXME: change this when mips goes MC".
236   BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
237   BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
238   BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
239                                                      .addReg(Mips::AT);
240   NewReg = Mips::AT;
241   NewImm = ImmLo;
242 
243   return true;
244 }
245 
246 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
247   MachineBasicBlock &MBB   = MF.front();
248   MachineFrameInfo *MFI    = MF.getFrameInfo();
249   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
250   const MipsRegisterInfo *RegInfo =
251     static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
252   const MipsInstrInfo &TII =
253     *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
254   MachineBasicBlock::iterator MBBI = MBB.begin();
255   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
256   bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
257   unsigned NewReg = 0;
258   int NewImm = 0;
259   bool ATUsed;
260 
261   // Get the right frame order for Mips.
262   adjustMipsStackFrame(MF);
263 
264   // Get the number of bytes to allocate from the FrameInfo.
265   unsigned StackSize = MFI->getStackSize();
266 
267   // No need to allocate space on the stack.
268   if (StackSize == 0 && !MFI->adjustsStack()) return;
269 
270   int FPOffset = MipsFI->getFPStackOffset();
271   int RAOffset = MipsFI->getRAStackOffset();
272 
273   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
274 
275   // TODO: check need from GP here.
276   if (isPIC && STI.isABI_O32())
277     BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
278       .addReg(RegInfo->getPICCallReg());
279   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
280 
281   // Adjust stack : addi sp, sp, (-imm)
282   ATUsed = expandRegLargeImmPair(Mips::SP, -StackSize, NewReg, NewImm, MBB,
283                                  MBBI);
284   BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
285     .addReg(NewReg).addImm(NewImm);
286 
287   // FIXME: change this when mips goes MC".
288   if (ATUsed)
289     BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
290 
291   // Save the return address only if the function isn't a leaf one.
292   // sw  $ra, stack_loc($sp)
293   if (MFI->adjustsStack()) {
294     ATUsed = expandRegLargeImmPair(Mips::SP, RAOffset, NewReg, NewImm, MBB,
295                                    MBBI);
296     BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
297       .addReg(Mips::RA).addImm(NewImm).addReg(NewReg);
298 
299     // FIXME: change this when mips goes MC".
300     if (ATUsed)
301       BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
302   }
303 
304   // if framepointer enabled, save it and set it
305   // to point to the stack pointer
306   if (hasFP(MF)) {
307     // sw  $fp,stack_loc($sp)
308     ATUsed = expandRegLargeImmPair(Mips::SP, FPOffset, NewReg, NewImm, MBB,
309                                    MBBI);
310     BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
311       .addReg(Mips::FP).addImm(NewImm).addReg(NewReg);
312 
313     // FIXME: change this when mips goes MC".
314     if (ATUsed)
315       BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
316 
317     // move $fp, $sp
318     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
319       .addReg(Mips::SP).addReg(Mips::ZERO);
320   }
321 
322   // Restore GP from the saved stack location
323   if (MipsFI->needGPSaveRestore())
324     BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
325       .addImm(MipsFI->getGPStackOffset());
326 }
327 
328 void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
329                                  MachineBasicBlock &MBB) const {
330   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
331   MachineFrameInfo *MFI            = MF.getFrameInfo();
332   MipsFunctionInfo *MipsFI         = MF.getInfo<MipsFunctionInfo>();
333   const MipsInstrInfo &TII =
334     *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
335   DebugLoc dl = MBBI->getDebugLoc();
336 
337   // Get the number of bytes from FrameInfo
338   int NumBytes = (int) MFI->getStackSize();
339 
340   // Get the FI's where RA and FP are saved.
341   int FPOffset = MipsFI->getFPStackOffset();
342   int RAOffset = MipsFI->getRAStackOffset();
343 
344   unsigned NewReg = 0;
345   int NewImm = 0;
346   bool ATUsed = false;
347 
348   // if framepointer enabled, restore it and restore the
349   // stack pointer
350   if (hasFP(MF)) {
351     // move $sp, $fp
352     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
353       .addReg(Mips::FP).addReg(Mips::ZERO);
354 
355     // lw  $fp,stack_loc($sp)
356     ATUsed = expandRegLargeImmPair(Mips::SP, FPOffset, NewReg, NewImm, MBB,
357                                    MBBI);
358     BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP)
359       .addImm(NewImm).addReg(NewReg);
360 
361     // FIXME: change this when mips goes MC".
362     if (ATUsed)
363       BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
364   }
365 
366   // Restore the return address only if the function isn't a leaf one.
367   // lw  $ra, stack_loc($sp)
368   if (MFI->adjustsStack()) {
369     ATUsed = expandRegLargeImmPair(Mips::SP, RAOffset, NewReg, NewImm, MBB,
370                                    MBBI);
371     BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA)
372       .addImm(NewImm).addReg(NewReg);
373 
374     // FIXME: change this when mips goes MC".
375     if (ATUsed)
376       BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
377   }
378 
379   // adjust stack  : insert addi sp, sp, (imm)
380   if (NumBytes) {
381     ATUsed = expandRegLargeImmPair(Mips::SP, NumBytes, NewReg, NewImm, MBB,
382                                    MBBI);
383     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
384       .addReg(NewReg).addImm(NewImm);
385 
386     // FIXME: change this when mips goes MC".
387     if (ATUsed)
388       BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
389   }
390 }
391 
392 void MipsFrameLowering::
393 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
394   const MipsRegisterInfo *RegInfo =
395     static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
396   RegInfo->processFunctionBeforeFrameFinalized(MF);
397 }
398