1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file defines the MIPS-specific support for the FastISel class.
12 /// Some of the target-specific code is generated by tablegen in the file
13 /// MipsGenFastISel.inc, which is #included here.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsCCState.h"
20 #include "MipsISelLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsMachineFunction.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Analysis/TargetLibraryInfo.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineMemOperand.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/TargetInstrInfo.h"
40 #include "llvm/CodeGen/TargetLowering.h"
41 #include "llvm/CodeGen/ValueTypes.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/CallingConv.h"
44 #include "llvm/IR/Constant.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DataLayout.h"
47 #include "llvm/IR/Function.h"
48 #include "llvm/IR/GetElementPtrTypeIterator.h"
49 #include "llvm/IR/GlobalValue.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/InstrTypes.h"
52 #include "llvm/IR/Instruction.h"
53 #include "llvm/IR/Instructions.h"
54 #include "llvm/IR/IntrinsicInst.h"
55 #include "llvm/IR/Operator.h"
56 #include "llvm/IR/Type.h"
57 #include "llvm/IR/User.h"
58 #include "llvm/IR/Value.h"
59 #include "llvm/MC/MCInstrDesc.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/MC/MCSymbol.h"
62 #include "llvm/Support/Casting.h"
63 #include "llvm/Support/Compiler.h"
64 #include "llvm/Support/Debug.h"
65 #include "llvm/Support/ErrorHandling.h"
66 #include "llvm/Support/MachineValueType.h"
67 #include "llvm/Support/MathExtras.h"
68 #include "llvm/Support/raw_ostream.h"
69 #include <algorithm>
70 #include <array>
71 #include <cassert>
72 #include <cstdint>
73 
74 #define DEBUG_TYPE "mips-fastisel"
75 
76 using namespace llvm;
77 
78 namespace {
79 
80 class MipsFastISel final : public FastISel {
81 
82   // All possible address modes.
83   class Address {
84   public:
85     using BaseKind = enum { RegBase, FrameIndexBase };
86 
87   private:
88     BaseKind Kind = RegBase;
89     union {
90       unsigned Reg;
91       int FI;
92     } Base;
93 
94     int64_t Offset = 0;
95 
96     const GlobalValue *GV = nullptr;
97 
98   public:
99     // Innocuous defaults for our address.
100     Address() { Base.Reg = 0; }
101 
102     void setKind(BaseKind K) { Kind = K; }
103     BaseKind getKind() const { return Kind; }
104     bool isRegBase() const { return Kind == RegBase; }
105     bool isFIBase() const { return Kind == FrameIndexBase; }
106 
107     void setReg(unsigned Reg) {
108       assert(isRegBase() && "Invalid base register access!");
109       Base.Reg = Reg;
110     }
111 
112     unsigned getReg() const {
113       assert(isRegBase() && "Invalid base register access!");
114       return Base.Reg;
115     }
116 
117     void setFI(unsigned FI) {
118       assert(isFIBase() && "Invalid base frame index access!");
119       Base.FI = FI;
120     }
121 
122     unsigned getFI() const {
123       assert(isFIBase() && "Invalid base frame index access!");
124       return Base.FI;
125     }
126 
127     void setOffset(int64_t Offset_) { Offset = Offset_; }
128     int64_t getOffset() const { return Offset; }
129     void setGlobalValue(const GlobalValue *G) { GV = G; }
130     const GlobalValue *getGlobalValue() { return GV; }
131   };
132 
133   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
134   /// make the right decision when generating code for different targets.
135   const TargetMachine &TM;
136   const MipsSubtarget *Subtarget;
137   const TargetInstrInfo &TII;
138   const TargetLowering &TLI;
139   MipsFunctionInfo *MFI;
140 
141   // Convenience variables to avoid some queries.
142   LLVMContext *Context;
143 
144   bool fastLowerArguments() override;
145   bool fastLowerCall(CallLoweringInfo &CLI) override;
146   bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
147 
148   bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
149   // floating point but not reject doing fast-isel in other
150   // situations
151 
152 private:
153   // Selection routines.
154   bool selectLogicalOp(const Instruction *I);
155   bool selectLoad(const Instruction *I);
156   bool selectStore(const Instruction *I);
157   bool selectBranch(const Instruction *I);
158   bool selectSelect(const Instruction *I);
159   bool selectCmp(const Instruction *I);
160   bool selectFPExt(const Instruction *I);
161   bool selectFPTrunc(const Instruction *I);
162   bool selectFPToInt(const Instruction *I, bool IsSigned);
163   bool selectRet(const Instruction *I);
164   bool selectTrunc(const Instruction *I);
165   bool selectIntExt(const Instruction *I);
166   bool selectShift(const Instruction *I);
167   bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
168 
169   // Utility helper routines.
170   bool isTypeLegal(Type *Ty, MVT &VT);
171   bool isTypeSupported(Type *Ty, MVT &VT);
172   bool isLoadTypeLegal(Type *Ty, MVT &VT);
173   bool computeAddress(const Value *Obj, Address &Addr);
174   bool computeCallAddress(const Value *V, Address &Addr);
175   void simplifyAddress(Address &Addr);
176 
177   // Emit helper routines.
178   bool emitCmp(unsigned DestReg, const CmpInst *CI);
179   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
180                 unsigned Alignment = 0);
181   bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
182                  MachineMemOperand *MMO = nullptr);
183   bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
184                  unsigned Alignment = 0);
185   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
186   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 
188                   bool IsZExt);
189   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 
191   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
192   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
193                        unsigned DestReg);
194   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
195                        unsigned DestReg);
196 
197   unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
198 
199   unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
200                          const Value *RHS);
201 
202   unsigned materializeFP(const ConstantFP *CFP, MVT VT);
203   unsigned materializeGV(const GlobalValue *GV, MVT VT);
204   unsigned materializeInt(const Constant *C, MVT VT);
205   unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
206   unsigned materializeExternalCallSym(MCSymbol *Syn);
207 
208   MachineInstrBuilder emitInst(unsigned Opc) {
209     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
210   }
211 
212   MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
213     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
214                    DstReg);
215   }
216 
217   MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
218                                     unsigned MemReg, int64_t MemOffset) {
219     return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
220   }
221 
222   MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
223                                    unsigned MemReg, int64_t MemOffset) {
224     return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
225   }
226 
227   unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
228                            const TargetRegisterClass *RC,
229                            unsigned Op0, bool Op0IsKill,
230                            unsigned Op1, bool Op1IsKill);
231 
232   // for some reason, this default is not generated by tablegen
233   // so we explicitly generate it here.
234   unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
235                              unsigned Op0, bool Op0IsKill, uint64_t imm1,
236                              uint64_t imm2, unsigned Op3, bool Op3IsKill) {
237     return 0;
238   }
239 
240   // Call handling routines.
241 private:
242   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
243   bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
244                        unsigned &NumBytes);
245   bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
246 
247   const MipsABIInfo &getABI() const {
248     return static_cast<const MipsTargetMachine &>(TM).getABI();
249   }
250 
251 public:
252   // Backend specific FastISel code.
253   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
254                         const TargetLibraryInfo *libInfo)
255       : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
256         Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
257         TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
258     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
259     Context = &funcInfo.Fn->getContext();
260     UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
261   }
262 
263   unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
264   unsigned fastMaterializeConstant(const Constant *C) override;
265   bool fastSelectInstruction(const Instruction *I) override;
266 
267 #include "MipsGenFastISel.inc"
268 };
269 
270 } // end anonymous namespace
271 
272 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
273                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
274                     CCState &State) LLVM_ATTRIBUTE_UNUSED;
275 
276 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
277                             CCValAssign::LocInfo LocInfo,
278                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
279   llvm_unreachable("should not be called");
280 }
281 
282 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
283                             CCValAssign::LocInfo LocInfo,
284                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
285   llvm_unreachable("should not be called");
286 }
287 
288 #include "MipsGenCallingConv.inc"
289 
290 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
291   return CC_MipsO32;
292 }
293 
294 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
295                                      const Value *LHS, const Value *RHS) {
296   // Canonicalize immediates to the RHS first.
297   if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
298     std::swap(LHS, RHS);
299 
300   unsigned Opc;
301   switch (ISDOpc) {
302   case ISD::AND:
303     Opc = Mips::AND;
304     break;
305   case ISD::OR:
306     Opc = Mips::OR;
307     break;
308   case ISD::XOR:
309     Opc = Mips::XOR;
310     break;
311   default:
312     llvm_unreachable("unexpected opcode");
313   }
314 
315   unsigned LHSReg = getRegForValue(LHS);
316   if (!LHSReg)
317     return 0;
318 
319   unsigned RHSReg;
320   if (const auto *C = dyn_cast<ConstantInt>(RHS))
321     RHSReg = materializeInt(C, MVT::i32);
322   else
323     RHSReg = getRegForValue(RHS);
324   if (!RHSReg)
325     return 0;
326 
327   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
328   if (!ResultReg)
329     return 0;
330 
331   emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
332   return ResultReg;
333 }
334 
335 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
336   assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
337          "Alloca should always return a pointer.");
338 
339   DenseMap<const AllocaInst *, int>::iterator SI =
340       FuncInfo.StaticAllocaMap.find(AI);
341 
342   if (SI != FuncInfo.StaticAllocaMap.end()) {
343     unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
344     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
345             ResultReg)
346         .addFrameIndex(SI->second)
347         .addImm(0);
348     return ResultReg;
349   }
350 
351   return 0;
352 }
353 
354 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
355   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
356     return 0;
357   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
358   const ConstantInt *CI = cast<ConstantInt>(C);
359   return materialize32BitInt(CI->getZExtValue(), RC);
360 }
361 
362 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
363                                            const TargetRegisterClass *RC) {
364   unsigned ResultReg = createResultReg(RC);
365 
366   if (isInt<16>(Imm)) {
367     unsigned Opc = Mips::ADDiu;
368     emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
369     return ResultReg;
370   } else if (isUInt<16>(Imm)) {
371     emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
372     return ResultReg;
373   }
374   unsigned Lo = Imm & 0xFFFF;
375   unsigned Hi = (Imm >> 16) & 0xFFFF;
376   if (Lo) {
377     // Both Lo and Hi have nonzero bits.
378     unsigned TmpReg = createResultReg(RC);
379     emitInst(Mips::LUi, TmpReg).addImm(Hi);
380     emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
381   } else {
382     emitInst(Mips::LUi, ResultReg).addImm(Hi);
383   }
384   return ResultReg;
385 }
386 
387 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
388   if (UnsupportedFPMode)
389     return 0;
390   int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
391   if (VT == MVT::f32) {
392     const TargetRegisterClass *RC = &Mips::FGR32RegClass;
393     unsigned DestReg = createResultReg(RC);
394     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
395     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
396     return DestReg;
397   } else if (VT == MVT::f64) {
398     const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
399     unsigned DestReg = createResultReg(RC);
400     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
401     unsigned TempReg2 =
402         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
403     emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
404     return DestReg;
405   }
406   return 0;
407 }
408 
409 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
410   // For now 32-bit only.
411   if (VT != MVT::i32)
412     return 0;
413   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
414   unsigned DestReg = createResultReg(RC);
415   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
416   bool IsThreadLocal = GVar && GVar->isThreadLocal();
417   // TLS not supported at this time.
418   if (IsThreadLocal)
419     return 0;
420   emitInst(Mips::LW, DestReg)
421       .addReg(MFI->getGlobalBaseReg())
422       .addGlobalAddress(GV, 0, MipsII::MO_GOT);
423   if ((GV->hasInternalLinkage() ||
424        (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
425     unsigned TempReg = createResultReg(RC);
426     emitInst(Mips::ADDiu, TempReg)
427         .addReg(DestReg)
428         .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
429     DestReg = TempReg;
430   }
431   return DestReg;
432 }
433 
434 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
435   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
436   unsigned DestReg = createResultReg(RC);
437   emitInst(Mips::LW, DestReg)
438       .addReg(MFI->getGlobalBaseReg())
439       .addSym(Sym, MipsII::MO_GOT);
440   return DestReg;
441 }
442 
443 // Materialize a constant into a register, and return the register
444 // number (or zero if we failed to handle it).
445 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
446   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
447 
448   // Only handle simple types.
449   if (!CEVT.isSimple())
450     return 0;
451   MVT VT = CEVT.getSimpleVT();
452 
453   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
454     return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
455   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
456     return materializeGV(GV, VT);
457   else if (isa<ConstantInt>(C))
458     return materializeInt(C, VT);
459 
460   return 0;
461 }
462 
463 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
464   const User *U = nullptr;
465   unsigned Opcode = Instruction::UserOp1;
466   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
467     // Don't walk into other basic blocks unless the object is an alloca from
468     // another block, otherwise it may not have a virtual register assigned.
469     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
470         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
471       Opcode = I->getOpcode();
472       U = I;
473     }
474   } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
475     Opcode = C->getOpcode();
476     U = C;
477   }
478   switch (Opcode) {
479   default:
480     break;
481   case Instruction::BitCast:
482     // Look through bitcasts.
483     return computeAddress(U->getOperand(0), Addr);
484   case Instruction::GetElementPtr: {
485     Address SavedAddr = Addr;
486     int64_t TmpOffset = Addr.getOffset();
487     // Iterate through the GEP folding the constants into offsets where
488     // we can.
489     gep_type_iterator GTI = gep_type_begin(U);
490     for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
491          ++i, ++GTI) {
492       const Value *Op = *i;
493       if (StructType *STy = GTI.getStructTypeOrNull()) {
494         const StructLayout *SL = DL.getStructLayout(STy);
495         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
496         TmpOffset += SL->getElementOffset(Idx);
497       } else {
498         uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
499         while (true) {
500           if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
501             // Constant-offset addressing.
502             TmpOffset += CI->getSExtValue() * S;
503             break;
504           }
505           if (canFoldAddIntoGEP(U, Op)) {
506             // A compatible add with a constant operand. Fold the constant.
507             ConstantInt *CI =
508                 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
509             TmpOffset += CI->getSExtValue() * S;
510             // Iterate on the other operand.
511             Op = cast<AddOperator>(Op)->getOperand(0);
512             continue;
513           }
514           // Unsupported
515           goto unsupported_gep;
516         }
517       }
518     }
519     // Try to grab the base operand now.
520     Addr.setOffset(TmpOffset);
521     if (computeAddress(U->getOperand(0), Addr))
522       return true;
523     // We failed, restore everything and try the other options.
524     Addr = SavedAddr;
525   unsupported_gep:
526     break;
527   }
528   case Instruction::Alloca: {
529     const AllocaInst *AI = cast<AllocaInst>(Obj);
530     DenseMap<const AllocaInst *, int>::iterator SI =
531         FuncInfo.StaticAllocaMap.find(AI);
532     if (SI != FuncInfo.StaticAllocaMap.end()) {
533       Addr.setKind(Address::FrameIndexBase);
534       Addr.setFI(SI->second);
535       return true;
536     }
537     break;
538   }
539   }
540   Addr.setReg(getRegForValue(Obj));
541   return Addr.getReg() != 0;
542 }
543 
544 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
545   const User *U = nullptr;
546   unsigned Opcode = Instruction::UserOp1;
547 
548   if (const auto *I = dyn_cast<Instruction>(V)) {
549     // Check if the value is defined in the same basic block. This information
550     // is crucial to know whether or not folding an operand is valid.
551     if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
552       Opcode = I->getOpcode();
553       U = I;
554     }
555   } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
556     Opcode = C->getOpcode();
557     U = C;
558   }
559 
560   switch (Opcode) {
561   default:
562     break;
563   case Instruction::BitCast:
564     // Look past bitcasts if its operand is in the same BB.
565       return computeCallAddress(U->getOperand(0), Addr);
566     break;
567   case Instruction::IntToPtr:
568     // Look past no-op inttoptrs if its operand is in the same BB.
569     if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
570         TLI.getPointerTy(DL))
571       return computeCallAddress(U->getOperand(0), Addr);
572     break;
573   case Instruction::PtrToInt:
574     // Look past no-op ptrtoints if its operand is in the same BB.
575     if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
576       return computeCallAddress(U->getOperand(0), Addr);
577     break;
578   }
579 
580   if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
581     Addr.setGlobalValue(GV);
582     return true;
583   }
584 
585   // If all else fails, try to materialize the value in a register.
586   if (!Addr.getGlobalValue()) {
587     Addr.setReg(getRegForValue(V));
588     return Addr.getReg() != 0;
589   }
590 
591   return false;
592 }
593 
594 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
595   EVT evt = TLI.getValueType(DL, Ty, true);
596   // Only handle simple types.
597   if (evt == MVT::Other || !evt.isSimple())
598     return false;
599   VT = evt.getSimpleVT();
600 
601   // Handle all legal types, i.e. a register that will directly hold this
602   // value.
603   return TLI.isTypeLegal(VT);
604 }
605 
606 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
607   if (Ty->isVectorTy())
608     return false;
609 
610   if (isTypeLegal(Ty, VT))
611     return true;
612 
613   // If this is a type than can be sign or zero-extended to a basic operation
614   // go ahead and accept it now.
615   if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
616     return true;
617 
618   return false;
619 }
620 
621 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
622   if (isTypeLegal(Ty, VT))
623     return true;
624   // We will extend this in a later patch:
625   //   If this is a type than can be sign or zero-extended to a basic operation
626   //   go ahead and accept it now.
627   if (VT == MVT::i8 || VT == MVT::i16)
628     return true;
629   return false;
630 }
631 
632 // Because of how EmitCmp is called with fast-isel, you can
633 // end up with redundant "andi" instructions after the sequences emitted below.
634 // We should try and solve this issue in the future.
635 //
636 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
637   const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
638   bool IsUnsigned = CI->isUnsigned();
639   unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
640   if (LeftReg == 0)
641     return false;
642   unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
643   if (RightReg == 0)
644     return false;
645   CmpInst::Predicate P = CI->getPredicate();
646 
647   switch (P) {
648   default:
649     return false;
650   case CmpInst::ICMP_EQ: {
651     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
652     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
653     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
654     break;
655   }
656   case CmpInst::ICMP_NE: {
657     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
658     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
659     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
660     break;
661   }
662   case CmpInst::ICMP_UGT:
663     emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
664     break;
665   case CmpInst::ICMP_ULT:
666     emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
667     break;
668   case CmpInst::ICMP_UGE: {
669     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
670     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
671     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
672     break;
673   }
674   case CmpInst::ICMP_ULE: {
675     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
676     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
677     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
678     break;
679   }
680   case CmpInst::ICMP_SGT:
681     emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
682     break;
683   case CmpInst::ICMP_SLT:
684     emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
685     break;
686   case CmpInst::ICMP_SGE: {
687     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
688     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
689     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
690     break;
691   }
692   case CmpInst::ICMP_SLE: {
693     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
694     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
695     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
696     break;
697   }
698   case CmpInst::FCMP_OEQ:
699   case CmpInst::FCMP_UNE:
700   case CmpInst::FCMP_OLT:
701   case CmpInst::FCMP_OLE:
702   case CmpInst::FCMP_OGT:
703   case CmpInst::FCMP_OGE: {
704     if (UnsupportedFPMode)
705       return false;
706     bool IsFloat = Left->getType()->isFloatTy();
707     bool IsDouble = Left->getType()->isDoubleTy();
708     if (!IsFloat && !IsDouble)
709       return false;
710     unsigned Opc, CondMovOpc;
711     switch (P) {
712     case CmpInst::FCMP_OEQ:
713       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
714       CondMovOpc = Mips::MOVT_I;
715       break;
716     case CmpInst::FCMP_UNE:
717       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
718       CondMovOpc = Mips::MOVF_I;
719       break;
720     case CmpInst::FCMP_OLT:
721       Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
722       CondMovOpc = Mips::MOVT_I;
723       break;
724     case CmpInst::FCMP_OLE:
725       Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
726       CondMovOpc = Mips::MOVT_I;
727       break;
728     case CmpInst::FCMP_OGT:
729       Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
730       CondMovOpc = Mips::MOVF_I;
731       break;
732     case CmpInst::FCMP_OGE:
733       Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
734       CondMovOpc = Mips::MOVF_I;
735       break;
736     default:
737       llvm_unreachable("Only switching of a subset of CCs.");
738     }
739     unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
740     unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
741     emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
742     emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
743     emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
744                  .addReg(RightReg);
745     emitInst(CondMovOpc, ResultReg)
746         .addReg(RegWithOne)
747         .addReg(Mips::FCC0)
748         .addReg(RegWithZero);
749     break;
750   }
751   }
752   return true;
753 }
754 
755 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
756                             unsigned Alignment) {
757   //
758   // more cases will be handled here in following patches.
759   //
760   unsigned Opc;
761   switch (VT.SimpleTy) {
762   case MVT::i32:
763     ResultReg = createResultReg(&Mips::GPR32RegClass);
764     Opc = Mips::LW;
765     break;
766   case MVT::i16:
767     ResultReg = createResultReg(&Mips::GPR32RegClass);
768     Opc = Mips::LHu;
769     break;
770   case MVT::i8:
771     ResultReg = createResultReg(&Mips::GPR32RegClass);
772     Opc = Mips::LBu;
773     break;
774   case MVT::f32:
775     if (UnsupportedFPMode)
776       return false;
777     ResultReg = createResultReg(&Mips::FGR32RegClass);
778     Opc = Mips::LWC1;
779     break;
780   case MVT::f64:
781     if (UnsupportedFPMode)
782       return false;
783     ResultReg = createResultReg(&Mips::AFGR64RegClass);
784     Opc = Mips::LDC1;
785     break;
786   default:
787     return false;
788   }
789   if (Addr.isRegBase()) {
790     simplifyAddress(Addr);
791     emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
792     return true;
793   }
794   if (Addr.isFIBase()) {
795     unsigned FI = Addr.getFI();
796     unsigned Align = 4;
797     int64_t Offset = Addr.getOffset();
798     MachineFrameInfo &MFI = MF->getFrameInfo();
799     MachineMemOperand *MMO = MF->getMachineMemOperand(
800         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
801         MFI.getObjectSize(FI), Align);
802     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
803         .addFrameIndex(FI)
804         .addImm(Offset)
805         .addMemOperand(MMO);
806     return true;
807   }
808   return false;
809 }
810 
811 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
812                              unsigned Alignment) {
813   //
814   // more cases will be handled here in following patches.
815   //
816   unsigned Opc;
817   switch (VT.SimpleTy) {
818   case MVT::i8:
819     Opc = Mips::SB;
820     break;
821   case MVT::i16:
822     Opc = Mips::SH;
823     break;
824   case MVT::i32:
825     Opc = Mips::SW;
826     break;
827   case MVT::f32:
828     if (UnsupportedFPMode)
829       return false;
830     Opc = Mips::SWC1;
831     break;
832   case MVT::f64:
833     if (UnsupportedFPMode)
834       return false;
835     Opc = Mips::SDC1;
836     break;
837   default:
838     return false;
839   }
840   if (Addr.isRegBase()) {
841     simplifyAddress(Addr);
842     emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
843     return true;
844   }
845   if (Addr.isFIBase()) {
846     unsigned FI = Addr.getFI();
847     unsigned Align = 4;
848     int64_t Offset = Addr.getOffset();
849     MachineFrameInfo &MFI = MF->getFrameInfo();
850     MachineMemOperand *MMO = MF->getMachineMemOperand(
851         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
852         MFI.getObjectSize(FI), Align);
853     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
854         .addReg(SrcReg)
855         .addFrameIndex(FI)
856         .addImm(Offset)
857         .addMemOperand(MMO);
858     return true;
859   }
860   return false;
861 }
862 
863 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
864   MVT VT;
865   if (!isTypeSupported(I->getType(), VT))
866     return false;
867 
868   unsigned ResultReg;
869   switch (I->getOpcode()) {
870   default:
871     llvm_unreachable("Unexpected instruction.");
872   case Instruction::And:
873     ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
874     break;
875   case Instruction::Or:
876     ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
877     break;
878   case Instruction::Xor:
879     ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
880     break;
881   }
882 
883   if (!ResultReg)
884     return false;
885 
886   updateValueMap(I, ResultReg);
887   return true;
888 }
889 
890 bool MipsFastISel::selectLoad(const Instruction *I) {
891   // Atomic loads need special handling.
892   if (cast<LoadInst>(I)->isAtomic())
893     return false;
894 
895   // Verify we have a legal type before going any further.
896   MVT VT;
897   if (!isLoadTypeLegal(I->getType(), VT))
898     return false;
899 
900   // See if we can handle this address.
901   Address Addr;
902   if (!computeAddress(I->getOperand(0), Addr))
903     return false;
904 
905   unsigned ResultReg;
906   if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
907     return false;
908   updateValueMap(I, ResultReg);
909   return true;
910 }
911 
912 bool MipsFastISel::selectStore(const Instruction *I) {
913   Value *Op0 = I->getOperand(0);
914   unsigned SrcReg = 0;
915 
916   // Atomic stores need special handling.
917   if (cast<StoreInst>(I)->isAtomic())
918     return false;
919 
920   // Verify we have a legal type before going any further.
921   MVT VT;
922   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
923     return false;
924 
925   // Get the value to be stored into a register.
926   SrcReg = getRegForValue(Op0);
927   if (SrcReg == 0)
928     return false;
929 
930   // See if we can handle this address.
931   Address Addr;
932   if (!computeAddress(I->getOperand(1), Addr))
933     return false;
934 
935   if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
936     return false;
937   return true;
938 }
939 
940 // This can cause a redundant sltiu to be generated.
941 // FIXME: try and eliminate this in a future patch.
942 bool MipsFastISel::selectBranch(const Instruction *I) {
943   const BranchInst *BI = cast<BranchInst>(I);
944   MachineBasicBlock *BrBB = FuncInfo.MBB;
945   //
946   // TBB is the basic block for the case where the comparison is true.
947   // FBB is the basic block for the case where the comparison is false.
948   // if (cond) goto TBB
949   // goto FBB
950   // TBB:
951   //
952   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
953   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
954   BI->getCondition();
955   // For now, just try the simplest case where it's fed by a compare.
956   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
957     unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
958     if (!emitCmp(CondReg, CI))
959       return false;
960     BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
961         .addReg(CondReg)
962         .addMBB(TBB);
963     finishCondBranch(BI->getParent(), TBB, FBB);
964     return true;
965   }
966   return false;
967 }
968 
969 bool MipsFastISel::selectCmp(const Instruction *I) {
970   const CmpInst *CI = cast<CmpInst>(I);
971   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
972   if (!emitCmp(ResultReg, CI))
973     return false;
974   updateValueMap(I, ResultReg);
975   return true;
976 }
977 
978 // Attempt to fast-select a floating-point extend instruction.
979 bool MipsFastISel::selectFPExt(const Instruction *I) {
980   if (UnsupportedFPMode)
981     return false;
982   Value *Src = I->getOperand(0);
983   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
984   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
985 
986   if (SrcVT != MVT::f32 || DestVT != MVT::f64)
987     return false;
988 
989   unsigned SrcReg =
990       getRegForValue(Src); // this must be a 32bit floating point register class
991                            // maybe we should handle this differently
992   if (!SrcReg)
993     return false;
994 
995   unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
996   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
997   updateValueMap(I, DestReg);
998   return true;
999 }
1000 
1001 bool MipsFastISel::selectSelect(const Instruction *I) {
1002   assert(isa<SelectInst>(I) && "Expected a select instruction.");
1003 
1004   DEBUG(dbgs() << "selectSelect\n");
1005 
1006   MVT VT;
1007   if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1008     DEBUG(dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1009     return false;
1010   }
1011 
1012   unsigned CondMovOpc;
1013   const TargetRegisterClass *RC;
1014 
1015   if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1016     CondMovOpc = Mips::MOVN_I_I;
1017     RC = &Mips::GPR32RegClass;
1018   } else if (VT == MVT::f32) {
1019     CondMovOpc = Mips::MOVN_I_S;
1020     RC = &Mips::FGR32RegClass;
1021   } else if (VT == MVT::f64) {
1022     CondMovOpc = Mips::MOVN_I_D32;
1023     RC = &Mips::AFGR64RegClass;
1024   } else
1025     return false;
1026 
1027   const SelectInst *SI = cast<SelectInst>(I);
1028   const Value *Cond = SI->getCondition();
1029   unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1030   unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1031   unsigned CondReg = getRegForValue(Cond);
1032 
1033   if (!Src1Reg || !Src2Reg || !CondReg)
1034     return false;
1035 
1036   unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1037   if (!ZExtCondReg)
1038     return false;
1039 
1040   if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1041     return false;
1042 
1043   unsigned ResultReg = createResultReg(RC);
1044   unsigned TempReg = createResultReg(RC);
1045 
1046   if (!ResultReg || !TempReg)
1047     return false;
1048 
1049   emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1050   emitInst(CondMovOpc, ResultReg)
1051     .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1052   updateValueMap(I, ResultReg);
1053   return true;
1054 }
1055 
1056 // Attempt to fast-select a floating-point truncate instruction.
1057 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1058   if (UnsupportedFPMode)
1059     return false;
1060   Value *Src = I->getOperand(0);
1061   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1062   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1063 
1064   if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1065     return false;
1066 
1067   unsigned SrcReg = getRegForValue(Src);
1068   if (!SrcReg)
1069     return false;
1070 
1071   unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1072   if (!DestReg)
1073     return false;
1074 
1075   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1076   updateValueMap(I, DestReg);
1077   return true;
1078 }
1079 
1080 // Attempt to fast-select a floating-point-to-integer conversion.
1081 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1082   if (UnsupportedFPMode)
1083     return false;
1084   MVT DstVT, SrcVT;
1085   if (!IsSigned)
1086     return false; // We don't handle this case yet. There is no native
1087                   // instruction for this but it can be synthesized.
1088   Type *DstTy = I->getType();
1089   if (!isTypeLegal(DstTy, DstVT))
1090     return false;
1091 
1092   if (DstVT != MVT::i32)
1093     return false;
1094 
1095   Value *Src = I->getOperand(0);
1096   Type *SrcTy = Src->getType();
1097   if (!isTypeLegal(SrcTy, SrcVT))
1098     return false;
1099 
1100   if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1101     return false;
1102 
1103   unsigned SrcReg = getRegForValue(Src);
1104   if (SrcReg == 0)
1105     return false;
1106 
1107   // Determine the opcode for the conversion, which takes place
1108   // entirely within FPRs.
1109   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1110   unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1111   unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1112 
1113   // Generate the convert.
1114   emitInst(Opc, TempReg).addReg(SrcReg);
1115   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1116 
1117   updateValueMap(I, DestReg);
1118   return true;
1119 }
1120 
1121 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1122                                    SmallVectorImpl<MVT> &OutVTs,
1123                                    unsigned &NumBytes) {
1124   CallingConv::ID CC = CLI.CallConv;
1125   SmallVector<CCValAssign, 16> ArgLocs;
1126   CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1127   CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1128   // Get a count of how many bytes are to be pushed on the stack.
1129   NumBytes = CCInfo.getNextStackOffset();
1130   // This is the minimum argument area used for A0-A3.
1131   if (NumBytes < 16)
1132     NumBytes = 16;
1133 
1134   emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1135   // Process the args.
1136   MVT firstMVT;
1137   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1138     CCValAssign &VA = ArgLocs[i];
1139     const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1140     MVT ArgVT = OutVTs[VA.getValNo()];
1141 
1142     if (i == 0) {
1143       firstMVT = ArgVT;
1144       if (ArgVT == MVT::f32) {
1145         VA.convertToReg(Mips::F12);
1146       } else if (ArgVT == MVT::f64) {
1147         VA.convertToReg(Mips::D6);
1148       }
1149     } else if (i == 1) {
1150       if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1151         if (ArgVT == MVT::f32) {
1152           VA.convertToReg(Mips::F14);
1153         } else if (ArgVT == MVT::f64) {
1154           VA.convertToReg(Mips::D7);
1155         }
1156       }
1157     }
1158     if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1159          (ArgVT == MVT::i8)) &&
1160         VA.isMemLoc()) {
1161       switch (VA.getLocMemOffset()) {
1162       case 0:
1163         VA.convertToReg(Mips::A0);
1164         break;
1165       case 4:
1166         VA.convertToReg(Mips::A1);
1167         break;
1168       case 8:
1169         VA.convertToReg(Mips::A2);
1170         break;
1171       case 12:
1172         VA.convertToReg(Mips::A3);
1173         break;
1174       default:
1175         break;
1176       }
1177     }
1178     unsigned ArgReg = getRegForValue(ArgVal);
1179     if (!ArgReg)
1180       return false;
1181 
1182     // Handle arg promotion: SExt, ZExt, AExt.
1183     switch (VA.getLocInfo()) {
1184     case CCValAssign::Full:
1185       break;
1186     case CCValAssign::AExt:
1187     case CCValAssign::SExt: {
1188       MVT DestVT = VA.getLocVT();
1189       MVT SrcVT = ArgVT;
1190       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1191       if (!ArgReg)
1192         return false;
1193       break;
1194     }
1195     case CCValAssign::ZExt: {
1196       MVT DestVT = VA.getLocVT();
1197       MVT SrcVT = ArgVT;
1198       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1199       if (!ArgReg)
1200         return false;
1201       break;
1202     }
1203     default:
1204       llvm_unreachable("Unknown arg promotion!");
1205     }
1206 
1207     // Now copy/store arg to correct locations.
1208     if (VA.isRegLoc() && !VA.needsCustom()) {
1209       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1210               TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1211       CLI.OutRegs.push_back(VA.getLocReg());
1212     } else if (VA.needsCustom()) {
1213       llvm_unreachable("Mips does not use custom args.");
1214       return false;
1215     } else {
1216       //
1217       // FIXME: This path will currently return false. It was copied
1218       // from the AArch64 port and should be essentially fine for Mips too.
1219       // The work to finish up this path will be done in a follow-on patch.
1220       //
1221       assert(VA.isMemLoc() && "Assuming store on stack.");
1222       // Don't emit stores for undef values.
1223       if (isa<UndefValue>(ArgVal))
1224         continue;
1225 
1226       // Need to store on the stack.
1227       // FIXME: This alignment is incorrect but this path is disabled
1228       // for now (will return false). We need to determine the right alignment
1229       // based on the normal alignment for the underlying machine type.
1230       //
1231       unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1232 
1233       unsigned BEAlign = 0;
1234       if (ArgSize < 8 && !Subtarget->isLittle())
1235         BEAlign = 8 - ArgSize;
1236 
1237       Address Addr;
1238       Addr.setKind(Address::RegBase);
1239       Addr.setReg(Mips::SP);
1240       Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1241 
1242       unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1243       MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1244           MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1245           MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1246       (void)(MMO);
1247       // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1248       return false; // can't store on the stack yet.
1249     }
1250   }
1251 
1252   return true;
1253 }
1254 
1255 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1256                               unsigned NumBytes) {
1257   CallingConv::ID CC = CLI.CallConv;
1258   emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1259   if (RetVT != MVT::isVoid) {
1260     SmallVector<CCValAssign, 16> RVLocs;
1261     MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1262 
1263     CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1264                              CLI.Symbol ? CLI.Symbol->getName().data()
1265                                         : nullptr);
1266 
1267     // Only handle a single return value.
1268     if (RVLocs.size() != 1)
1269       return false;
1270     // Copy all of the result registers out of their specified physreg.
1271     MVT CopyVT = RVLocs[0].getValVT();
1272     // Special handling for extended integers.
1273     if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1274       CopyVT = MVT::i32;
1275 
1276     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1277     if (!ResultReg)
1278       return false;
1279     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1280             TII.get(TargetOpcode::COPY),
1281             ResultReg).addReg(RVLocs[0].getLocReg());
1282     CLI.InRegs.push_back(RVLocs[0].getLocReg());
1283 
1284     CLI.ResultReg = ResultReg;
1285     CLI.NumResultRegs = 1;
1286   }
1287   return true;
1288 }
1289 
1290 bool MipsFastISel::fastLowerArguments() {
1291   DEBUG(dbgs() << "fastLowerArguments\n");
1292 
1293   if (!FuncInfo.CanLowerReturn) {
1294     DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1295     return false;
1296   }
1297 
1298   const Function *F = FuncInfo.Fn;
1299   if (F->isVarArg()) {
1300     DEBUG(dbgs() << ".. gave up (varargs)\n");
1301     return false;
1302   }
1303 
1304   CallingConv::ID CC = F->getCallingConv();
1305   if (CC != CallingConv::C) {
1306     DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1307     return false;
1308   }
1309 
1310   std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1311                                            Mips::A3}};
1312   std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1313   std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1314   auto NextGPR32 = GPR32ArgRegs.begin();
1315   auto NextFGR32 = FGR32ArgRegs.begin();
1316   auto NextAFGR64 = AFGR64ArgRegs.begin();
1317 
1318   struct AllocatedReg {
1319     const TargetRegisterClass *RC;
1320     unsigned Reg;
1321     AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1322         : RC(RC), Reg(Reg) {}
1323   };
1324 
1325   // Only handle simple cases. i.e. All arguments are directly mapped to
1326   // registers of the appropriate type.
1327   SmallVector<AllocatedReg, 4> Allocation;
1328   for (const auto &FormalArg : F->args()) {
1329     if (FormalArg.hasAttribute(Attribute::InReg) ||
1330         FormalArg.hasAttribute(Attribute::StructRet) ||
1331         FormalArg.hasAttribute(Attribute::ByVal)) {
1332       DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1333       return false;
1334     }
1335 
1336     Type *ArgTy = FormalArg.getType();
1337     if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1338       DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1339       return false;
1340     }
1341 
1342     EVT ArgVT = TLI.getValueType(DL, ArgTy);
1343     DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1344                  << ArgVT.getEVTString() << "\n");
1345     if (!ArgVT.isSimple()) {
1346       DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1347       return false;
1348     }
1349 
1350     switch (ArgVT.getSimpleVT().SimpleTy) {
1351     case MVT::i1:
1352     case MVT::i8:
1353     case MVT::i16:
1354       if (!FormalArg.hasAttribute(Attribute::SExt) &&
1355           !FormalArg.hasAttribute(Attribute::ZExt)) {
1356         // It must be any extend, this shouldn't happen for clang-generated IR
1357         // so just fall back on SelectionDAG.
1358         DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1359         return false;
1360       }
1361 
1362       if (NextGPR32 == GPR32ArgRegs.end()) {
1363         DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1364         return false;
1365       }
1366 
1367       DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1368       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1369 
1370       // Allocating any GPR32 prohibits further use of floating point arguments.
1371       NextFGR32 = FGR32ArgRegs.end();
1372       NextAFGR64 = AFGR64ArgRegs.end();
1373       break;
1374 
1375     case MVT::i32:
1376       if (FormalArg.hasAttribute(Attribute::ZExt)) {
1377         // The O32 ABI does not permit a zero-extended i32.
1378         DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1379         return false;
1380       }
1381 
1382       if (NextGPR32 == GPR32ArgRegs.end()) {
1383         DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1384         return false;
1385       }
1386 
1387       DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1388       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1389 
1390       // Allocating any GPR32 prohibits further use of floating point arguments.
1391       NextFGR32 = FGR32ArgRegs.end();
1392       NextAFGR64 = AFGR64ArgRegs.end();
1393       break;
1394 
1395     case MVT::f32:
1396       if (UnsupportedFPMode) {
1397         DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1398         return false;
1399       }
1400       if (NextFGR32 == FGR32ArgRegs.end()) {
1401         DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1402         return false;
1403       }
1404       DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1405       Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1406       // Allocating an FGR32 also allocates the super-register AFGR64, and
1407       // ABI rules require us to skip the corresponding GPR32.
1408       if (NextGPR32 != GPR32ArgRegs.end())
1409         NextGPR32++;
1410       if (NextAFGR64 != AFGR64ArgRegs.end())
1411         NextAFGR64++;
1412       break;
1413 
1414     case MVT::f64:
1415       if (UnsupportedFPMode) {
1416         DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1417         return false;
1418       }
1419       if (NextAFGR64 == AFGR64ArgRegs.end()) {
1420         DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1421         return false;
1422       }
1423       DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1424       Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1425       // Allocating an FGR32 also allocates the super-register AFGR64, and
1426       // ABI rules require us to skip the corresponding GPR32 pair.
1427       if (NextGPR32 != GPR32ArgRegs.end())
1428         NextGPR32++;
1429       if (NextGPR32 != GPR32ArgRegs.end())
1430         NextGPR32++;
1431       if (NextFGR32 != FGR32ArgRegs.end())
1432         NextFGR32++;
1433       break;
1434 
1435     default:
1436       DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1437       return false;
1438     }
1439   }
1440 
1441   for (const auto &FormalArg : F->args()) {
1442     unsigned ArgNo = FormalArg.getArgNo();
1443     unsigned SrcReg = Allocation[ArgNo].Reg;
1444     unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1445     // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1446     // Without this, EmitLiveInCopies may eliminate the livein if its only
1447     // use is a bitcast (which isn't turned into an instruction).
1448     unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1449     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1450             TII.get(TargetOpcode::COPY), ResultReg)
1451         .addReg(DstReg, getKillRegState(true));
1452     updateValueMap(&FormalArg, ResultReg);
1453   }
1454 
1455   // Calculate the size of the incoming arguments area.
1456   // We currently reject all the cases where this would be non-zero.
1457   unsigned IncomingArgSizeInBytes = 0;
1458 
1459   // Account for the reserved argument area on ABI's that have one (O32).
1460   // It seems strange to do this on the caller side but it's necessary in
1461   // SelectionDAG's implementation.
1462   IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1463                                     IncomingArgSizeInBytes);
1464 
1465   MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1466                                                     false);
1467 
1468   return true;
1469 }
1470 
1471 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1472   CallingConv::ID CC = CLI.CallConv;
1473   bool IsTailCall = CLI.IsTailCall;
1474   bool IsVarArg = CLI.IsVarArg;
1475   const Value *Callee = CLI.Callee;
1476   MCSymbol *Symbol = CLI.Symbol;
1477 
1478   // Do not handle FastCC.
1479   if (CC == CallingConv::Fast)
1480     return false;
1481 
1482   // Allow SelectionDAG isel to handle tail calls.
1483   if (IsTailCall)
1484     return false;
1485 
1486   // Let SDISel handle vararg functions.
1487   if (IsVarArg)
1488     return false;
1489 
1490   // FIXME: Only handle *simple* calls for now.
1491   MVT RetVT;
1492   if (CLI.RetTy->isVoidTy())
1493     RetVT = MVT::isVoid;
1494   else if (!isTypeSupported(CLI.RetTy, RetVT))
1495     return false;
1496 
1497   for (auto Flag : CLI.OutFlags)
1498     if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1499       return false;
1500 
1501   // Set up the argument vectors.
1502   SmallVector<MVT, 16> OutVTs;
1503   OutVTs.reserve(CLI.OutVals.size());
1504 
1505   for (auto *Val : CLI.OutVals) {
1506     MVT VT;
1507     if (!isTypeLegal(Val->getType(), VT) &&
1508         !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1509       return false;
1510 
1511     // We don't handle vector parameters yet.
1512     if (VT.isVector() || VT.getSizeInBits() > 64)
1513       return false;
1514 
1515     OutVTs.push_back(VT);
1516   }
1517 
1518   Address Addr;
1519   if (!computeCallAddress(Callee, Addr))
1520     return false;
1521 
1522   // Handle the arguments now that we've gotten them.
1523   unsigned NumBytes;
1524   if (!processCallArgs(CLI, OutVTs, NumBytes))
1525     return false;
1526 
1527   if (!Addr.getGlobalValue())
1528     return false;
1529 
1530   // Issue the call.
1531   unsigned DestAddress;
1532   if (Symbol)
1533     DestAddress = materializeExternalCallSym(Symbol);
1534   else
1535     DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1536   emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1537   MachineInstrBuilder MIB =
1538       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1539               Mips::RA).addReg(Mips::T9);
1540 
1541   // Add implicit physical register uses to the call.
1542   for (auto Reg : CLI.OutRegs)
1543     MIB.addReg(Reg, RegState::Implicit);
1544 
1545   // Add a register mask with the call-preserved registers.
1546   // Proper defs for return values will be added by setPhysRegsDeadExcept().
1547   MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1548 
1549   CLI.Call = MIB;
1550 
1551   // Finish off the call including any return values.
1552   return finishCall(CLI, RetVT, NumBytes);
1553 }
1554 
1555 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1556   switch (II->getIntrinsicID()) {
1557   default:
1558     return false;
1559   case Intrinsic::bswap: {
1560     Type *RetTy = II->getCalledFunction()->getReturnType();
1561 
1562     MVT VT;
1563     if (!isTypeSupported(RetTy, VT))
1564       return false;
1565 
1566     unsigned SrcReg = getRegForValue(II->getOperand(0));
1567     if (SrcReg == 0)
1568       return false;
1569     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1570     if (DestReg == 0)
1571       return false;
1572     if (VT == MVT::i16) {
1573       if (Subtarget->hasMips32r2()) {
1574         emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1575         updateValueMap(II, DestReg);
1576         return true;
1577       } else {
1578         unsigned TempReg[3];
1579         for (int i = 0; i < 3; i++) {
1580           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1581           if (TempReg[i] == 0)
1582             return false;
1583         }
1584         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1585         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1586         emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1587         emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1588         updateValueMap(II, DestReg);
1589         return true;
1590       }
1591     } else if (VT == MVT::i32) {
1592       if (Subtarget->hasMips32r2()) {
1593         unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1594         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1595         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1596         updateValueMap(II, DestReg);
1597         return true;
1598       } else {
1599         unsigned TempReg[8];
1600         for (int i = 0; i < 8; i++) {
1601           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1602           if (TempReg[i] == 0)
1603             return false;
1604         }
1605 
1606         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1607         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1608         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1609         emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1610 
1611         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1612         emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1613 
1614         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1615         emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1616         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1617         updateValueMap(II, DestReg);
1618         return true;
1619       }
1620     }
1621     return false;
1622   }
1623   case Intrinsic::memcpy:
1624   case Intrinsic::memmove: {
1625     const auto *MTI = cast<MemTransferInst>(II);
1626     // Don't handle volatile.
1627     if (MTI->isVolatile())
1628       return false;
1629     if (!MTI->getLength()->getType()->isIntegerTy(32))
1630       return false;
1631     const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1632     return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1633   }
1634   case Intrinsic::memset: {
1635     const MemSetInst *MSI = cast<MemSetInst>(II);
1636     // Don't handle volatile.
1637     if (MSI->isVolatile())
1638       return false;
1639     if (!MSI->getLength()->getType()->isIntegerTy(32))
1640       return false;
1641     return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1642   }
1643   }
1644   return false;
1645 }
1646 
1647 bool MipsFastISel::selectRet(const Instruction *I) {
1648   const Function &F = *I->getParent()->getParent();
1649   const ReturnInst *Ret = cast<ReturnInst>(I);
1650 
1651   DEBUG(dbgs() << "selectRet\n");
1652 
1653   if (!FuncInfo.CanLowerReturn)
1654     return false;
1655 
1656   // Build a list of return value registers.
1657   SmallVector<unsigned, 4> RetRegs;
1658 
1659   if (Ret->getNumOperands() > 0) {
1660     CallingConv::ID CC = F.getCallingConv();
1661 
1662     // Do not handle FastCC.
1663     if (CC == CallingConv::Fast)
1664       return false;
1665 
1666     SmallVector<ISD::OutputArg, 4> Outs;
1667     GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1668 
1669     // Analyze operands of the call, assigning locations to each operand.
1670     SmallVector<CCValAssign, 16> ValLocs;
1671     MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1672                        I->getContext());
1673     CCAssignFn *RetCC = RetCC_Mips;
1674     CCInfo.AnalyzeReturn(Outs, RetCC);
1675 
1676     // Only handle a single return value for now.
1677     if (ValLocs.size() != 1)
1678       return false;
1679 
1680     CCValAssign &VA = ValLocs[0];
1681     const Value *RV = Ret->getOperand(0);
1682 
1683     // Don't bother handling odd stuff for now.
1684     if ((VA.getLocInfo() != CCValAssign::Full) &&
1685         (VA.getLocInfo() != CCValAssign::BCvt))
1686       return false;
1687 
1688     // Only handle register returns for now.
1689     if (!VA.isRegLoc())
1690       return false;
1691 
1692     unsigned Reg = getRegForValue(RV);
1693     if (Reg == 0)
1694       return false;
1695 
1696     unsigned SrcReg = Reg + VA.getValNo();
1697     unsigned DestReg = VA.getLocReg();
1698     // Avoid a cross-class copy. This is very unlikely.
1699     if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1700       return false;
1701 
1702     EVT RVEVT = TLI.getValueType(DL, RV->getType());
1703     if (!RVEVT.isSimple())
1704       return false;
1705 
1706     if (RVEVT.isVector())
1707       return false;
1708 
1709     MVT RVVT = RVEVT.getSimpleVT();
1710     if (RVVT == MVT::f128)
1711       return false;
1712 
1713     // Do not handle FGR64 returns for now.
1714     if (RVVT == MVT::f64 && UnsupportedFPMode) {
1715       DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1716       return false;
1717     }
1718 
1719     MVT DestVT = VA.getValVT();
1720     // Special handling for extended integers.
1721     if (RVVT != DestVT) {
1722       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1723         return false;
1724 
1725       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1726         bool IsZExt = Outs[0].Flags.isZExt();
1727         SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1728         if (SrcReg == 0)
1729           return false;
1730       }
1731     }
1732 
1733     // Make the copy.
1734     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1735             TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1736 
1737     // Add register to return instruction.
1738     RetRegs.push_back(VA.getLocReg());
1739   }
1740   MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1741   for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1742     MIB.addReg(RetRegs[i], RegState::Implicit);
1743   return true;
1744 }
1745 
1746 bool MipsFastISel::selectTrunc(const Instruction *I) {
1747   // The high bits for a type smaller than the register size are assumed to be
1748   // undefined.
1749   Value *Op = I->getOperand(0);
1750 
1751   EVT SrcVT, DestVT;
1752   SrcVT = TLI.getValueType(DL, Op->getType(), true);
1753   DestVT = TLI.getValueType(DL, I->getType(), true);
1754 
1755   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1756     return false;
1757   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1758     return false;
1759 
1760   unsigned SrcReg = getRegForValue(Op);
1761   if (!SrcReg)
1762     return false;
1763 
1764   // Because the high bits are undefined, a truncate doesn't generate
1765   // any code.
1766   updateValueMap(I, SrcReg);
1767   return true;
1768 }
1769 
1770 bool MipsFastISel::selectIntExt(const Instruction *I) {
1771   Type *DestTy = I->getType();
1772   Value *Src = I->getOperand(0);
1773   Type *SrcTy = Src->getType();
1774 
1775   bool isZExt = isa<ZExtInst>(I);
1776   unsigned SrcReg = getRegForValue(Src);
1777   if (!SrcReg)
1778     return false;
1779 
1780   EVT SrcEVT, DestEVT;
1781   SrcEVT = TLI.getValueType(DL, SrcTy, true);
1782   DestEVT = TLI.getValueType(DL, DestTy, true);
1783   if (!SrcEVT.isSimple())
1784     return false;
1785   if (!DestEVT.isSimple())
1786     return false;
1787 
1788   MVT SrcVT = SrcEVT.getSimpleVT();
1789   MVT DestVT = DestEVT.getSimpleVT();
1790   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1791 
1792   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1793     return false;
1794   updateValueMap(I, ResultReg);
1795   return true;
1796 }
1797 
1798 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1799                                    unsigned DestReg) {
1800   unsigned ShiftAmt;
1801   switch (SrcVT.SimpleTy) {
1802   default:
1803     return false;
1804   case MVT::i8:
1805     ShiftAmt = 24;
1806     break;
1807   case MVT::i16:
1808     ShiftAmt = 16;
1809     break;
1810   }
1811   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1812   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1813   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1814   return true;
1815 }
1816 
1817 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1818                                    unsigned DestReg) {
1819   switch (SrcVT.SimpleTy) {
1820   default:
1821     return false;
1822   case MVT::i8:
1823     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1824     break;
1825   case MVT::i16:
1826     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1827     break;
1828   }
1829   return true;
1830 }
1831 
1832 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1833                                unsigned DestReg) {
1834   if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1835     return false;
1836   if (Subtarget->hasMips32r2())
1837     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1838   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1839 }
1840 
1841 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1842                                unsigned DestReg) {
1843   int64_t Imm;
1844 
1845   switch (SrcVT.SimpleTy) {
1846   default:
1847     return false;
1848   case MVT::i1:
1849     Imm = 1;
1850     break;
1851   case MVT::i8:
1852     Imm = 0xff;
1853     break;
1854   case MVT::i16:
1855     Imm = 0xffff;
1856     break;
1857   }
1858 
1859   emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1860   return true;
1861 }
1862 
1863 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1864                               unsigned DestReg, bool IsZExt) {
1865   // FastISel does not have plumbing to deal with extensions where the SrcVT or
1866   // DestVT are odd things, so test to make sure that they are both types we can
1867   // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1868   // bail out to SelectionDAG.
1869   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1870       ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1871     return false;
1872   if (IsZExt)
1873     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1874   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1875 }
1876 
1877 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1878                                   bool isZExt) {
1879   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1880   bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1881   return Success ? DestReg : 0;
1882 }
1883 
1884 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1885   EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1886   if (!DestEVT.isSimple())
1887     return false;
1888 
1889   MVT DestVT = DestEVT.getSimpleVT();
1890   if (DestVT != MVT::i32)
1891     return false;
1892 
1893   unsigned DivOpc;
1894   switch (ISDOpcode) {
1895   default:
1896     return false;
1897   case ISD::SDIV:
1898   case ISD::SREM:
1899     DivOpc = Mips::SDIV;
1900     break;
1901   case ISD::UDIV:
1902   case ISD::UREM:
1903     DivOpc = Mips::UDIV;
1904     break;
1905   }
1906 
1907   unsigned Src0Reg = getRegForValue(I->getOperand(0));
1908   unsigned Src1Reg = getRegForValue(I->getOperand(1));
1909   if (!Src0Reg || !Src1Reg)
1910     return false;
1911 
1912   emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1913   emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1914 
1915   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1916   if (!ResultReg)
1917     return false;
1918 
1919   unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1920                        ? Mips::MFHI
1921                        : Mips::MFLO;
1922   emitInst(MFOpc, ResultReg);
1923 
1924   updateValueMap(I, ResultReg);
1925   return true;
1926 }
1927 
1928 bool MipsFastISel::selectShift(const Instruction *I) {
1929   MVT RetVT;
1930 
1931   if (!isTypeSupported(I->getType(), RetVT))
1932     return false;
1933 
1934   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1935   if (!ResultReg)
1936     return false;
1937 
1938   unsigned Opcode = I->getOpcode();
1939   const Value *Op0 = I->getOperand(0);
1940   unsigned Op0Reg = getRegForValue(Op0);
1941   if (!Op0Reg)
1942     return false;
1943 
1944   // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1945   if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1946     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1947     if (!TempReg)
1948       return false;
1949 
1950     MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1951     bool IsZExt = Opcode == Instruction::LShr;
1952     if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1953       return false;
1954 
1955     Op0Reg = TempReg;
1956   }
1957 
1958   if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1959     uint64_t ShiftVal = C->getZExtValue();
1960 
1961     switch (Opcode) {
1962     default:
1963       llvm_unreachable("Unexpected instruction.");
1964     case Instruction::Shl:
1965       Opcode = Mips::SLL;
1966       break;
1967     case Instruction::AShr:
1968       Opcode = Mips::SRA;
1969       break;
1970     case Instruction::LShr:
1971       Opcode = Mips::SRL;
1972       break;
1973     }
1974 
1975     emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1976     updateValueMap(I, ResultReg);
1977     return true;
1978   }
1979 
1980   unsigned Op1Reg = getRegForValue(I->getOperand(1));
1981   if (!Op1Reg)
1982     return false;
1983 
1984   switch (Opcode) {
1985   default:
1986     llvm_unreachable("Unexpected instruction.");
1987   case Instruction::Shl:
1988     Opcode = Mips::SLLV;
1989     break;
1990   case Instruction::AShr:
1991     Opcode = Mips::SRAV;
1992     break;
1993   case Instruction::LShr:
1994     Opcode = Mips::SRLV;
1995     break;
1996   }
1997 
1998   emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1999   updateValueMap(I, ResultReg);
2000   return true;
2001 }
2002 
2003 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2004   switch (I->getOpcode()) {
2005   default:
2006     break;
2007   case Instruction::Load:
2008     return selectLoad(I);
2009   case Instruction::Store:
2010     return selectStore(I);
2011   case Instruction::SDiv:
2012     if (!selectBinaryOp(I, ISD::SDIV))
2013       return selectDivRem(I, ISD::SDIV);
2014     return true;
2015   case Instruction::UDiv:
2016     if (!selectBinaryOp(I, ISD::UDIV))
2017       return selectDivRem(I, ISD::UDIV);
2018     return true;
2019   case Instruction::SRem:
2020     if (!selectBinaryOp(I, ISD::SREM))
2021       return selectDivRem(I, ISD::SREM);
2022     return true;
2023   case Instruction::URem:
2024     if (!selectBinaryOp(I, ISD::UREM))
2025       return selectDivRem(I, ISD::UREM);
2026     return true;
2027   case Instruction::Shl:
2028   case Instruction::LShr:
2029   case Instruction::AShr:
2030     return selectShift(I);
2031   case Instruction::And:
2032   case Instruction::Or:
2033   case Instruction::Xor:
2034     return selectLogicalOp(I);
2035   case Instruction::Br:
2036     return selectBranch(I);
2037   case Instruction::Ret:
2038     return selectRet(I);
2039   case Instruction::Trunc:
2040     return selectTrunc(I);
2041   case Instruction::ZExt:
2042   case Instruction::SExt:
2043     return selectIntExt(I);
2044   case Instruction::FPTrunc:
2045     return selectFPTrunc(I);
2046   case Instruction::FPExt:
2047     return selectFPExt(I);
2048   case Instruction::FPToSI:
2049     return selectFPToInt(I, /*isSigned*/ true);
2050   case Instruction::FPToUI:
2051     return selectFPToInt(I, /*isSigned*/ false);
2052   case Instruction::ICmp:
2053   case Instruction::FCmp:
2054     return selectCmp(I);
2055   case Instruction::Select:
2056     return selectSelect(I);
2057   }
2058   return false;
2059 }
2060 
2061 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2062                                                            bool IsUnsigned) {
2063   unsigned VReg = getRegForValue(V);
2064   if (VReg == 0)
2065     return 0;
2066   MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2067   if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2068     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2069     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2070       return 0;
2071     VReg = TempReg;
2072   }
2073   return VReg;
2074 }
2075 
2076 void MipsFastISel::simplifyAddress(Address &Addr) {
2077   if (!isInt<16>(Addr.getOffset())) {
2078     unsigned TempReg =
2079         materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2080     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2081     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2082     Addr.setReg(DestReg);
2083     Addr.setOffset(0);
2084   }
2085 }
2086 
2087 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2088                                        const TargetRegisterClass *RC,
2089                                        unsigned Op0, bool Op0IsKill,
2090                                        unsigned Op1, bool Op1IsKill) {
2091   // We treat the MUL instruction in a special way because it clobbers
2092   // the HI0 & LO0 registers. The TableGen definition of this instruction can
2093   // mark these registers only as implicitly defined. As a result, the
2094   // register allocator runs out of registers when this instruction is
2095   // followed by another instruction that defines the same registers too.
2096   // We can fix this by explicitly marking those registers as dead.
2097   if (MachineInstOpcode == Mips::MUL) {
2098     unsigned ResultReg = createResultReg(RC);
2099     const MCInstrDesc &II = TII.get(MachineInstOpcode);
2100     Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2101     Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2102     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2103       .addReg(Op0, getKillRegState(Op0IsKill))
2104       .addReg(Op1, getKillRegState(Op1IsKill))
2105       .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2106       .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
2107     return ResultReg;
2108   }
2109 
2110   return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2111                                    Op1IsKill);
2112 }
2113 
2114 namespace llvm {
2115 
2116 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
2117                                const TargetLibraryInfo *libInfo) {
2118   return new MipsFastISel(funcInfo, libInfo);
2119 }
2120 
2121 } // end namespace llvm
2122