1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file defines the MIPS-specific support for the FastISel class.
12 /// Some of the target-specific code is generated by tablegen in the file
13 /// MipsGenFastISel.inc, which is #included here.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsCCState.h"
20 #include "MipsISelLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsMachineFunction.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Analysis/TargetLibraryInfo.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineMemOperand.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/TargetInstrInfo.h"
40 #include "llvm/CodeGen/TargetLowering.h"
41 #include "llvm/CodeGen/ValueTypes.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/CallingConv.h"
44 #include "llvm/IR/Constant.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DataLayout.h"
47 #include "llvm/IR/Function.h"
48 #include "llvm/IR/GetElementPtrTypeIterator.h"
49 #include "llvm/IR/GlobalValue.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/InstrTypes.h"
52 #include "llvm/IR/Instruction.h"
53 #include "llvm/IR/Instructions.h"
54 #include "llvm/IR/IntrinsicInst.h"
55 #include "llvm/IR/Operator.h"
56 #include "llvm/IR/Type.h"
57 #include "llvm/IR/User.h"
58 #include "llvm/IR/Value.h"
59 #include "llvm/MC/MCInstrDesc.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/MC/MCSymbol.h"
62 #include "llvm/Support/Casting.h"
63 #include "llvm/Support/Compiler.h"
64 #include "llvm/Support/Debug.h"
65 #include "llvm/Support/ErrorHandling.h"
66 #include "llvm/Support/MachineValueType.h"
67 #include "llvm/Support/MathExtras.h"
68 #include "llvm/Support/raw_ostream.h"
69 #include <algorithm>
70 #include <array>
71 #include <cassert>
72 #include <cstdint>
73 
74 #define DEBUG_TYPE "mips-fastisel"
75 
76 using namespace llvm;
77 
78 namespace {
79 
80 class MipsFastISel final : public FastISel {
81 
82   // All possible address modes.
83   class Address {
84   public:
85     using BaseKind = enum { RegBase, FrameIndexBase };
86 
87   private:
88     BaseKind Kind = RegBase;
89     union {
90       unsigned Reg;
91       int FI;
92     } Base;
93 
94     int64_t Offset = 0;
95 
96     const GlobalValue *GV = nullptr;
97 
98   public:
99     // Innocuous defaults for our address.
100     Address() { Base.Reg = 0; }
101 
102     void setKind(BaseKind K) { Kind = K; }
103     BaseKind getKind() const { return Kind; }
104     bool isRegBase() const { return Kind == RegBase; }
105     bool isFIBase() const { return Kind == FrameIndexBase; }
106 
107     void setReg(unsigned Reg) {
108       assert(isRegBase() && "Invalid base register access!");
109       Base.Reg = Reg;
110     }
111 
112     unsigned getReg() const {
113       assert(isRegBase() && "Invalid base register access!");
114       return Base.Reg;
115     }
116 
117     void setFI(unsigned FI) {
118       assert(isFIBase() && "Invalid base frame index access!");
119       Base.FI = FI;
120     }
121 
122     unsigned getFI() const {
123       assert(isFIBase() && "Invalid base frame index access!");
124       return Base.FI;
125     }
126 
127     void setOffset(int64_t Offset_) { Offset = Offset_; }
128     int64_t getOffset() const { return Offset; }
129     void setGlobalValue(const GlobalValue *G) { GV = G; }
130     const GlobalValue *getGlobalValue() { return GV; }
131   };
132 
133   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
134   /// make the right decision when generating code for different targets.
135   const TargetMachine &TM;
136   const MipsSubtarget *Subtarget;
137   const TargetInstrInfo &TII;
138   const TargetLowering &TLI;
139   MipsFunctionInfo *MFI;
140 
141   // Convenience variables to avoid some queries.
142   LLVMContext *Context;
143 
144   bool fastLowerArguments() override;
145   bool fastLowerCall(CallLoweringInfo &CLI) override;
146   bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
147 
148   bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
149   // floating point but not reject doing fast-isel in other
150   // situations
151 
152 private:
153   // Selection routines.
154   bool selectLogicalOp(const Instruction *I);
155   bool selectLoad(const Instruction *I);
156   bool selectStore(const Instruction *I);
157   bool selectBranch(const Instruction *I);
158   bool selectSelect(const Instruction *I);
159   bool selectCmp(const Instruction *I);
160   bool selectFPExt(const Instruction *I);
161   bool selectFPTrunc(const Instruction *I);
162   bool selectFPToInt(const Instruction *I, bool IsSigned);
163   bool selectRet(const Instruction *I);
164   bool selectTrunc(const Instruction *I);
165   bool selectIntExt(const Instruction *I);
166   bool selectShift(const Instruction *I);
167   bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
168 
169   // Utility helper routines.
170   bool isTypeLegal(Type *Ty, MVT &VT);
171   bool isTypeSupported(Type *Ty, MVT &VT);
172   bool isLoadTypeLegal(Type *Ty, MVT &VT);
173   bool computeAddress(const Value *Obj, Address &Addr);
174   bool computeCallAddress(const Value *V, Address &Addr);
175   void simplifyAddress(Address &Addr);
176 
177   // Emit helper routines.
178   bool emitCmp(unsigned DestReg, const CmpInst *CI);
179   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
180                 unsigned Alignment = 0);
181   bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
182                  MachineMemOperand *MMO = nullptr);
183   bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
184                  unsigned Alignment = 0);
185   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
186   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 
188                   bool IsZExt);
189   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 
191   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
192   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
193                        unsigned DestReg);
194   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
195                        unsigned DestReg);
196 
197   unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
198 
199   unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
200                          const Value *RHS);
201 
202   unsigned materializeFP(const ConstantFP *CFP, MVT VT);
203   unsigned materializeGV(const GlobalValue *GV, MVT VT);
204   unsigned materializeInt(const Constant *C, MVT VT);
205   unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
206   unsigned materializeExternalCallSym(MCSymbol *Syn);
207 
208   MachineInstrBuilder emitInst(unsigned Opc) {
209     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
210   }
211 
212   MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
213     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
214                    DstReg);
215   }
216 
217   MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
218                                     unsigned MemReg, int64_t MemOffset) {
219     return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
220   }
221 
222   MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
223                                    unsigned MemReg, int64_t MemOffset) {
224     return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
225   }
226 
227   unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
228                            const TargetRegisterClass *RC,
229                            unsigned Op0, bool Op0IsKill,
230                            unsigned Op1, bool Op1IsKill);
231 
232   // for some reason, this default is not generated by tablegen
233   // so we explicitly generate it here.
234   unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
235                              unsigned Op0, bool Op0IsKill, uint64_t imm1,
236                              uint64_t imm2, unsigned Op3, bool Op3IsKill) {
237     return 0;
238   }
239 
240   // Call handling routines.
241 private:
242   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
243   bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
244                        unsigned &NumBytes);
245   bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
246 
247   const MipsABIInfo &getABI() const {
248     return static_cast<const MipsTargetMachine &>(TM).getABI();
249   }
250 
251 public:
252   // Backend specific FastISel code.
253   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
254                         const TargetLibraryInfo *libInfo)
255       : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
256         Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
257         TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
258     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
259     Context = &funcInfo.Fn->getContext();
260     UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
261   }
262 
263   unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
264   unsigned fastMaterializeConstant(const Constant *C) override;
265   bool fastSelectInstruction(const Instruction *I) override;
266 
267 #include "MipsGenFastISel.inc"
268 };
269 
270 } // end anonymous namespace
271 
272 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
273                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
274                     CCState &State) LLVM_ATTRIBUTE_UNUSED;
275 
276 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
277                             CCValAssign::LocInfo LocInfo,
278                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
279   llvm_unreachable("should not be called");
280 }
281 
282 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
283                             CCValAssign::LocInfo LocInfo,
284                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
285   llvm_unreachable("should not be called");
286 }
287 
288 #include "MipsGenCallingConv.inc"
289 
290 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
291   return CC_MipsO32;
292 }
293 
294 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
295                                      const Value *LHS, const Value *RHS) {
296   // Canonicalize immediates to the RHS first.
297   if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
298     std::swap(LHS, RHS);
299 
300   unsigned Opc;
301   switch (ISDOpc) {
302   case ISD::AND:
303     Opc = Mips::AND;
304     break;
305   case ISD::OR:
306     Opc = Mips::OR;
307     break;
308   case ISD::XOR:
309     Opc = Mips::XOR;
310     break;
311   default:
312     llvm_unreachable("unexpected opcode");
313   }
314 
315   unsigned LHSReg = getRegForValue(LHS);
316   if (!LHSReg)
317     return 0;
318 
319   unsigned RHSReg;
320   if (const auto *C = dyn_cast<ConstantInt>(RHS))
321     RHSReg = materializeInt(C, MVT::i32);
322   else
323     RHSReg = getRegForValue(RHS);
324   if (!RHSReg)
325     return 0;
326 
327   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
328   if (!ResultReg)
329     return 0;
330 
331   emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
332   return ResultReg;
333 }
334 
335 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
336   assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
337          "Alloca should always return a pointer.");
338 
339   DenseMap<const AllocaInst *, int>::iterator SI =
340       FuncInfo.StaticAllocaMap.find(AI);
341 
342   if (SI != FuncInfo.StaticAllocaMap.end()) {
343     unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
344     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
345             ResultReg)
346         .addFrameIndex(SI->second)
347         .addImm(0);
348     return ResultReg;
349   }
350 
351   return 0;
352 }
353 
354 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
355   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
356     return 0;
357   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
358   const ConstantInt *CI = cast<ConstantInt>(C);
359   return materialize32BitInt(CI->getZExtValue(), RC);
360 }
361 
362 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
363                                            const TargetRegisterClass *RC) {
364   unsigned ResultReg = createResultReg(RC);
365 
366   if (isInt<16>(Imm)) {
367     unsigned Opc = Mips::ADDiu;
368     emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
369     return ResultReg;
370   } else if (isUInt<16>(Imm)) {
371     emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
372     return ResultReg;
373   }
374   unsigned Lo = Imm & 0xFFFF;
375   unsigned Hi = (Imm >> 16) & 0xFFFF;
376   if (Lo) {
377     // Both Lo and Hi have nonzero bits.
378     unsigned TmpReg = createResultReg(RC);
379     emitInst(Mips::LUi, TmpReg).addImm(Hi);
380     emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
381   } else {
382     emitInst(Mips::LUi, ResultReg).addImm(Hi);
383   }
384   return ResultReg;
385 }
386 
387 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
388   if (UnsupportedFPMode)
389     return 0;
390   int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
391   if (VT == MVT::f32) {
392     const TargetRegisterClass *RC = &Mips::FGR32RegClass;
393     unsigned DestReg = createResultReg(RC);
394     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
395     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
396     return DestReg;
397   } else if (VT == MVT::f64) {
398     const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
399     unsigned DestReg = createResultReg(RC);
400     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
401     unsigned TempReg2 =
402         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
403     emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
404     return DestReg;
405   }
406   return 0;
407 }
408 
409 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
410   // For now 32-bit only.
411   if (VT != MVT::i32)
412     return 0;
413   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
414   unsigned DestReg = createResultReg(RC);
415   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
416   bool IsThreadLocal = GVar && GVar->isThreadLocal();
417   // TLS not supported at this time.
418   if (IsThreadLocal)
419     return 0;
420   emitInst(Mips::LW, DestReg)
421       .addReg(MFI->getGlobalBaseReg())
422       .addGlobalAddress(GV, 0, MipsII::MO_GOT);
423   if ((GV->hasInternalLinkage() ||
424        (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
425     unsigned TempReg = createResultReg(RC);
426     emitInst(Mips::ADDiu, TempReg)
427         .addReg(DestReg)
428         .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
429     DestReg = TempReg;
430   }
431   return DestReg;
432 }
433 
434 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
435   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
436   unsigned DestReg = createResultReg(RC);
437   emitInst(Mips::LW, DestReg)
438       .addReg(MFI->getGlobalBaseReg())
439       .addSym(Sym, MipsII::MO_GOT);
440   return DestReg;
441 }
442 
443 // Materialize a constant into a register, and return the register
444 // number (or zero if we failed to handle it).
445 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
446   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
447 
448   // Only handle simple types.
449   if (!CEVT.isSimple())
450     return 0;
451   MVT VT = CEVT.getSimpleVT();
452 
453   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
454     return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
455   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
456     return materializeGV(GV, VT);
457   else if (isa<ConstantInt>(C))
458     return materializeInt(C, VT);
459 
460   return 0;
461 }
462 
463 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
464   const User *U = nullptr;
465   unsigned Opcode = Instruction::UserOp1;
466   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
467     // Don't walk into other basic blocks unless the object is an alloca from
468     // another block, otherwise it may not have a virtual register assigned.
469     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
470         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
471       Opcode = I->getOpcode();
472       U = I;
473     }
474   } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
475     Opcode = C->getOpcode();
476     U = C;
477   }
478   switch (Opcode) {
479   default:
480     break;
481   case Instruction::BitCast:
482     // Look through bitcasts.
483     return computeAddress(U->getOperand(0), Addr);
484   case Instruction::GetElementPtr: {
485     Address SavedAddr = Addr;
486     int64_t TmpOffset = Addr.getOffset();
487     // Iterate through the GEP folding the constants into offsets where
488     // we can.
489     gep_type_iterator GTI = gep_type_begin(U);
490     for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
491          ++i, ++GTI) {
492       const Value *Op = *i;
493       if (StructType *STy = GTI.getStructTypeOrNull()) {
494         const StructLayout *SL = DL.getStructLayout(STy);
495         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
496         TmpOffset += SL->getElementOffset(Idx);
497       } else {
498         uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
499         while (true) {
500           if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
501             // Constant-offset addressing.
502             TmpOffset += CI->getSExtValue() * S;
503             break;
504           }
505           if (canFoldAddIntoGEP(U, Op)) {
506             // A compatible add with a constant operand. Fold the constant.
507             ConstantInt *CI =
508                 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
509             TmpOffset += CI->getSExtValue() * S;
510             // Iterate on the other operand.
511             Op = cast<AddOperator>(Op)->getOperand(0);
512             continue;
513           }
514           // Unsupported
515           goto unsupported_gep;
516         }
517       }
518     }
519     // Try to grab the base operand now.
520     Addr.setOffset(TmpOffset);
521     if (computeAddress(U->getOperand(0), Addr))
522       return true;
523     // We failed, restore everything and try the other options.
524     Addr = SavedAddr;
525   unsupported_gep:
526     break;
527   }
528   case Instruction::Alloca: {
529     const AllocaInst *AI = cast<AllocaInst>(Obj);
530     DenseMap<const AllocaInst *, int>::iterator SI =
531         FuncInfo.StaticAllocaMap.find(AI);
532     if (SI != FuncInfo.StaticAllocaMap.end()) {
533       Addr.setKind(Address::FrameIndexBase);
534       Addr.setFI(SI->second);
535       return true;
536     }
537     break;
538   }
539   }
540   Addr.setReg(getRegForValue(Obj));
541   return Addr.getReg() != 0;
542 }
543 
544 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
545   const User *U = nullptr;
546   unsigned Opcode = Instruction::UserOp1;
547 
548   if (const auto *I = dyn_cast<Instruction>(V)) {
549     // Check if the value is defined in the same basic block. This information
550     // is crucial to know whether or not folding an operand is valid.
551     if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
552       Opcode = I->getOpcode();
553       U = I;
554     }
555   } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
556     Opcode = C->getOpcode();
557     U = C;
558   }
559 
560   switch (Opcode) {
561   default:
562     break;
563   case Instruction::BitCast:
564     // Look past bitcasts if its operand is in the same BB.
565       return computeCallAddress(U->getOperand(0), Addr);
566     break;
567   case Instruction::IntToPtr:
568     // Look past no-op inttoptrs if its operand is in the same BB.
569     if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
570         TLI.getPointerTy(DL))
571       return computeCallAddress(U->getOperand(0), Addr);
572     break;
573   case Instruction::PtrToInt:
574     // Look past no-op ptrtoints if its operand is in the same BB.
575     if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
576       return computeCallAddress(U->getOperand(0), Addr);
577     break;
578   }
579 
580   if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
581     Addr.setGlobalValue(GV);
582     return true;
583   }
584 
585   // If all else fails, try to materialize the value in a register.
586   if (!Addr.getGlobalValue()) {
587     Addr.setReg(getRegForValue(V));
588     return Addr.getReg() != 0;
589   }
590 
591   return false;
592 }
593 
594 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
595   EVT evt = TLI.getValueType(DL, Ty, true);
596   // Only handle simple types.
597   if (evt == MVT::Other || !evt.isSimple())
598     return false;
599   VT = evt.getSimpleVT();
600 
601   // Handle all legal types, i.e. a register that will directly hold this
602   // value.
603   return TLI.isTypeLegal(VT);
604 }
605 
606 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
607   if (Ty->isVectorTy())
608     return false;
609 
610   if (isTypeLegal(Ty, VT))
611     return true;
612 
613   // If this is a type than can be sign or zero-extended to a basic operation
614   // go ahead and accept it now.
615   if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
616     return true;
617 
618   return false;
619 }
620 
621 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
622   if (isTypeLegal(Ty, VT))
623     return true;
624   // We will extend this in a later patch:
625   //   If this is a type than can be sign or zero-extended to a basic operation
626   //   go ahead and accept it now.
627   if (VT == MVT::i8 || VT == MVT::i16)
628     return true;
629   return false;
630 }
631 
632 // Because of how EmitCmp is called with fast-isel, you can
633 // end up with redundant "andi" instructions after the sequences emitted below.
634 // We should try and solve this issue in the future.
635 //
636 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
637   const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
638   bool IsUnsigned = CI->isUnsigned();
639   unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
640   if (LeftReg == 0)
641     return false;
642   unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
643   if (RightReg == 0)
644     return false;
645   CmpInst::Predicate P = CI->getPredicate();
646 
647   switch (P) {
648   default:
649     return false;
650   case CmpInst::ICMP_EQ: {
651     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
652     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
653     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
654     break;
655   }
656   case CmpInst::ICMP_NE: {
657     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
658     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
659     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
660     break;
661   }
662   case CmpInst::ICMP_UGT:
663     emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
664     break;
665   case CmpInst::ICMP_ULT:
666     emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
667     break;
668   case CmpInst::ICMP_UGE: {
669     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
670     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
671     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
672     break;
673   }
674   case CmpInst::ICMP_ULE: {
675     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
676     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
677     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
678     break;
679   }
680   case CmpInst::ICMP_SGT:
681     emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
682     break;
683   case CmpInst::ICMP_SLT:
684     emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
685     break;
686   case CmpInst::ICMP_SGE: {
687     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
688     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
689     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
690     break;
691   }
692   case CmpInst::ICMP_SLE: {
693     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
694     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
695     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
696     break;
697   }
698   case CmpInst::FCMP_OEQ:
699   case CmpInst::FCMP_UNE:
700   case CmpInst::FCMP_OLT:
701   case CmpInst::FCMP_OLE:
702   case CmpInst::FCMP_OGT:
703   case CmpInst::FCMP_OGE: {
704     if (UnsupportedFPMode)
705       return false;
706     bool IsFloat = Left->getType()->isFloatTy();
707     bool IsDouble = Left->getType()->isDoubleTy();
708     if (!IsFloat && !IsDouble)
709       return false;
710     unsigned Opc, CondMovOpc;
711     switch (P) {
712     case CmpInst::FCMP_OEQ:
713       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
714       CondMovOpc = Mips::MOVT_I;
715       break;
716     case CmpInst::FCMP_UNE:
717       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
718       CondMovOpc = Mips::MOVF_I;
719       break;
720     case CmpInst::FCMP_OLT:
721       Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
722       CondMovOpc = Mips::MOVT_I;
723       break;
724     case CmpInst::FCMP_OLE:
725       Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
726       CondMovOpc = Mips::MOVT_I;
727       break;
728     case CmpInst::FCMP_OGT:
729       Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
730       CondMovOpc = Mips::MOVF_I;
731       break;
732     case CmpInst::FCMP_OGE:
733       Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
734       CondMovOpc = Mips::MOVF_I;
735       break;
736     default:
737       llvm_unreachable("Only switching of a subset of CCs.");
738     }
739     unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
740     unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
741     emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
742     emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
743     emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
744                  .addReg(RightReg);
745     emitInst(CondMovOpc, ResultReg)
746         .addReg(RegWithOne)
747         .addReg(Mips::FCC0)
748         .addReg(RegWithZero);
749     break;
750   }
751   }
752   return true;
753 }
754 
755 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
756                             unsigned Alignment) {
757   //
758   // more cases will be handled here in following patches.
759   //
760   unsigned Opc;
761   switch (VT.SimpleTy) {
762   case MVT::i32:
763     ResultReg = createResultReg(&Mips::GPR32RegClass);
764     Opc = Mips::LW;
765     break;
766   case MVT::i16:
767     ResultReg = createResultReg(&Mips::GPR32RegClass);
768     Opc = Mips::LHu;
769     break;
770   case MVT::i8:
771     ResultReg = createResultReg(&Mips::GPR32RegClass);
772     Opc = Mips::LBu;
773     break;
774   case MVT::f32:
775     if (UnsupportedFPMode)
776       return false;
777     ResultReg = createResultReg(&Mips::FGR32RegClass);
778     Opc = Mips::LWC1;
779     break;
780   case MVT::f64:
781     if (UnsupportedFPMode)
782       return false;
783     ResultReg = createResultReg(&Mips::AFGR64RegClass);
784     Opc = Mips::LDC1;
785     break;
786   default:
787     return false;
788   }
789   if (Addr.isRegBase()) {
790     simplifyAddress(Addr);
791     emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
792     return true;
793   }
794   if (Addr.isFIBase()) {
795     unsigned FI = Addr.getFI();
796     unsigned Align = 4;
797     int64_t Offset = Addr.getOffset();
798     MachineFrameInfo &MFI = MF->getFrameInfo();
799     MachineMemOperand *MMO = MF->getMachineMemOperand(
800         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
801         MFI.getObjectSize(FI), Align);
802     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
803         .addFrameIndex(FI)
804         .addImm(Offset)
805         .addMemOperand(MMO);
806     return true;
807   }
808   return false;
809 }
810 
811 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
812                              unsigned Alignment) {
813   //
814   // more cases will be handled here in following patches.
815   //
816   unsigned Opc;
817   switch (VT.SimpleTy) {
818   case MVT::i8:
819     Opc = Mips::SB;
820     break;
821   case MVT::i16:
822     Opc = Mips::SH;
823     break;
824   case MVT::i32:
825     Opc = Mips::SW;
826     break;
827   case MVT::f32:
828     if (UnsupportedFPMode)
829       return false;
830     Opc = Mips::SWC1;
831     break;
832   case MVT::f64:
833     if (UnsupportedFPMode)
834       return false;
835     Opc = Mips::SDC1;
836     break;
837   default:
838     return false;
839   }
840   if (Addr.isRegBase()) {
841     simplifyAddress(Addr);
842     emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
843     return true;
844   }
845   if (Addr.isFIBase()) {
846     unsigned FI = Addr.getFI();
847     unsigned Align = 4;
848     int64_t Offset = Addr.getOffset();
849     MachineFrameInfo &MFI = MF->getFrameInfo();
850     MachineMemOperand *MMO = MF->getMachineMemOperand(
851         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
852         MFI.getObjectSize(FI), Align);
853     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
854         .addReg(SrcReg)
855         .addFrameIndex(FI)
856         .addImm(Offset)
857         .addMemOperand(MMO);
858     return true;
859   }
860   return false;
861 }
862 
863 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
864   MVT VT;
865   if (!isTypeSupported(I->getType(), VT))
866     return false;
867 
868   unsigned ResultReg;
869   switch (I->getOpcode()) {
870   default:
871     llvm_unreachable("Unexpected instruction.");
872   case Instruction::And:
873     ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
874     break;
875   case Instruction::Or:
876     ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
877     break;
878   case Instruction::Xor:
879     ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
880     break;
881   }
882 
883   if (!ResultReg)
884     return false;
885 
886   updateValueMap(I, ResultReg);
887   return true;
888 }
889 
890 bool MipsFastISel::selectLoad(const Instruction *I) {
891   // Atomic loads need special handling.
892   if (cast<LoadInst>(I)->isAtomic())
893     return false;
894 
895   // Verify we have a legal type before going any further.
896   MVT VT;
897   if (!isLoadTypeLegal(I->getType(), VT))
898     return false;
899 
900   // See if we can handle this address.
901   Address Addr;
902   if (!computeAddress(I->getOperand(0), Addr))
903     return false;
904 
905   unsigned ResultReg;
906   if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
907     return false;
908   updateValueMap(I, ResultReg);
909   return true;
910 }
911 
912 bool MipsFastISel::selectStore(const Instruction *I) {
913   Value *Op0 = I->getOperand(0);
914   unsigned SrcReg = 0;
915 
916   // Atomic stores need special handling.
917   if (cast<StoreInst>(I)->isAtomic())
918     return false;
919 
920   // Verify we have a legal type before going any further.
921   MVT VT;
922   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
923     return false;
924 
925   // Get the value to be stored into a register.
926   SrcReg = getRegForValue(Op0);
927   if (SrcReg == 0)
928     return false;
929 
930   // See if we can handle this address.
931   Address Addr;
932   if (!computeAddress(I->getOperand(1), Addr))
933     return false;
934 
935   if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
936     return false;
937   return true;
938 }
939 
940 // This can cause a redundant sltiu to be generated.
941 // FIXME: try and eliminate this in a future patch.
942 bool MipsFastISel::selectBranch(const Instruction *I) {
943   const BranchInst *BI = cast<BranchInst>(I);
944   MachineBasicBlock *BrBB = FuncInfo.MBB;
945   //
946   // TBB is the basic block for the case where the comparison is true.
947   // FBB is the basic block for the case where the comparison is false.
948   // if (cond) goto TBB
949   // goto FBB
950   // TBB:
951   //
952   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
953   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
954   // For now, just try the simplest case where it's fed by a compare.
955   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
956     MVT CIMVT =
957         TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT();
958     if (CIMVT == MVT::i1)
959       return false;
960 
961     unsigned CondReg = getRegForValue(CI);
962     BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
963         .addReg(CondReg)
964         .addMBB(TBB);
965     finishCondBranch(BI->getParent(), TBB, FBB);
966     return true;
967   }
968   return false;
969 }
970 
971 bool MipsFastISel::selectCmp(const Instruction *I) {
972   const CmpInst *CI = cast<CmpInst>(I);
973   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
974   if (!emitCmp(ResultReg, CI))
975     return false;
976   updateValueMap(I, ResultReg);
977   return true;
978 }
979 
980 // Attempt to fast-select a floating-point extend instruction.
981 bool MipsFastISel::selectFPExt(const Instruction *I) {
982   if (UnsupportedFPMode)
983     return false;
984   Value *Src = I->getOperand(0);
985   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
986   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
987 
988   if (SrcVT != MVT::f32 || DestVT != MVT::f64)
989     return false;
990 
991   unsigned SrcReg =
992       getRegForValue(Src); // this must be a 32bit floating point register class
993                            // maybe we should handle this differently
994   if (!SrcReg)
995     return false;
996 
997   unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
998   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
999   updateValueMap(I, DestReg);
1000   return true;
1001 }
1002 
1003 bool MipsFastISel::selectSelect(const Instruction *I) {
1004   assert(isa<SelectInst>(I) && "Expected a select instruction.");
1005 
1006   LLVM_DEBUG(dbgs() << "selectSelect\n");
1007 
1008   MVT VT;
1009   if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1010     LLVM_DEBUG(
1011         dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1012     return false;
1013   }
1014 
1015   unsigned CondMovOpc;
1016   const TargetRegisterClass *RC;
1017 
1018   if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1019     CondMovOpc = Mips::MOVN_I_I;
1020     RC = &Mips::GPR32RegClass;
1021   } else if (VT == MVT::f32) {
1022     CondMovOpc = Mips::MOVN_I_S;
1023     RC = &Mips::FGR32RegClass;
1024   } else if (VT == MVT::f64) {
1025     CondMovOpc = Mips::MOVN_I_D32;
1026     RC = &Mips::AFGR64RegClass;
1027   } else
1028     return false;
1029 
1030   const SelectInst *SI = cast<SelectInst>(I);
1031   const Value *Cond = SI->getCondition();
1032   unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1033   unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1034   unsigned CondReg = getRegForValue(Cond);
1035 
1036   if (!Src1Reg || !Src2Reg || !CondReg)
1037     return false;
1038 
1039   unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1040   if (!ZExtCondReg)
1041     return false;
1042 
1043   if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1044     return false;
1045 
1046   unsigned ResultReg = createResultReg(RC);
1047   unsigned TempReg = createResultReg(RC);
1048 
1049   if (!ResultReg || !TempReg)
1050     return false;
1051 
1052   emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1053   emitInst(CondMovOpc, ResultReg)
1054     .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1055   updateValueMap(I, ResultReg);
1056   return true;
1057 }
1058 
1059 // Attempt to fast-select a floating-point truncate instruction.
1060 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1061   if (UnsupportedFPMode)
1062     return false;
1063   Value *Src = I->getOperand(0);
1064   EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1065   EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1066 
1067   if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1068     return false;
1069 
1070   unsigned SrcReg = getRegForValue(Src);
1071   if (!SrcReg)
1072     return false;
1073 
1074   unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1075   if (!DestReg)
1076     return false;
1077 
1078   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1079   updateValueMap(I, DestReg);
1080   return true;
1081 }
1082 
1083 // Attempt to fast-select a floating-point-to-integer conversion.
1084 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1085   if (UnsupportedFPMode)
1086     return false;
1087   MVT DstVT, SrcVT;
1088   if (!IsSigned)
1089     return false; // We don't handle this case yet. There is no native
1090                   // instruction for this but it can be synthesized.
1091   Type *DstTy = I->getType();
1092   if (!isTypeLegal(DstTy, DstVT))
1093     return false;
1094 
1095   if (DstVT != MVT::i32)
1096     return false;
1097 
1098   Value *Src = I->getOperand(0);
1099   Type *SrcTy = Src->getType();
1100   if (!isTypeLegal(SrcTy, SrcVT))
1101     return false;
1102 
1103   if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1104     return false;
1105 
1106   unsigned SrcReg = getRegForValue(Src);
1107   if (SrcReg == 0)
1108     return false;
1109 
1110   // Determine the opcode for the conversion, which takes place
1111   // entirely within FPRs.
1112   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1113   unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1114   unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1115 
1116   // Generate the convert.
1117   emitInst(Opc, TempReg).addReg(SrcReg);
1118   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1119 
1120   updateValueMap(I, DestReg);
1121   return true;
1122 }
1123 
1124 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1125                                    SmallVectorImpl<MVT> &OutVTs,
1126                                    unsigned &NumBytes) {
1127   CallingConv::ID CC = CLI.CallConv;
1128   SmallVector<CCValAssign, 16> ArgLocs;
1129   CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1130   CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1131   // Get a count of how many bytes are to be pushed on the stack.
1132   NumBytes = CCInfo.getNextStackOffset();
1133   // This is the minimum argument area used for A0-A3.
1134   if (NumBytes < 16)
1135     NumBytes = 16;
1136 
1137   emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1138   // Process the args.
1139   MVT firstMVT;
1140   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1141     CCValAssign &VA = ArgLocs[i];
1142     const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1143     MVT ArgVT = OutVTs[VA.getValNo()];
1144 
1145     if (i == 0) {
1146       firstMVT = ArgVT;
1147       if (ArgVT == MVT::f32) {
1148         VA.convertToReg(Mips::F12);
1149       } else if (ArgVT == MVT::f64) {
1150         VA.convertToReg(Mips::D6);
1151       }
1152     } else if (i == 1) {
1153       if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1154         if (ArgVT == MVT::f32) {
1155           VA.convertToReg(Mips::F14);
1156         } else if (ArgVT == MVT::f64) {
1157           VA.convertToReg(Mips::D7);
1158         }
1159       }
1160     }
1161     if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1162          (ArgVT == MVT::i8)) &&
1163         VA.isMemLoc()) {
1164       switch (VA.getLocMemOffset()) {
1165       case 0:
1166         VA.convertToReg(Mips::A0);
1167         break;
1168       case 4:
1169         VA.convertToReg(Mips::A1);
1170         break;
1171       case 8:
1172         VA.convertToReg(Mips::A2);
1173         break;
1174       case 12:
1175         VA.convertToReg(Mips::A3);
1176         break;
1177       default:
1178         break;
1179       }
1180     }
1181     unsigned ArgReg = getRegForValue(ArgVal);
1182     if (!ArgReg)
1183       return false;
1184 
1185     // Handle arg promotion: SExt, ZExt, AExt.
1186     switch (VA.getLocInfo()) {
1187     case CCValAssign::Full:
1188       break;
1189     case CCValAssign::AExt:
1190     case CCValAssign::SExt: {
1191       MVT DestVT = VA.getLocVT();
1192       MVT SrcVT = ArgVT;
1193       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1194       if (!ArgReg)
1195         return false;
1196       break;
1197     }
1198     case CCValAssign::ZExt: {
1199       MVT DestVT = VA.getLocVT();
1200       MVT SrcVT = ArgVT;
1201       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1202       if (!ArgReg)
1203         return false;
1204       break;
1205     }
1206     default:
1207       llvm_unreachable("Unknown arg promotion!");
1208     }
1209 
1210     // Now copy/store arg to correct locations.
1211     if (VA.isRegLoc() && !VA.needsCustom()) {
1212       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1213               TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1214       CLI.OutRegs.push_back(VA.getLocReg());
1215     } else if (VA.needsCustom()) {
1216       llvm_unreachable("Mips does not use custom args.");
1217       return false;
1218     } else {
1219       //
1220       // FIXME: This path will currently return false. It was copied
1221       // from the AArch64 port and should be essentially fine for Mips too.
1222       // The work to finish up this path will be done in a follow-on patch.
1223       //
1224       assert(VA.isMemLoc() && "Assuming store on stack.");
1225       // Don't emit stores for undef values.
1226       if (isa<UndefValue>(ArgVal))
1227         continue;
1228 
1229       // Need to store on the stack.
1230       // FIXME: This alignment is incorrect but this path is disabled
1231       // for now (will return false). We need to determine the right alignment
1232       // based on the normal alignment for the underlying machine type.
1233       //
1234       unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1235 
1236       unsigned BEAlign = 0;
1237       if (ArgSize < 8 && !Subtarget->isLittle())
1238         BEAlign = 8 - ArgSize;
1239 
1240       Address Addr;
1241       Addr.setKind(Address::RegBase);
1242       Addr.setReg(Mips::SP);
1243       Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1244 
1245       unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1246       MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1247           MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1248           MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1249       (void)(MMO);
1250       // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1251       return false; // can't store on the stack yet.
1252     }
1253   }
1254 
1255   return true;
1256 }
1257 
1258 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1259                               unsigned NumBytes) {
1260   CallingConv::ID CC = CLI.CallConv;
1261   emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1262   if (RetVT != MVT::isVoid) {
1263     SmallVector<CCValAssign, 16> RVLocs;
1264     MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1265 
1266     CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1267                              CLI.Symbol ? CLI.Symbol->getName().data()
1268                                         : nullptr);
1269 
1270     // Only handle a single return value.
1271     if (RVLocs.size() != 1)
1272       return false;
1273     // Copy all of the result registers out of their specified physreg.
1274     MVT CopyVT = RVLocs[0].getValVT();
1275     // Special handling for extended integers.
1276     if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1277       CopyVT = MVT::i32;
1278 
1279     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1280     if (!ResultReg)
1281       return false;
1282     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1283             TII.get(TargetOpcode::COPY),
1284             ResultReg).addReg(RVLocs[0].getLocReg());
1285     CLI.InRegs.push_back(RVLocs[0].getLocReg());
1286 
1287     CLI.ResultReg = ResultReg;
1288     CLI.NumResultRegs = 1;
1289   }
1290   return true;
1291 }
1292 
1293 bool MipsFastISel::fastLowerArguments() {
1294   LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1295 
1296   if (!FuncInfo.CanLowerReturn) {
1297     LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1298     return false;
1299   }
1300 
1301   const Function *F = FuncInfo.Fn;
1302   if (F->isVarArg()) {
1303     LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1304     return false;
1305   }
1306 
1307   CallingConv::ID CC = F->getCallingConv();
1308   if (CC != CallingConv::C) {
1309     LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1310     return false;
1311   }
1312 
1313   std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1314                                            Mips::A3}};
1315   std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1316   std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1317   auto NextGPR32 = GPR32ArgRegs.begin();
1318   auto NextFGR32 = FGR32ArgRegs.begin();
1319   auto NextAFGR64 = AFGR64ArgRegs.begin();
1320 
1321   struct AllocatedReg {
1322     const TargetRegisterClass *RC;
1323     unsigned Reg;
1324     AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1325         : RC(RC), Reg(Reg) {}
1326   };
1327 
1328   // Only handle simple cases. i.e. All arguments are directly mapped to
1329   // registers of the appropriate type.
1330   SmallVector<AllocatedReg, 4> Allocation;
1331   for (const auto &FormalArg : F->args()) {
1332     if (FormalArg.hasAttribute(Attribute::InReg) ||
1333         FormalArg.hasAttribute(Attribute::StructRet) ||
1334         FormalArg.hasAttribute(Attribute::ByVal)) {
1335       LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1336       return false;
1337     }
1338 
1339     Type *ArgTy = FormalArg.getType();
1340     if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1341       LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1342       return false;
1343     }
1344 
1345     EVT ArgVT = TLI.getValueType(DL, ArgTy);
1346     LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1347                       << ArgVT.getEVTString() << "\n");
1348     if (!ArgVT.isSimple()) {
1349       LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1350       return false;
1351     }
1352 
1353     switch (ArgVT.getSimpleVT().SimpleTy) {
1354     case MVT::i1:
1355     case MVT::i8:
1356     case MVT::i16:
1357       if (!FormalArg.hasAttribute(Attribute::SExt) &&
1358           !FormalArg.hasAttribute(Attribute::ZExt)) {
1359         // It must be any extend, this shouldn't happen for clang-generated IR
1360         // so just fall back on SelectionDAG.
1361         LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1362         return false;
1363       }
1364 
1365       if (NextGPR32 == GPR32ArgRegs.end()) {
1366         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1367         return false;
1368       }
1369 
1370       LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1371       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1372 
1373       // Allocating any GPR32 prohibits further use of floating point arguments.
1374       NextFGR32 = FGR32ArgRegs.end();
1375       NextAFGR64 = AFGR64ArgRegs.end();
1376       break;
1377 
1378     case MVT::i32:
1379       if (FormalArg.hasAttribute(Attribute::ZExt)) {
1380         // The O32 ABI does not permit a zero-extended i32.
1381         LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1382         return false;
1383       }
1384 
1385       if (NextGPR32 == GPR32ArgRegs.end()) {
1386         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1387         return false;
1388       }
1389 
1390       LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1391       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1392 
1393       // Allocating any GPR32 prohibits further use of floating point arguments.
1394       NextFGR32 = FGR32ArgRegs.end();
1395       NextAFGR64 = AFGR64ArgRegs.end();
1396       break;
1397 
1398     case MVT::f32:
1399       if (UnsupportedFPMode) {
1400         LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1401         return false;
1402       }
1403       if (NextFGR32 == FGR32ArgRegs.end()) {
1404         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1405         return false;
1406       }
1407       LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1408       Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1409       // Allocating an FGR32 also allocates the super-register AFGR64, and
1410       // ABI rules require us to skip the corresponding GPR32.
1411       if (NextGPR32 != GPR32ArgRegs.end())
1412         NextGPR32++;
1413       if (NextAFGR64 != AFGR64ArgRegs.end())
1414         NextAFGR64++;
1415       break;
1416 
1417     case MVT::f64:
1418       if (UnsupportedFPMode) {
1419         LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1420         return false;
1421       }
1422       if (NextAFGR64 == AFGR64ArgRegs.end()) {
1423         LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1424         return false;
1425       }
1426       LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1427       Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1428       // Allocating an FGR32 also allocates the super-register AFGR64, and
1429       // ABI rules require us to skip the corresponding GPR32 pair.
1430       if (NextGPR32 != GPR32ArgRegs.end())
1431         NextGPR32++;
1432       if (NextGPR32 != GPR32ArgRegs.end())
1433         NextGPR32++;
1434       if (NextFGR32 != FGR32ArgRegs.end())
1435         NextFGR32++;
1436       break;
1437 
1438     default:
1439       LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1440       return false;
1441     }
1442   }
1443 
1444   for (const auto &FormalArg : F->args()) {
1445     unsigned ArgNo = FormalArg.getArgNo();
1446     unsigned SrcReg = Allocation[ArgNo].Reg;
1447     unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1448     // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1449     // Without this, EmitLiveInCopies may eliminate the livein if its only
1450     // use is a bitcast (which isn't turned into an instruction).
1451     unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1452     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1453             TII.get(TargetOpcode::COPY), ResultReg)
1454         .addReg(DstReg, getKillRegState(true));
1455     updateValueMap(&FormalArg, ResultReg);
1456   }
1457 
1458   // Calculate the size of the incoming arguments area.
1459   // We currently reject all the cases where this would be non-zero.
1460   unsigned IncomingArgSizeInBytes = 0;
1461 
1462   // Account for the reserved argument area on ABI's that have one (O32).
1463   // It seems strange to do this on the caller side but it's necessary in
1464   // SelectionDAG's implementation.
1465   IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1466                                     IncomingArgSizeInBytes);
1467 
1468   MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1469                                                     false);
1470 
1471   return true;
1472 }
1473 
1474 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1475   CallingConv::ID CC = CLI.CallConv;
1476   bool IsTailCall = CLI.IsTailCall;
1477   bool IsVarArg = CLI.IsVarArg;
1478   const Value *Callee = CLI.Callee;
1479   MCSymbol *Symbol = CLI.Symbol;
1480 
1481   // Do not handle FastCC.
1482   if (CC == CallingConv::Fast)
1483     return false;
1484 
1485   // Allow SelectionDAG isel to handle tail calls.
1486   if (IsTailCall)
1487     return false;
1488 
1489   // Let SDISel handle vararg functions.
1490   if (IsVarArg)
1491     return false;
1492 
1493   // FIXME: Only handle *simple* calls for now.
1494   MVT RetVT;
1495   if (CLI.RetTy->isVoidTy())
1496     RetVT = MVT::isVoid;
1497   else if (!isTypeSupported(CLI.RetTy, RetVT))
1498     return false;
1499 
1500   for (auto Flag : CLI.OutFlags)
1501     if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1502       return false;
1503 
1504   // Set up the argument vectors.
1505   SmallVector<MVT, 16> OutVTs;
1506   OutVTs.reserve(CLI.OutVals.size());
1507 
1508   for (auto *Val : CLI.OutVals) {
1509     MVT VT;
1510     if (!isTypeLegal(Val->getType(), VT) &&
1511         !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1512       return false;
1513 
1514     // We don't handle vector parameters yet.
1515     if (VT.isVector() || VT.getSizeInBits() > 64)
1516       return false;
1517 
1518     OutVTs.push_back(VT);
1519   }
1520 
1521   Address Addr;
1522   if (!computeCallAddress(Callee, Addr))
1523     return false;
1524 
1525   // Handle the arguments now that we've gotten them.
1526   unsigned NumBytes;
1527   if (!processCallArgs(CLI, OutVTs, NumBytes))
1528     return false;
1529 
1530   if (!Addr.getGlobalValue())
1531     return false;
1532 
1533   // Issue the call.
1534   unsigned DestAddress;
1535   if (Symbol)
1536     DestAddress = materializeExternalCallSym(Symbol);
1537   else
1538     DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1539   emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1540   MachineInstrBuilder MIB =
1541       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1542               Mips::RA).addReg(Mips::T9);
1543 
1544   // Add implicit physical register uses to the call.
1545   for (auto Reg : CLI.OutRegs)
1546     MIB.addReg(Reg, RegState::Implicit);
1547 
1548   // Add a register mask with the call-preserved registers.
1549   // Proper defs for return values will be added by setPhysRegsDeadExcept().
1550   MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1551 
1552   CLI.Call = MIB;
1553 
1554   // Finish off the call including any return values.
1555   return finishCall(CLI, RetVT, NumBytes);
1556 }
1557 
1558 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1559   switch (II->getIntrinsicID()) {
1560   default:
1561     return false;
1562   case Intrinsic::bswap: {
1563     Type *RetTy = II->getCalledFunction()->getReturnType();
1564 
1565     MVT VT;
1566     if (!isTypeSupported(RetTy, VT))
1567       return false;
1568 
1569     unsigned SrcReg = getRegForValue(II->getOperand(0));
1570     if (SrcReg == 0)
1571       return false;
1572     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1573     if (DestReg == 0)
1574       return false;
1575     if (VT == MVT::i16) {
1576       if (Subtarget->hasMips32r2()) {
1577         emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1578         updateValueMap(II, DestReg);
1579         return true;
1580       } else {
1581         unsigned TempReg[3];
1582         for (int i = 0; i < 3; i++) {
1583           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1584           if (TempReg[i] == 0)
1585             return false;
1586         }
1587         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1588         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1589         emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1590         emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1591         updateValueMap(II, DestReg);
1592         return true;
1593       }
1594     } else if (VT == MVT::i32) {
1595       if (Subtarget->hasMips32r2()) {
1596         unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1597         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1598         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1599         updateValueMap(II, DestReg);
1600         return true;
1601       } else {
1602         unsigned TempReg[8];
1603         for (int i = 0; i < 8; i++) {
1604           TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1605           if (TempReg[i] == 0)
1606             return false;
1607         }
1608 
1609         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1610         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1611         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1612         emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1613 
1614         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1615         emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1616 
1617         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1618         emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1619         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1620         updateValueMap(II, DestReg);
1621         return true;
1622       }
1623     }
1624     return false;
1625   }
1626   case Intrinsic::memcpy:
1627   case Intrinsic::memmove: {
1628     const auto *MTI = cast<MemTransferInst>(II);
1629     // Don't handle volatile.
1630     if (MTI->isVolatile())
1631       return false;
1632     if (!MTI->getLength()->getType()->isIntegerTy(32))
1633       return false;
1634     const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1635     return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1636   }
1637   case Intrinsic::memset: {
1638     const MemSetInst *MSI = cast<MemSetInst>(II);
1639     // Don't handle volatile.
1640     if (MSI->isVolatile())
1641       return false;
1642     if (!MSI->getLength()->getType()->isIntegerTy(32))
1643       return false;
1644     return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1645   }
1646   }
1647   return false;
1648 }
1649 
1650 bool MipsFastISel::selectRet(const Instruction *I) {
1651   const Function &F = *I->getParent()->getParent();
1652   const ReturnInst *Ret = cast<ReturnInst>(I);
1653 
1654   LLVM_DEBUG(dbgs() << "selectRet\n");
1655 
1656   if (!FuncInfo.CanLowerReturn)
1657     return false;
1658 
1659   // Build a list of return value registers.
1660   SmallVector<unsigned, 4> RetRegs;
1661 
1662   if (Ret->getNumOperands() > 0) {
1663     CallingConv::ID CC = F.getCallingConv();
1664 
1665     // Do not handle FastCC.
1666     if (CC == CallingConv::Fast)
1667       return false;
1668 
1669     SmallVector<ISD::OutputArg, 4> Outs;
1670     GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1671 
1672     // Analyze operands of the call, assigning locations to each operand.
1673     SmallVector<CCValAssign, 16> ValLocs;
1674     MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1675                        I->getContext());
1676     CCAssignFn *RetCC = RetCC_Mips;
1677     CCInfo.AnalyzeReturn(Outs, RetCC);
1678 
1679     // Only handle a single return value for now.
1680     if (ValLocs.size() != 1)
1681       return false;
1682 
1683     CCValAssign &VA = ValLocs[0];
1684     const Value *RV = Ret->getOperand(0);
1685 
1686     // Don't bother handling odd stuff for now.
1687     if ((VA.getLocInfo() != CCValAssign::Full) &&
1688         (VA.getLocInfo() != CCValAssign::BCvt))
1689       return false;
1690 
1691     // Only handle register returns for now.
1692     if (!VA.isRegLoc())
1693       return false;
1694 
1695     unsigned Reg = getRegForValue(RV);
1696     if (Reg == 0)
1697       return false;
1698 
1699     unsigned SrcReg = Reg + VA.getValNo();
1700     unsigned DestReg = VA.getLocReg();
1701     // Avoid a cross-class copy. This is very unlikely.
1702     if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1703       return false;
1704 
1705     EVT RVEVT = TLI.getValueType(DL, RV->getType());
1706     if (!RVEVT.isSimple())
1707       return false;
1708 
1709     if (RVEVT.isVector())
1710       return false;
1711 
1712     MVT RVVT = RVEVT.getSimpleVT();
1713     if (RVVT == MVT::f128)
1714       return false;
1715 
1716     // Do not handle FGR64 returns for now.
1717     if (RVVT == MVT::f64 && UnsupportedFPMode) {
1718       LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1719       return false;
1720     }
1721 
1722     MVT DestVT = VA.getValVT();
1723     // Special handling for extended integers.
1724     if (RVVT != DestVT) {
1725       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1726         return false;
1727 
1728       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1729         bool IsZExt = Outs[0].Flags.isZExt();
1730         SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1731         if (SrcReg == 0)
1732           return false;
1733       }
1734     }
1735 
1736     // Make the copy.
1737     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1738             TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1739 
1740     // Add register to return instruction.
1741     RetRegs.push_back(VA.getLocReg());
1742   }
1743   MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1744   for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1745     MIB.addReg(RetRegs[i], RegState::Implicit);
1746   return true;
1747 }
1748 
1749 bool MipsFastISel::selectTrunc(const Instruction *I) {
1750   // The high bits for a type smaller than the register size are assumed to be
1751   // undefined.
1752   Value *Op = I->getOperand(0);
1753 
1754   EVT SrcVT, DestVT;
1755   SrcVT = TLI.getValueType(DL, Op->getType(), true);
1756   DestVT = TLI.getValueType(DL, I->getType(), true);
1757 
1758   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1759     return false;
1760   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1761     return false;
1762 
1763   unsigned SrcReg = getRegForValue(Op);
1764   if (!SrcReg)
1765     return false;
1766 
1767   // Because the high bits are undefined, a truncate doesn't generate
1768   // any code.
1769   updateValueMap(I, SrcReg);
1770   return true;
1771 }
1772 
1773 bool MipsFastISel::selectIntExt(const Instruction *I) {
1774   Type *DestTy = I->getType();
1775   Value *Src = I->getOperand(0);
1776   Type *SrcTy = Src->getType();
1777 
1778   bool isZExt = isa<ZExtInst>(I);
1779   unsigned SrcReg = getRegForValue(Src);
1780   if (!SrcReg)
1781     return false;
1782 
1783   EVT SrcEVT, DestEVT;
1784   SrcEVT = TLI.getValueType(DL, SrcTy, true);
1785   DestEVT = TLI.getValueType(DL, DestTy, true);
1786   if (!SrcEVT.isSimple())
1787     return false;
1788   if (!DestEVT.isSimple())
1789     return false;
1790 
1791   MVT SrcVT = SrcEVT.getSimpleVT();
1792   MVT DestVT = DestEVT.getSimpleVT();
1793   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1794 
1795   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1796     return false;
1797   updateValueMap(I, ResultReg);
1798   return true;
1799 }
1800 
1801 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1802                                    unsigned DestReg) {
1803   unsigned ShiftAmt;
1804   switch (SrcVT.SimpleTy) {
1805   default:
1806     return false;
1807   case MVT::i8:
1808     ShiftAmt = 24;
1809     break;
1810   case MVT::i16:
1811     ShiftAmt = 16;
1812     break;
1813   }
1814   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1815   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1816   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1817   return true;
1818 }
1819 
1820 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1821                                    unsigned DestReg) {
1822   switch (SrcVT.SimpleTy) {
1823   default:
1824     return false;
1825   case MVT::i8:
1826     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1827     break;
1828   case MVT::i16:
1829     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1830     break;
1831   }
1832   return true;
1833 }
1834 
1835 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1836                                unsigned DestReg) {
1837   if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1838     return false;
1839   if (Subtarget->hasMips32r2())
1840     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1841   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1842 }
1843 
1844 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1845                                unsigned DestReg) {
1846   int64_t Imm;
1847 
1848   switch (SrcVT.SimpleTy) {
1849   default:
1850     return false;
1851   case MVT::i1:
1852     Imm = 1;
1853     break;
1854   case MVT::i8:
1855     Imm = 0xff;
1856     break;
1857   case MVT::i16:
1858     Imm = 0xffff;
1859     break;
1860   }
1861 
1862   emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1863   return true;
1864 }
1865 
1866 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1867                               unsigned DestReg, bool IsZExt) {
1868   // FastISel does not have plumbing to deal with extensions where the SrcVT or
1869   // DestVT are odd things, so test to make sure that they are both types we can
1870   // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1871   // bail out to SelectionDAG.
1872   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1873       ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1874     return false;
1875   if (IsZExt)
1876     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1877   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1878 }
1879 
1880 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1881                                   bool isZExt) {
1882   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1883   bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1884   return Success ? DestReg : 0;
1885 }
1886 
1887 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1888   EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1889   if (!DestEVT.isSimple())
1890     return false;
1891 
1892   MVT DestVT = DestEVT.getSimpleVT();
1893   if (DestVT != MVT::i32)
1894     return false;
1895 
1896   unsigned DivOpc;
1897   switch (ISDOpcode) {
1898   default:
1899     return false;
1900   case ISD::SDIV:
1901   case ISD::SREM:
1902     DivOpc = Mips::SDIV;
1903     break;
1904   case ISD::UDIV:
1905   case ISD::UREM:
1906     DivOpc = Mips::UDIV;
1907     break;
1908   }
1909 
1910   unsigned Src0Reg = getRegForValue(I->getOperand(0));
1911   unsigned Src1Reg = getRegForValue(I->getOperand(1));
1912   if (!Src0Reg || !Src1Reg)
1913     return false;
1914 
1915   emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1916   emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1917 
1918   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1919   if (!ResultReg)
1920     return false;
1921 
1922   unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1923                        ? Mips::MFHI
1924                        : Mips::MFLO;
1925   emitInst(MFOpc, ResultReg);
1926 
1927   updateValueMap(I, ResultReg);
1928   return true;
1929 }
1930 
1931 bool MipsFastISel::selectShift(const Instruction *I) {
1932   MVT RetVT;
1933 
1934   if (!isTypeSupported(I->getType(), RetVT))
1935     return false;
1936 
1937   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1938   if (!ResultReg)
1939     return false;
1940 
1941   unsigned Opcode = I->getOpcode();
1942   const Value *Op0 = I->getOperand(0);
1943   unsigned Op0Reg = getRegForValue(Op0);
1944   if (!Op0Reg)
1945     return false;
1946 
1947   // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1948   if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1949     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1950     if (!TempReg)
1951       return false;
1952 
1953     MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1954     bool IsZExt = Opcode == Instruction::LShr;
1955     if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1956       return false;
1957 
1958     Op0Reg = TempReg;
1959   }
1960 
1961   if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1962     uint64_t ShiftVal = C->getZExtValue();
1963 
1964     switch (Opcode) {
1965     default:
1966       llvm_unreachable("Unexpected instruction.");
1967     case Instruction::Shl:
1968       Opcode = Mips::SLL;
1969       break;
1970     case Instruction::AShr:
1971       Opcode = Mips::SRA;
1972       break;
1973     case Instruction::LShr:
1974       Opcode = Mips::SRL;
1975       break;
1976     }
1977 
1978     emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1979     updateValueMap(I, ResultReg);
1980     return true;
1981   }
1982 
1983   unsigned Op1Reg = getRegForValue(I->getOperand(1));
1984   if (!Op1Reg)
1985     return false;
1986 
1987   switch (Opcode) {
1988   default:
1989     llvm_unreachable("Unexpected instruction.");
1990   case Instruction::Shl:
1991     Opcode = Mips::SLLV;
1992     break;
1993   case Instruction::AShr:
1994     Opcode = Mips::SRAV;
1995     break;
1996   case Instruction::LShr:
1997     Opcode = Mips::SRLV;
1998     break;
1999   }
2000 
2001   emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2002   updateValueMap(I, ResultReg);
2003   return true;
2004 }
2005 
2006 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2007   switch (I->getOpcode()) {
2008   default:
2009     break;
2010   case Instruction::Load:
2011     return selectLoad(I);
2012   case Instruction::Store:
2013     return selectStore(I);
2014   case Instruction::SDiv:
2015     if (!selectBinaryOp(I, ISD::SDIV))
2016       return selectDivRem(I, ISD::SDIV);
2017     return true;
2018   case Instruction::UDiv:
2019     if (!selectBinaryOp(I, ISD::UDIV))
2020       return selectDivRem(I, ISD::UDIV);
2021     return true;
2022   case Instruction::SRem:
2023     if (!selectBinaryOp(I, ISD::SREM))
2024       return selectDivRem(I, ISD::SREM);
2025     return true;
2026   case Instruction::URem:
2027     if (!selectBinaryOp(I, ISD::UREM))
2028       return selectDivRem(I, ISD::UREM);
2029     return true;
2030   case Instruction::Shl:
2031   case Instruction::LShr:
2032   case Instruction::AShr:
2033     return selectShift(I);
2034   case Instruction::And:
2035   case Instruction::Or:
2036   case Instruction::Xor:
2037     return selectLogicalOp(I);
2038   case Instruction::Br:
2039     return selectBranch(I);
2040   case Instruction::Ret:
2041     return selectRet(I);
2042   case Instruction::Trunc:
2043     return selectTrunc(I);
2044   case Instruction::ZExt:
2045   case Instruction::SExt:
2046     return selectIntExt(I);
2047   case Instruction::FPTrunc:
2048     return selectFPTrunc(I);
2049   case Instruction::FPExt:
2050     return selectFPExt(I);
2051   case Instruction::FPToSI:
2052     return selectFPToInt(I, /*isSigned*/ true);
2053   case Instruction::FPToUI:
2054     return selectFPToInt(I, /*isSigned*/ false);
2055   case Instruction::ICmp:
2056   case Instruction::FCmp:
2057     return selectCmp(I);
2058   case Instruction::Select:
2059     return selectSelect(I);
2060   }
2061   return false;
2062 }
2063 
2064 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2065                                                            bool IsUnsigned) {
2066   unsigned VReg = getRegForValue(V);
2067   if (VReg == 0)
2068     return 0;
2069   MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2070 
2071   if (VMVT == MVT::i1)
2072     return 0;
2073 
2074   if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2075     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2076     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2077       return 0;
2078     VReg = TempReg;
2079   }
2080   return VReg;
2081 }
2082 
2083 void MipsFastISel::simplifyAddress(Address &Addr) {
2084   if (!isInt<16>(Addr.getOffset())) {
2085     unsigned TempReg =
2086         materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2087     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2088     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2089     Addr.setReg(DestReg);
2090     Addr.setOffset(0);
2091   }
2092 }
2093 
2094 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2095                                        const TargetRegisterClass *RC,
2096                                        unsigned Op0, bool Op0IsKill,
2097                                        unsigned Op1, bool Op1IsKill) {
2098   // We treat the MUL instruction in a special way because it clobbers
2099   // the HI0 & LO0 registers. The TableGen definition of this instruction can
2100   // mark these registers only as implicitly defined. As a result, the
2101   // register allocator runs out of registers when this instruction is
2102   // followed by another instruction that defines the same registers too.
2103   // We can fix this by explicitly marking those registers as dead.
2104   if (MachineInstOpcode == Mips::MUL) {
2105     unsigned ResultReg = createResultReg(RC);
2106     const MCInstrDesc &II = TII.get(MachineInstOpcode);
2107     Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2108     Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2109     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2110       .addReg(Op0, getKillRegState(Op0IsKill))
2111       .addReg(Op1, getKillRegState(Op1IsKill))
2112       .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2113       .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
2114     return ResultReg;
2115   }
2116 
2117   return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2118                                    Op1IsKill);
2119 }
2120 
2121 namespace llvm {
2122 
2123 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
2124                                const TargetLibraryInfo *libInfo) {
2125   return new MipsFastISel(funcInfo, libInfo);
2126 }
2127 
2128 } // end namespace llvm
2129