1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
3 
4 #include "llvm/CodeGen/FunctionLoweringInfo.h"
5 #include "MipsCCState.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/Analysis/TargetLibraryInfo.h"
12 #include "llvm/CodeGen/FastISel.h"
13 #include "llvm/CodeGen/MachineInstrBuilder.h"
14 #include "llvm/IR/GlobalAlias.h"
15 #include "llvm/IR/GlobalVariable.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 
18 using namespace llvm;
19 
20 namespace {
21 
22 class MipsFastISel final : public FastISel {
23 
24   // All possible address modes.
25   class Address {
26   public:
27     typedef enum { RegBase, FrameIndexBase } BaseKind;
28 
29   private:
30     BaseKind Kind;
31     union {
32       unsigned Reg;
33       int FI;
34     } Base;
35 
36     int64_t Offset;
37 
38     const GlobalValue *GV;
39 
40   public:
41     // Innocuous defaults for our address.
42     Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
43     void setKind(BaseKind K) { Kind = K; }
44     BaseKind getKind() const { return Kind; }
45     bool isRegBase() const { return Kind == RegBase; }
46     void setReg(unsigned Reg) {
47       assert(isRegBase() && "Invalid base register access!");
48       Base.Reg = Reg;
49     }
50     unsigned getReg() const {
51       assert(isRegBase() && "Invalid base register access!");
52       return Base.Reg;
53     }
54     void setOffset(int64_t Offset_) { Offset = Offset_; }
55     int64_t getOffset() const { return Offset; }
56     void setGlobalValue(const GlobalValue *G) { GV = G; }
57     const GlobalValue *getGlobalValue() { return GV; }
58   };
59 
60   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
61   /// make the right decision when generating code for different targets.
62   const TargetMachine &TM;
63   const MipsSubtarget *Subtarget;
64   const TargetInstrInfo &TII;
65   const TargetLowering &TLI;
66   MipsFunctionInfo *MFI;
67 
68   // Convenience variables to avoid some queries.
69   LLVMContext *Context;
70 
71   bool fastLowerCall(CallLoweringInfo &CLI) override;
72 
73   bool TargetSupported;
74   bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
75   // floating point but not reject doing fast-isel in other
76   // situations
77 
78 private:
79   // Selection routines.
80   bool selectLoad(const Instruction *I);
81   bool selectStore(const Instruction *I);
82   bool selectBranch(const Instruction *I);
83   bool selectCmp(const Instruction *I);
84   bool selectFPExt(const Instruction *I);
85   bool selectFPTrunc(const Instruction *I);
86   bool selectFPToInt(const Instruction *I, bool IsSigned);
87   bool selectRet(const Instruction *I);
88   bool selectTrunc(const Instruction *I);
89   bool selectIntExt(const Instruction *I);
90 
91   // Utility helper routines.
92   bool isTypeLegal(Type *Ty, MVT &VT);
93   bool isLoadTypeLegal(Type *Ty, MVT &VT);
94   bool computeAddress(const Value *Obj, Address &Addr);
95   bool computeCallAddress(const Value *V, Address &Addr);
96 
97   // Emit helper routines.
98   bool emitCmp(unsigned DestReg, const CmpInst *CI);
99   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
100                 unsigned Alignment = 0);
101   bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
102                  MachineMemOperand *MMO = nullptr);
103   bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
104                  unsigned Alignment = 0);
105   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
106   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
107 
108                   bool IsZExt);
109   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
110 
111   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
112   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
113                        unsigned DestReg);
114   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
115                        unsigned DestReg);
116 
117   unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
118 
119   unsigned materializeFP(const ConstantFP *CFP, MVT VT);
120   unsigned materializeGV(const GlobalValue *GV, MVT VT);
121   unsigned materializeInt(const Constant *C, MVT VT);
122   unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
123 
124   MachineInstrBuilder emitInst(unsigned Opc) {
125     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
126   }
127   MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
128     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
129                    DstReg);
130   }
131   MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
132                                     unsigned MemReg, int64_t MemOffset) {
133     return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
134   }
135   MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
136                                    unsigned MemReg, int64_t MemOffset) {
137     return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
138   }
139   // for some reason, this default is not generated by tablegen
140   // so we explicitly generate it here.
141   //
142   unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
143                              unsigned Op0, bool Op0IsKill, uint64_t imm1,
144                              uint64_t imm2, unsigned Op3, bool Op3IsKill) {
145     return 0;
146   }
147 
148   // Call handling routines.
149 private:
150   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
151   bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
152                        unsigned &NumBytes);
153   bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
154 
155 public:
156   // Backend specific FastISel code.
157   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
158                         const TargetLibraryInfo *libInfo)
159       : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
160         Subtarget(
161             &static_cast<const MipsSubtarget &>(funcInfo.MF->getSubtarget())),
162         TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
163     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
164     Context = &funcInfo.Fn->getContext();
165     TargetSupported =
166         ((TM.getRelocationModel() == Reloc::PIC_) &&
167          ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
168           (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
169     UnsupportedFPMode = Subtarget->isFP64bit();
170   }
171 
172   unsigned fastMaterializeConstant(const Constant *C) override;
173   bool fastSelectInstruction(const Instruction *I) override;
174 
175 #include "MipsGenFastISel.inc"
176 };
177 } // end anonymous namespace.
178 
179 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
180                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
181                     CCState &State) LLVM_ATTRIBUTE_UNUSED;
182 
183 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
184                             CCValAssign::LocInfo LocInfo,
185                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
186   llvm_unreachable("should not be called");
187 }
188 
189 bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
190                      CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
191                      CCState &State) {
192   llvm_unreachable("should not be called");
193 }
194 
195 #include "MipsGenCallingConv.inc"
196 
197 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
198   return CC_MipsO32;
199 }
200 
201 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
202   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
203     return 0;
204   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
205   const ConstantInt *CI = cast<ConstantInt>(C);
206   int64_t Imm;
207   if ((VT != MVT::i1) && CI->isNegative())
208     Imm = CI->getSExtValue();
209   else
210     Imm = CI->getZExtValue();
211   return materialize32BitInt(Imm, RC);
212 }
213 
214 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
215                                            const TargetRegisterClass *RC) {
216   unsigned ResultReg = createResultReg(RC);
217 
218   if (isInt<16>(Imm)) {
219     unsigned Opc = Mips::ADDiu;
220     emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
221     return ResultReg;
222   } else if (isUInt<16>(Imm)) {
223     emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
224     return ResultReg;
225   }
226   unsigned Lo = Imm & 0xFFFF;
227   unsigned Hi = (Imm >> 16) & 0xFFFF;
228   if (Lo) {
229     // Both Lo and Hi have nonzero bits.
230     unsigned TmpReg = createResultReg(RC);
231     emitInst(Mips::LUi, TmpReg).addImm(Hi);
232     emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
233   } else {
234     emitInst(Mips::LUi, ResultReg).addImm(Hi);
235   }
236   return ResultReg;
237 }
238 
239 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
240   if (UnsupportedFPMode)
241     return 0;
242   int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
243   if (VT == MVT::f32) {
244     const TargetRegisterClass *RC = &Mips::FGR32RegClass;
245     unsigned DestReg = createResultReg(RC);
246     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
247     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
248     return DestReg;
249   } else if (VT == MVT::f64) {
250     const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
251     unsigned DestReg = createResultReg(RC);
252     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
253     unsigned TempReg2 =
254         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
255     emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
256     return DestReg;
257   }
258   return 0;
259 }
260 
261 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
262   // For now 32-bit only.
263   if (VT != MVT::i32)
264     return 0;
265   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
266   unsigned DestReg = createResultReg(RC);
267   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
268   bool IsThreadLocal = GVar && GVar->isThreadLocal();
269   // TLS not supported at this time.
270   if (IsThreadLocal)
271     return 0;
272   emitInst(Mips::LW, DestReg)
273       .addReg(MFI->getGlobalBaseReg())
274       .addGlobalAddress(GV, 0, MipsII::MO_GOT);
275   if ((GV->hasInternalLinkage() ||
276        (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
277     unsigned TempReg = createResultReg(RC);
278     emitInst(Mips::ADDiu, TempReg)
279         .addReg(DestReg)
280         .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
281     DestReg = TempReg;
282   }
283   return DestReg;
284 }
285 
286 // Materialize a constant into a register, and return the register
287 // number (or zero if we failed to handle it).
288 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
289   EVT CEVT = TLI.getValueType(C->getType(), true);
290 
291   // Only handle simple types.
292   if (!CEVT.isSimple())
293     return 0;
294   MVT VT = CEVT.getSimpleVT();
295 
296   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
297     return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
298   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
299     return materializeGV(GV, VT);
300   else if (isa<ConstantInt>(C))
301     return materializeInt(C, VT);
302 
303   return 0;
304 }
305 
306 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
307   // This construct looks a big awkward but it is how other ports handle this
308   // and as this function is more fully completed, these cases which
309   // return false will have additional code in them.
310   //
311   if (isa<Instruction>(Obj))
312     return false;
313   else if (isa<ConstantExpr>(Obj))
314     return false;
315   Addr.setReg(getRegForValue(Obj));
316   return Addr.getReg() != 0;
317 }
318 
319 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
320   const GlobalValue *GV = dyn_cast<GlobalValue>(V);
321   if (GV && isa<Function>(GV) && dyn_cast<Function>(GV)->isIntrinsic())
322     return false;
323   if (!GV)
324     return false;
325   if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
326     Addr.setGlobalValue(GV);
327     return true;
328   }
329   return false;
330 }
331 
332 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
333   EVT evt = TLI.getValueType(Ty, true);
334   // Only handle simple types.
335   if (evt == MVT::Other || !evt.isSimple())
336     return false;
337   VT = evt.getSimpleVT();
338 
339   // Handle all legal types, i.e. a register that will directly hold this
340   // value.
341   return TLI.isTypeLegal(VT);
342 }
343 
344 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
345   if (isTypeLegal(Ty, VT))
346     return true;
347   // We will extend this in a later patch:
348   //   If this is a type than can be sign or zero-extended to a basic operation
349   //   go ahead and accept it now.
350   if (VT == MVT::i8 || VT == MVT::i16)
351     return true;
352   return false;
353 }
354 // Because of how EmitCmp is called with fast-isel, you can
355 // end up with redundant "andi" instructions after the sequences emitted below.
356 // We should try and solve this issue in the future.
357 //
358 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
359   const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
360   bool IsUnsigned = CI->isUnsigned();
361   unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
362   if (LeftReg == 0)
363     return false;
364   unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
365   if (RightReg == 0)
366     return false;
367   CmpInst::Predicate P = CI->getPredicate();
368 
369   switch (P) {
370   default:
371     return false;
372   case CmpInst::ICMP_EQ: {
373     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
374     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
375     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
376     break;
377   }
378   case CmpInst::ICMP_NE: {
379     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
380     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
381     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
382     break;
383   }
384   case CmpInst::ICMP_UGT: {
385     emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
386     break;
387   }
388   case CmpInst::ICMP_ULT: {
389     emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
390     break;
391   }
392   case CmpInst::ICMP_UGE: {
393     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
394     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
395     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
396     break;
397   }
398   case CmpInst::ICMP_ULE: {
399     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
400     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
401     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
402     break;
403   }
404   case CmpInst::ICMP_SGT: {
405     emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
406     break;
407   }
408   case CmpInst::ICMP_SLT: {
409     emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
410     break;
411   }
412   case CmpInst::ICMP_SGE: {
413     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
414     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
415     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
416     break;
417   }
418   case CmpInst::ICMP_SLE: {
419     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
420     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
421     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
422     break;
423   }
424   case CmpInst::FCMP_OEQ:
425   case CmpInst::FCMP_UNE:
426   case CmpInst::FCMP_OLT:
427   case CmpInst::FCMP_OLE:
428   case CmpInst::FCMP_OGT:
429   case CmpInst::FCMP_OGE: {
430     if (UnsupportedFPMode)
431       return false;
432     bool IsFloat = Left->getType()->isFloatTy();
433     bool IsDouble = Left->getType()->isDoubleTy();
434     if (!IsFloat && !IsDouble)
435       return false;
436     unsigned Opc, CondMovOpc;
437     switch (P) {
438     case CmpInst::FCMP_OEQ:
439       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
440       CondMovOpc = Mips::MOVT_I;
441       break;
442     case CmpInst::FCMP_UNE:
443       Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
444       CondMovOpc = Mips::MOVF_I;
445       break;
446     case CmpInst::FCMP_OLT:
447       Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
448       CondMovOpc = Mips::MOVT_I;
449       break;
450     case CmpInst::FCMP_OLE:
451       Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
452       CondMovOpc = Mips::MOVT_I;
453       break;
454     case CmpInst::FCMP_OGT:
455       Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
456       CondMovOpc = Mips::MOVF_I;
457       break;
458     case CmpInst::FCMP_OGE:
459       Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
460       CondMovOpc = Mips::MOVF_I;
461       break;
462     default:
463       llvm_unreachable("Only switching of a subset of CCs.");
464     }
465     unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
466     unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
467     emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
468     emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
469     emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
470         Mips::FCC0, RegState::ImplicitDefine);
471     MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
472                                  .addReg(RegWithOne)
473                                  .addReg(Mips::FCC0)
474                                  .addReg(RegWithZero, RegState::Implicit);
475     MI->tieOperands(0, 3);
476     break;
477   }
478   }
479   return true;
480 }
481 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
482                             unsigned Alignment) {
483   //
484   // more cases will be handled here in following patches.
485   //
486   unsigned Opc;
487   switch (VT.SimpleTy) {
488   case MVT::i32: {
489     ResultReg = createResultReg(&Mips::GPR32RegClass);
490     Opc = Mips::LW;
491     break;
492   }
493   case MVT::i16: {
494     ResultReg = createResultReg(&Mips::GPR32RegClass);
495     Opc = Mips::LHu;
496     break;
497   }
498   case MVT::i8: {
499     ResultReg = createResultReg(&Mips::GPR32RegClass);
500     Opc = Mips::LBu;
501     break;
502   }
503   case MVT::f32: {
504     if (UnsupportedFPMode)
505       return false;
506     ResultReg = createResultReg(&Mips::FGR32RegClass);
507     Opc = Mips::LWC1;
508     break;
509   }
510   case MVT::f64: {
511     if (UnsupportedFPMode)
512       return false;
513     ResultReg = createResultReg(&Mips::AFGR64RegClass);
514     Opc = Mips::LDC1;
515     break;
516   }
517   default:
518     return false;
519   }
520   emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
521   return true;
522 }
523 
524 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
525                              unsigned Alignment) {
526   //
527   // more cases will be handled here in following patches.
528   //
529   unsigned Opc;
530   switch (VT.SimpleTy) {
531   case MVT::i8:
532     Opc = Mips::SB;
533     break;
534   case MVT::i16:
535     Opc = Mips::SH;
536     break;
537   case MVT::i32:
538     Opc = Mips::SW;
539     break;
540   case MVT::f32:
541     if (UnsupportedFPMode)
542       return false;
543     Opc = Mips::SWC1;
544     break;
545   case MVT::f64:
546     if (UnsupportedFPMode)
547       return false;
548     Opc = Mips::SDC1;
549     break;
550   default:
551     return false;
552   }
553   emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
554   return true;
555 }
556 
557 bool MipsFastISel::selectLoad(const Instruction *I) {
558   // Atomic loads need special handling.
559   if (cast<LoadInst>(I)->isAtomic())
560     return false;
561 
562   // Verify we have a legal type before going any further.
563   MVT VT;
564   if (!isLoadTypeLegal(I->getType(), VT))
565     return false;
566 
567   // See if we can handle this address.
568   Address Addr;
569   if (!computeAddress(I->getOperand(0), Addr))
570     return false;
571 
572   unsigned ResultReg;
573   if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
574     return false;
575   updateValueMap(I, ResultReg);
576   return true;
577 }
578 
579 bool MipsFastISel::selectStore(const Instruction *I) {
580   Value *Op0 = I->getOperand(0);
581   unsigned SrcReg = 0;
582 
583   // Atomic stores need special handling.
584   if (cast<StoreInst>(I)->isAtomic())
585     return false;
586 
587   // Verify we have a legal type before going any further.
588   MVT VT;
589   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
590     return false;
591 
592   // Get the value to be stored into a register.
593   SrcReg = getRegForValue(Op0);
594   if (SrcReg == 0)
595     return false;
596 
597   // See if we can handle this address.
598   Address Addr;
599   if (!computeAddress(I->getOperand(1), Addr))
600     return false;
601 
602   if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
603     return false;
604   return true;
605 }
606 
607 //
608 // This can cause a redundant sltiu to be generated.
609 // FIXME: try and eliminate this in a future patch.
610 //
611 bool MipsFastISel::selectBranch(const Instruction *I) {
612   const BranchInst *BI = cast<BranchInst>(I);
613   MachineBasicBlock *BrBB = FuncInfo.MBB;
614   //
615   // TBB is the basic block for the case where the comparison is true.
616   // FBB is the basic block for the case where the comparison is false.
617   // if (cond) goto TBB
618   // goto FBB
619   // TBB:
620   //
621   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
622   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
623   BI->getCondition();
624   // For now, just try the simplest case where it's fed by a compare.
625   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
626     unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
627     if (!emitCmp(CondReg, CI))
628       return false;
629     BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
630         .addReg(CondReg)
631         .addMBB(TBB);
632     fastEmitBranch(FBB, DbgLoc);
633     FuncInfo.MBB->addSuccessor(TBB);
634     return true;
635   }
636   return false;
637 }
638 
639 bool MipsFastISel::selectCmp(const Instruction *I) {
640   const CmpInst *CI = cast<CmpInst>(I);
641   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
642   if (!emitCmp(ResultReg, CI))
643     return false;
644   updateValueMap(I, ResultReg);
645   return true;
646 }
647 
648 // Attempt to fast-select a floating-point extend instruction.
649 bool MipsFastISel::selectFPExt(const Instruction *I) {
650   if (UnsupportedFPMode)
651     return false;
652   Value *Src = I->getOperand(0);
653   EVT SrcVT = TLI.getValueType(Src->getType(), true);
654   EVT DestVT = TLI.getValueType(I->getType(), true);
655 
656   if (SrcVT != MVT::f32 || DestVT != MVT::f64)
657     return false;
658 
659   unsigned SrcReg =
660       getRegForValue(Src); // his must be a 32 bit floating point register class
661                            // maybe we should handle this differently
662   if (!SrcReg)
663     return false;
664 
665   unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
666   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
667   updateValueMap(I, DestReg);
668   return true;
669 }
670 
671 // Attempt to fast-select a floating-point truncate instruction.
672 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
673   if (UnsupportedFPMode)
674     return false;
675   Value *Src = I->getOperand(0);
676   EVT SrcVT = TLI.getValueType(Src->getType(), true);
677   EVT DestVT = TLI.getValueType(I->getType(), true);
678 
679   if (SrcVT != MVT::f64 || DestVT != MVT::f32)
680     return false;
681 
682   unsigned SrcReg = getRegForValue(Src);
683   if (!SrcReg)
684     return false;
685 
686   unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
687   if (!DestReg)
688     return false;
689 
690   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
691   updateValueMap(I, DestReg);
692   return true;
693 }
694 
695 // Attempt to fast-select a floating-point-to-integer conversion.
696 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
697   if (UnsupportedFPMode)
698     return false;
699   MVT DstVT, SrcVT;
700   if (!IsSigned)
701     return false; // We don't handle this case yet. There is no native
702                   // instruction for this but it can be synthesized.
703   Type *DstTy = I->getType();
704   if (!isTypeLegal(DstTy, DstVT))
705     return false;
706 
707   if (DstVT != MVT::i32)
708     return false;
709 
710   Value *Src = I->getOperand(0);
711   Type *SrcTy = Src->getType();
712   if (!isTypeLegal(SrcTy, SrcVT))
713     return false;
714 
715   if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
716     return false;
717 
718   unsigned SrcReg = getRegForValue(Src);
719   if (SrcReg == 0)
720     return false;
721 
722   // Determine the opcode for the conversion, which takes place
723   // entirely within FPRs.
724   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
725   unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
726   unsigned Opc;
727 
728   if (SrcVT == MVT::f32)
729     Opc = Mips::TRUNC_W_S;
730   else
731     Opc = Mips::TRUNC_W_D32;
732 
733   // Generate the convert.
734   emitInst(Opc, TempReg).addReg(SrcReg);
735 
736   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
737 
738   updateValueMap(I, DestReg);
739   return true;
740 }
741 //
742 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
743                                    SmallVectorImpl<MVT> &OutVTs,
744                                    unsigned &NumBytes) {
745   CallingConv::ID CC = CLI.CallConv;
746   SmallVector<CCValAssign, 16> ArgLocs;
747   CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
748   CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
749   // Get a count of how many bytes are to be pushed on the stack.
750   NumBytes = CCInfo.getNextStackOffset();
751   // This is the minimum argument area used for A0-A3.
752   if (NumBytes < 16)
753     NumBytes = 16;
754 
755   emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
756   // Process the args.
757   MVT firstMVT;
758   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
759     CCValAssign &VA = ArgLocs[i];
760     const Value *ArgVal = CLI.OutVals[VA.getValNo()];
761     MVT ArgVT = OutVTs[VA.getValNo()];
762 
763     if (i == 0) {
764       firstMVT = ArgVT;
765       if (ArgVT == MVT::f32) {
766         VA.convertToReg(Mips::F12);
767       } else if (ArgVT == MVT::f64) {
768         VA.convertToReg(Mips::D6);
769       }
770     } else if (i == 1) {
771       if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
772         if (ArgVT == MVT::f32) {
773           VA.convertToReg(Mips::F14);
774         } else if (ArgVT == MVT::f64) {
775           VA.convertToReg(Mips::D7);
776         }
777       }
778     }
779     if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) {
780       switch (VA.getLocMemOffset()) {
781       case 0:
782         VA.convertToReg(Mips::A0);
783         break;
784       case 4:
785         VA.convertToReg(Mips::A1);
786         break;
787       case 8:
788         VA.convertToReg(Mips::A2);
789         break;
790       case 12:
791         VA.convertToReg(Mips::A3);
792         break;
793       default:
794         break;
795       }
796     }
797     unsigned ArgReg = getRegForValue(ArgVal);
798     if (!ArgReg)
799       return false;
800 
801     // Handle arg promotion: SExt, ZExt, AExt.
802     switch (VA.getLocInfo()) {
803     case CCValAssign::Full:
804       break;
805     case CCValAssign::AExt:
806     case CCValAssign::SExt: {
807       MVT DestVT = VA.getLocVT();
808       MVT SrcVT = ArgVT;
809       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
810       if (!ArgReg)
811         return false;
812       break;
813     }
814     case CCValAssign::ZExt: {
815       MVT DestVT = VA.getLocVT();
816       MVT SrcVT = ArgVT;
817       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
818       if (!ArgReg)
819         return false;
820       break;
821     }
822     default:
823       llvm_unreachable("Unknown arg promotion!");
824     }
825 
826     // Now copy/store arg to correct locations.
827     if (VA.isRegLoc() && !VA.needsCustom()) {
828       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
829               TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
830       CLI.OutRegs.push_back(VA.getLocReg());
831     } else if (VA.needsCustom()) {
832       llvm_unreachable("Mips does not use custom args.");
833       return false;
834     } else {
835       //
836       // FIXME: This path will currently return false. It was copied
837       // from the AArch64 port and should be essentially fine for Mips too.
838       // The work to finish up this path will be done in a follow-on patch.
839       //
840       assert(VA.isMemLoc() && "Assuming store on stack.");
841       // Don't emit stores for undef values.
842       if (isa<UndefValue>(ArgVal))
843         continue;
844 
845       // Need to store on the stack.
846       // FIXME: This alignment is incorrect but this path is disabled
847       // for now (will return false). We need to determine the right alignment
848       // based on the normal alignment for the underlying machine type.
849       //
850       unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
851 
852       unsigned BEAlign = 0;
853       if (ArgSize < 8 && !Subtarget->isLittle())
854         BEAlign = 8 - ArgSize;
855 
856       Address Addr;
857       Addr.setKind(Address::RegBase);
858       Addr.setReg(Mips::SP);
859       Addr.setOffset(VA.getLocMemOffset() + BEAlign);
860 
861       unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
862       MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
863           MachinePointerInfo::getStack(Addr.getOffset()),
864           MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
865       (void)(MMO);
866       // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
867       return false; // can't store on the stack yet.
868     }
869   }
870 
871   return true;
872 }
873 
874 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
875                               unsigned NumBytes) {
876   CallingConv::ID CC = CLI.CallConv;
877   emitInst(Mips::ADJCALLSTACKUP).addImm(16);
878   if (RetVT != MVT::isVoid) {
879     SmallVector<CCValAssign, 16> RVLocs;
880     CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
881     CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
882 
883     // Only handle a single return value.
884     if (RVLocs.size() != 1)
885       return false;
886     // Copy all of the result registers out of their specified physreg.
887     MVT CopyVT = RVLocs[0].getValVT();
888     // Special handling for extended integers.
889     if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
890       CopyVT = MVT::i32;
891 
892     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
893     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
894             TII.get(TargetOpcode::COPY),
895             ResultReg).addReg(RVLocs[0].getLocReg());
896     CLI.InRegs.push_back(RVLocs[0].getLocReg());
897 
898     CLI.ResultReg = ResultReg;
899     CLI.NumResultRegs = 1;
900   }
901   return true;
902 }
903 
904 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
905   CallingConv::ID CC = CLI.CallConv;
906   bool IsTailCall = CLI.IsTailCall;
907   bool IsVarArg = CLI.IsVarArg;
908   const Value *Callee = CLI.Callee;
909   // const char *SymName = CLI.SymName;
910 
911   // Allow SelectionDAG isel to handle tail calls.
912   if (IsTailCall)
913     return false;
914 
915   // Let SDISel handle vararg functions.
916   if (IsVarArg)
917     return false;
918 
919   // FIXME: Only handle *simple* calls for now.
920   MVT RetVT;
921   if (CLI.RetTy->isVoidTy())
922     RetVT = MVT::isVoid;
923   else if (!isTypeLegal(CLI.RetTy, RetVT))
924     return false;
925 
926   for (auto Flag : CLI.OutFlags)
927     if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
928       return false;
929 
930   // Set up the argument vectors.
931   SmallVector<MVT, 16> OutVTs;
932   OutVTs.reserve(CLI.OutVals.size());
933 
934   for (auto *Val : CLI.OutVals) {
935     MVT VT;
936     if (!isTypeLegal(Val->getType(), VT) &&
937         !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
938       return false;
939 
940     // We don't handle vector parameters yet.
941     if (VT.isVector() || VT.getSizeInBits() > 64)
942       return false;
943 
944     OutVTs.push_back(VT);
945   }
946 
947   Address Addr;
948   if (!computeCallAddress(Callee, Addr))
949     return false;
950 
951   // Handle the arguments now that we've gotten them.
952   unsigned NumBytes;
953   if (!processCallArgs(CLI, OutVTs, NumBytes))
954     return false;
955 
956   // Issue the call.
957   unsigned DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
958   emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
959   MachineInstrBuilder MIB =
960       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
961               Mips::RA).addReg(Mips::T9);
962 
963   // Add implicit physical register uses to the call.
964   for (auto Reg : CLI.OutRegs)
965     MIB.addReg(Reg, RegState::Implicit);
966 
967   // Add a register mask with the call-preserved registers.
968   // Proper defs for return values will be added by setPhysRegsDeadExcept().
969   MIB.addRegMask(TRI.getCallPreservedMask(CC));
970 
971   CLI.Call = MIB;
972 
973   // Add implicit physical register uses to the call.
974   for (auto Reg : CLI.OutRegs)
975     MIB.addReg(Reg, RegState::Implicit);
976 
977   // Add a register mask with the call-preserved registers.  Proper
978   // defs for return values will be added by setPhysRegsDeadExcept().
979   MIB.addRegMask(TRI.getCallPreservedMask(CC));
980 
981   CLI.Call = MIB;
982   // Finish off the call including any return values.
983   return finishCall(CLI, RetVT, NumBytes);
984 }
985 
986 bool MipsFastISel::selectRet(const Instruction *I) {
987   const ReturnInst *Ret = cast<ReturnInst>(I);
988 
989   if (!FuncInfo.CanLowerReturn)
990     return false;
991   if (Ret->getNumOperands() > 0) {
992     return false;
993   }
994   emitInst(Mips::RetRA);
995   return true;
996 }
997 
998 bool MipsFastISel::selectTrunc(const Instruction *I) {
999   // The high bits for a type smaller than the register size are assumed to be
1000   // undefined.
1001   Value *Op = I->getOperand(0);
1002 
1003   EVT SrcVT, DestVT;
1004   SrcVT = TLI.getValueType(Op->getType(), true);
1005   DestVT = TLI.getValueType(I->getType(), true);
1006 
1007   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1008     return false;
1009   if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1010     return false;
1011 
1012   unsigned SrcReg = getRegForValue(Op);
1013   if (!SrcReg)
1014     return false;
1015 
1016   // Because the high bits are undefined, a truncate doesn't generate
1017   // any code.
1018   updateValueMap(I, SrcReg);
1019   return true;
1020 }
1021 bool MipsFastISel::selectIntExt(const Instruction *I) {
1022   Type *DestTy = I->getType();
1023   Value *Src = I->getOperand(0);
1024   Type *SrcTy = Src->getType();
1025 
1026   bool isZExt = isa<ZExtInst>(I);
1027   unsigned SrcReg = getRegForValue(Src);
1028   if (!SrcReg)
1029     return false;
1030 
1031   EVT SrcEVT, DestEVT;
1032   SrcEVT = TLI.getValueType(SrcTy, true);
1033   DestEVT = TLI.getValueType(DestTy, true);
1034   if (!SrcEVT.isSimple())
1035     return false;
1036   if (!DestEVT.isSimple())
1037     return false;
1038 
1039   MVT SrcVT = SrcEVT.getSimpleVT();
1040   MVT DestVT = DestEVT.getSimpleVT();
1041   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1042 
1043   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1044     return false;
1045   updateValueMap(I, ResultReg);
1046   return true;
1047 }
1048 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1049                                    unsigned DestReg) {
1050   unsigned ShiftAmt;
1051   switch (SrcVT.SimpleTy) {
1052   default:
1053     return false;
1054   case MVT::i8:
1055     ShiftAmt = 24;
1056     break;
1057   case MVT::i16:
1058     ShiftAmt = 16;
1059     break;
1060   }
1061   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1062   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1063   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1064   return true;
1065 }
1066 
1067 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1068                                    unsigned DestReg) {
1069   switch (SrcVT.SimpleTy) {
1070   default:
1071     return false;
1072   case MVT::i8:
1073     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1074     break;
1075   case MVT::i16:
1076     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1077     break;
1078   }
1079   return true;
1080 }
1081 
1082 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1083                                unsigned DestReg) {
1084   if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1085     return false;
1086   if (Subtarget->hasMips32r2())
1087     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1088   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1089 }
1090 
1091 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1092                                unsigned DestReg) {
1093   switch (SrcVT.SimpleTy) {
1094   default:
1095     return false;
1096   case MVT::i1:
1097     emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1098     break;
1099   case MVT::i8:
1100     emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1101     break;
1102   case MVT::i16:
1103     emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1104     break;
1105   }
1106   return true;
1107 }
1108 
1109 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1110                               unsigned DestReg, bool IsZExt) {
1111   if (IsZExt)
1112     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1113   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1114 }
1115 
1116 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1117                                   bool isZExt) {
1118   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1119   return emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1120 }
1121 
1122 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1123   if (!TargetSupported)
1124     return false;
1125   switch (I->getOpcode()) {
1126   default:
1127     break;
1128   case Instruction::Load:
1129     return selectLoad(I);
1130   case Instruction::Store:
1131     return selectStore(I);
1132   case Instruction::Br:
1133     return selectBranch(I);
1134   case Instruction::Ret:
1135     return selectRet(I);
1136   case Instruction::Trunc:
1137     return selectTrunc(I);
1138   case Instruction::ZExt:
1139   case Instruction::SExt:
1140     return selectIntExt(I);
1141   case Instruction::FPTrunc:
1142     return selectFPTrunc(I);
1143   case Instruction::FPExt:
1144     return selectFPExt(I);
1145   case Instruction::FPToSI:
1146     return selectFPToInt(I, /*isSigned*/ true);
1147   case Instruction::FPToUI:
1148     return selectFPToInt(I, /*isSigned*/ false);
1149   case Instruction::ICmp:
1150   case Instruction::FCmp:
1151     return selectCmp(I);
1152   }
1153   return false;
1154 }
1155 
1156 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1157                                                            bool IsUnsigned) {
1158   unsigned VReg = getRegForValue(V);
1159   if (VReg == 0)
1160     return 0;
1161   MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
1162   if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1163     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1164     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1165       return 0;
1166     VReg = TempReg;
1167   }
1168   return VReg;
1169 }
1170 
1171 namespace llvm {
1172 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1173                                const TargetLibraryInfo *libInfo) {
1174   return new MipsFastISel(funcInfo, libInfo);
1175 }
1176 }
1177