1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
3 
4 #include "llvm/CodeGen/FunctionLoweringInfo.h"
5 #include "llvm/CodeGen/FastISel.h"
6 #include "llvm/CodeGen/MachineInstrBuilder.h"
7 #include "llvm/IR/GlobalAlias.h"
8 #include "llvm/IR/GlobalVariable.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/TargetLibraryInfo.h"
11 #include "MipsRegisterInfo.h"
12 #include "MipsISelLowering.h"
13 #include "MipsMachineFunction.h"
14 #include "MipsSubtarget.h"
15 #include "MipsTargetMachine.h"
16 
17 using namespace llvm;
18 
19 namespace {
20 
21 // All possible address modes.
22 typedef struct Address {
23   enum { RegBase, FrameIndexBase } BaseType;
24 
25   union {
26     unsigned Reg;
27     int FI;
28   } Base;
29 
30   int64_t Offset;
31 
32   // Innocuous defaults for our address.
33   Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
34 } Address;
35 
36 class MipsFastISel final : public FastISel {
37 
38   /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
39   /// make the right decision when generating code for different targets.
40   Module &M;
41   const TargetMachine &TM;
42   const TargetInstrInfo &TII;
43   const TargetLowering &TLI;
44   const MipsSubtarget *Subtarget;
45   MipsFunctionInfo *MFI;
46 
47   // Convenience variables to avoid some queries.
48   LLVMContext *Context;
49 
50   bool TargetSupported;
51 
52 public:
53   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
54                         const TargetLibraryInfo *libInfo)
55       : FastISel(funcInfo, libInfo),
56         M(const_cast<Module &>(*funcInfo.Fn->getParent())),
57         TM(funcInfo.MF->getTarget()),
58         TII(*TM.getSubtargetImpl()->getInstrInfo()),
59         TLI(*TM.getSubtargetImpl()->getTargetLowering()),
60         Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
61     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
62     Context = &funcInfo.Fn->getContext();
63     TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
64                        (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
65   }
66 
67   bool TargetSelectInstruction(const Instruction *I) override;
68   unsigned TargetMaterializeConstant(const Constant *C) override;
69 
70   bool ComputeAddress(const Value *Obj, Address &Addr);
71 
72 private:
73   bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
74                 unsigned Alignment = 0);
75   bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
76                  unsigned Alignment = 0);
77   bool SelectLoad(const Instruction *I);
78   bool SelectRet(const Instruction *I);
79   bool SelectStore(const Instruction *I);
80 
81   bool isTypeLegal(Type *Ty, MVT &VT);
82   bool isLoadTypeLegal(Type *Ty, MVT &VT);
83 
84   unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
85   unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
86   unsigned MaterializeInt(const Constant *C, MVT VT);
87   unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
88 
89   // for some reason, this default is not generated by tablegen
90   // so we explicitly generate it here.
91   //
92   unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
93                              unsigned Op0, bool Op0IsKill, uint64_t imm1,
94                              uint64_t imm2, unsigned Op3, bool Op3IsKill) {
95     return 0;
96   }
97 
98   MachineInstrBuilder EmitInst(unsigned Opc) {
99     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
100   }
101 
102   MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
103     return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
104                    DstReg);
105   }
106 
107   MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
108                                     unsigned MemReg, int64_t MemOffset) {
109     return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
110   }
111 
112   MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
113                                    unsigned MemReg, int64_t MemOffset) {
114     return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
115   }
116 
117 #include "MipsGenFastISel.inc"
118 };
119 
120 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
121   EVT evt = TLI.getValueType(Ty, true);
122   // Only handle simple types.
123   if (evt == MVT::Other || !evt.isSimple())
124     return false;
125   VT = evt.getSimpleVT();
126 
127   // Handle all legal types, i.e. a register that will directly hold this
128   // value.
129   return TLI.isTypeLegal(VT);
130 }
131 
132 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
133   if (isTypeLegal(Ty, VT))
134     return true;
135   // We will extend this in a later patch:
136   //   If this is a type than can be sign or zero-extended to a basic operation
137   //   go ahead and accept it now.
138   if (VT == MVT::i8 || VT == MVT::i16)
139     return true;
140   return false;
141 }
142 
143 bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
144   // This construct looks a big awkward but it is how other ports handle this
145   // and as this function is more fully completed, these cases which
146   // return false will have additional code in them.
147   //
148   if (isa<Instruction>(Obj))
149     return false;
150   else if (isa<ConstantExpr>(Obj))
151     return false;
152   Addr.Base.Reg = getRegForValue(Obj);
153   return Addr.Base.Reg != 0;
154 }
155 
156 bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
157                             unsigned Alignment) {
158   //
159   // more cases will be handled here in following patches.
160   //
161   unsigned Opc;
162   switch (VT.SimpleTy) {
163   case MVT::i32: {
164     ResultReg = createResultReg(&Mips::GPR32RegClass);
165     Opc = Mips::LW;
166     break;
167   }
168   case MVT::i16: {
169     ResultReg = createResultReg(&Mips::GPR32RegClass);
170     Opc = Mips::LHu;
171     break;
172   }
173   case MVT::i8: {
174     ResultReg = createResultReg(&Mips::GPR32RegClass);
175     Opc = Mips::LBu;
176     break;
177   }
178   case MVT::f32: {
179     ResultReg = createResultReg(&Mips::FGR32RegClass);
180     Opc = Mips::LWC1;
181     break;
182   }
183   case MVT::f64: {
184     ResultReg = createResultReg(&Mips::AFGR64RegClass);
185     Opc = Mips::LDC1;
186     break;
187   }
188   default:
189     return false;
190   }
191   EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
192   return true;
193 }
194 
195 // Materialize a constant into a register, and return the register
196 // number (or zero if we failed to handle it).
197 unsigned MipsFastISel::TargetMaterializeConstant(const Constant *C) {
198   EVT CEVT = TLI.getValueType(C->getType(), true);
199 
200   // Only handle simple types.
201   if (!CEVT.isSimple())
202     return 0;
203   MVT VT = CEVT.getSimpleVT();
204 
205   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
206     return MaterializeFP(CFP, VT);
207   else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
208     return MaterializeGV(GV, VT);
209   else if (isa<ConstantInt>(C))
210     return MaterializeInt(C, VT);
211 
212   return 0;
213 }
214 
215 bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
216                              unsigned Alignment) {
217   //
218   // more cases will be handled here in following patches.
219   //
220   unsigned Opc;
221   switch (VT.SimpleTy) {
222   case MVT::i8:
223     Opc = Mips::SB;
224     break;
225   case MVT::i16:
226     Opc = Mips::SH;
227     break;
228   case MVT::i32:
229     Opc = Mips::SW;
230     break;
231   case MVT::f32:
232     Opc = Mips::SWC1;
233     break;
234   case MVT::f64:
235     Opc = Mips::SDC1;
236     break;
237   default:
238     return false;
239   }
240   EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
241   return true;
242 }
243 
244 bool MipsFastISel::SelectLoad(const Instruction *I) {
245   // Atomic loads need special handling.
246   if (cast<LoadInst>(I)->isAtomic())
247     return false;
248 
249   // Verify we have a legal type before going any further.
250   MVT VT;
251   if (!isLoadTypeLegal(I->getType(), VT))
252     return false;
253 
254   // See if we can handle this address.
255   Address Addr;
256   if (!ComputeAddress(I->getOperand(0), Addr))
257     return false;
258 
259   unsigned ResultReg;
260   if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
261     return false;
262   UpdateValueMap(I, ResultReg);
263   return true;
264 }
265 
266 bool MipsFastISel::SelectStore(const Instruction *I) {
267   Value *Op0 = I->getOperand(0);
268   unsigned SrcReg = 0;
269 
270   // Atomic stores need special handling.
271   if (cast<StoreInst>(I)->isAtomic())
272     return false;
273 
274   // Verify we have a legal type before going any further.
275   MVT VT;
276   if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
277     return false;
278 
279   // Get the value to be stored into a register.
280   SrcReg = getRegForValue(Op0);
281   if (SrcReg == 0)
282     return false;
283 
284   // See if we can handle this address.
285   Address Addr;
286   if (!ComputeAddress(I->getOperand(1), Addr))
287     return false;
288 
289   if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
290     return false;
291   return true;
292 }
293 
294 bool MipsFastISel::SelectRet(const Instruction *I) {
295   const ReturnInst *Ret = cast<ReturnInst>(I);
296 
297   if (!FuncInfo.CanLowerReturn)
298     return false;
299   if (Ret->getNumOperands() > 0) {
300     return false;
301   }
302   EmitInst(Mips::RetRA);
303   return true;
304 }
305 
306 bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
307   if (!TargetSupported)
308     return false;
309   switch (I->getOpcode()) {
310   default:
311     break;
312   case Instruction::Load:
313     return SelectLoad(I);
314   case Instruction::Store:
315     return SelectStore(I);
316   case Instruction::Ret:
317     return SelectRet(I);
318   }
319   return false;
320 }
321 }
322 
323 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
324   int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
325   if (VT == MVT::f32) {
326     const TargetRegisterClass *RC = &Mips::FGR32RegClass;
327     unsigned DestReg = createResultReg(RC);
328     unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
329     EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
330     return DestReg;
331   } else if (VT == MVT::f64) {
332     const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
333     unsigned DestReg = createResultReg(RC);
334     unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
335     unsigned TempReg2 =
336         Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
337     EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
338     return DestReg;
339   }
340   return 0;
341 }
342 
343 unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
344   // For now 32-bit only.
345   if (VT != MVT::i32)
346     return 0;
347   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
348   unsigned DestReg = createResultReg(RC);
349   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
350   bool IsThreadLocal = GVar && GVar->isThreadLocal();
351   // TLS not supported at this time.
352   if (IsThreadLocal)
353     return 0;
354   EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
355       GV, 0, MipsII::MO_GOT);
356   if ((GV->hasInternalLinkage() ||
357        (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
358     unsigned TempReg = createResultReg(RC);
359     EmitInst(Mips::ADDiu, TempReg).addReg(DestReg).addGlobalAddress(
360         GV, 0, MipsII::MO_ABS_LO);
361     DestReg = TempReg;
362   }
363   return DestReg;
364 }
365 
366 unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
367   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
368     return 0;
369   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
370   const ConstantInt *CI = cast<ConstantInt>(C);
371   int64_t Imm;
372   if ((VT != MVT::i1) && CI->isNegative())
373     Imm = CI->getSExtValue();
374   else
375     Imm = CI->getZExtValue();
376   return Materialize32BitInt(Imm, RC);
377 }
378 
379 unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
380                                            const TargetRegisterClass *RC) {
381   unsigned ResultReg = createResultReg(RC);
382 
383   if (isInt<16>(Imm)) {
384     unsigned Opc = Mips::ADDiu;
385     EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
386     return ResultReg;
387   } else if (isUInt<16>(Imm)) {
388     EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
389     return ResultReg;
390   }
391   unsigned Lo = Imm & 0xFFFF;
392   unsigned Hi = (Imm >> 16) & 0xFFFF;
393   if (Lo) {
394     // Both Lo and Hi have nonzero bits.
395     unsigned TmpReg = createResultReg(RC);
396     EmitInst(Mips::LUi, TmpReg).addImm(Hi);
397     EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
398   } else {
399     EmitInst(Mips::LUi, ResultReg).addImm(Hi);
400   }
401   return ResultReg;
402 }
403 
404 namespace llvm {
405 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
406                                const TargetLibraryInfo *libInfo) {
407   return new MipsFastISel(funcInfo, libInfo);
408 }
409 }
410