1//===- MipsCallingConv.td - Calling Conventions for Mips ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This describes the calling conventions for Mips architecture. 10//===----------------------------------------------------------------------===// 11 12/// CCIfSubtarget - Match if the current subtarget has a feature F. 13class CCIfSubtarget<string F, CCAction A>: 14 CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>; 15 16//===----------------------------------------------------------------------===// 17// Mips O32 Calling Convention 18//===----------------------------------------------------------------------===// 19 20// Only the return rules are defined here for O32. The rules for argument 21// passing are defined in MipsISelLowering.cpp. 22def RetCC_MipsO32 : CallingConv<[ 23 // i32 are returned in registers V0, V1, A0, A1 24 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>, 25 26 // f32 are returned in registers F0, F2 27 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 28 29 // f64 are returned in register D0, D1 30 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>> 31]>; 32 33//===----------------------------------------------------------------------===// 34// Mips N32/64 Calling Convention 35//===----------------------------------------------------------------------===// 36 37def CC_MipsN : CallingConv<[ 38 // Handles byval parameters. 39 CCIfByVal<CCCustom<"CC_Mips64Byval">>, 40 41 // Promote i8/i16/i32 arguments to i64. 42 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 43 44 // Integer arguments are passed in integer registers. 45 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64, 46 T0_64, T1_64, T2_64, T3_64], 47 [D12_64, D13_64, D14_64, D15_64, 48 D16_64, D17_64, D18_64, D19_64]>>, 49 50 // f32 arguments are passed in single precision FP registers. 51 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15, 52 F16, F17, F18, F19], 53 [A0_64, A1_64, A2_64, A3_64, 54 T0_64, T1_64, T2_64, T3_64]>>, 55 56 // f64 arguments are passed in double precision FP registers. 57 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64, 58 D16_64, D17_64, D18_64, D19_64], 59 [A0_64, A1_64, A2_64, A3_64, 60 T0_64, T1_64, T2_64, T3_64]>>, 61 62 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 63 CCIfType<[i64, f64], CCAssignToStack<8, 8>>, 64 CCIfType<[f32], CCAssignToStack<4, 8>> 65]>; 66 67// N32/64 variable arguments. 68// All arguments are passed in integer registers. 69def CC_MipsN_VarArg : CallingConv<[ 70 // Handles byval parameters. 71 CCIfByVal<CCCustom<"CC_Mips64Byval">>, 72 73 // Promote i8/i16/i32 arguments to i64. 74 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 75 76 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, 77 T0_64, T1_64, T2_64, T3_64]>>, 78 79 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 80 81 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 82 CCIfType<[i64, f64], CCAssignToStack<8, 8>>, 83 CCIfType<[f32], CCAssignToStack<4, 8>> 84]>; 85 86def RetCC_MipsN : CallingConv<[ 87 // FIXME: Handle complex and float double return values. 88 89 // i32 are returned in registers V0, V1 90 CCIfType<[i32], CCAssignToReg<[V0, V1]>>, 91 92 // i64 are returned in registers V0_64, V1_64 93 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>, 94 95 // f32 are returned in registers F0, F2 96 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 97 98 // f64 are returned in registers D0, D2 99 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>> 100]>; 101 102//===----------------------------------------------------------------------===// 103// Mips EABI Calling Convention 104//===----------------------------------------------------------------------===// 105 106def CC_MipsEABI : CallingConv<[ 107 // Promote i8/i16 arguments to i32. 108 CCIfType<[i8, i16], CCPromoteToType<i32>>, 109 110 // Integer arguments are passed in integer registers. 111 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 112 113 // Single fp arguments are passed in pairs within 32-bit mode 114 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()", 115 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>, 116 117 CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()", 118 CCAssignToReg<[F12, F14, F16, F18]>>>, 119 120 // The first 4 double fp arguments are passed in single fp registers. 121 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", 122 CCAssignToReg<[D6, D7, D8, D9]>>>, 123 124 // Integer values get stored in stack slots that are 4 bytes in 125 // size and 4-byte aligned. 126 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 127 128 // Integer values get stored in stack slots that are 8 bytes in 129 // size and 8-byte aligned. 130 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>> 131]>; 132 133def RetCC_MipsEABI : CallingConv<[ 134 // i32 are returned in registers V0, V1 135 CCIfType<[i32], CCAssignToReg<[V0, V1]>>, 136 137 // f32 are returned in registers F0, F1 138 CCIfType<[f32], CCAssignToReg<[F0, F1]>>, 139 140 // f64 are returned in register D0 141 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>> 142]>; 143 144//===----------------------------------------------------------------------===// 145// Mips Calling Convention Dispatch 146//===----------------------------------------------------------------------===// 147 148def CC_Mips : CallingConv<[ 149 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>, 150 CCIfSubtarget<"isABI_N32()", CCDelegateTo<CC_MipsN>>, 151 CCIfSubtarget<"isABI_N64()", CCDelegateTo<CC_MipsN>> 152]>; 153 154def RetCC_Mips : CallingConv<[ 155 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>, 156 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>, 157 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>, 158 CCDelegateTo<RetCC_MipsO32> 159]>; 160