1 //===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsCallLowering.h"
16 #include "MipsCCState.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
21 
22 using namespace llvm;
23 
24 MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI)
25     : CallLowering(&TLI) {}
26 
27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA,
28                                            const EVT &VT) {
29   if (VA.isRegLoc()) {
30     assignValueToReg(VReg, VA, VT);
31   } else if (VA.isMemLoc()) {
32     assignValueToAddress(VReg, VA);
33   } else {
34     return false;
35   }
36   return true;
37 }
38 
39 bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs,
40                                                 ArrayRef<CCValAssign> ArgLocs,
41                                                 unsigned ArgLocsStartIndex,
42                                                 const EVT &VT) {
43   for (unsigned i = 0; i < VRegs.size(); ++i)
44     if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT))
45       return false;
46   return true;
47 }
48 
49 void MipsCallLowering::MipsHandler::setLeastSignificantFirst(
50     SmallVectorImpl<Register> &VRegs) {
51   if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
52     std::reverse(VRegs.begin(), VRegs.end());
53 }
54 
55 bool MipsCallLowering::MipsHandler::handle(
56     ArrayRef<CCValAssign> ArgLocs, ArrayRef<CallLowering::ArgInfo> Args) {
57   SmallVector<Register, 4> VRegs;
58   unsigned SplitLength;
59   const Function &F = MIRBuilder.getMF().getFunction();
60   const DataLayout &DL = F.getParent()->getDataLayout();
61   const MipsTargetLowering &TLI = *static_cast<const MipsTargetLowering *>(
62       MIRBuilder.getMF().getSubtarget().getTargetLowering());
63 
64   for (unsigned ArgsIndex = 0, ArgLocsIndex = 0; ArgsIndex < Args.size();
65        ++ArgsIndex, ArgLocsIndex += SplitLength) {
66     EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty);
67     SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(),
68                                                     F.getCallingConv(), VT);
69     assert(Args[ArgsIndex].Regs.size() == 1 && "Can't handle multple regs yet");
70 
71     if (SplitLength > 1) {
72       VRegs.clear();
73       MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
74           F.getContext(), F.getCallingConv(), VT);
75       for (unsigned i = 0; i < SplitLength; ++i)
76         VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
77 
78       if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0],
79                        VT))
80         return false;
81     } else {
82       if (!assign(Args[ArgsIndex].Regs[0], ArgLocs[ArgLocsIndex], VT))
83         return false;
84     }
85   }
86   return true;
87 }
88 
89 namespace {
90 class MipsIncomingValueHandler : public MipsCallLowering::MipsHandler {
91 public:
92   MipsIncomingValueHandler(MachineIRBuilder &MIRBuilder,
93                            MachineRegisterInfo &MRI)
94       : MipsHandler(MIRBuilder, MRI) {}
95 
96 private:
97   void assignValueToReg(Register ValVReg, const CCValAssign &VA,
98                         const EVT &VT) override;
99 
100   Register getStackAddress(const CCValAssign &VA,
101                            MachineMemOperand *&MMO) override;
102 
103   void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
104 
105   bool handleSplit(SmallVectorImpl<Register> &VRegs,
106                    ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
107                    Register ArgsReg, const EVT &VT) override;
108 
109   virtual void markPhysRegUsed(unsigned PhysReg) {
110     MIRBuilder.getMRI()->addLiveIn(PhysReg);
111     MIRBuilder.getMBB().addLiveIn(PhysReg);
112   }
113 
114   MachineInstrBuilder buildLoad(const DstOp &Res, const CCValAssign &VA) {
115     MachineMemOperand *MMO;
116     Register Addr = getStackAddress(VA, MMO);
117     return MIRBuilder.buildLoad(Res, Addr, *MMO);
118   }
119 };
120 
121 class CallReturnHandler : public MipsIncomingValueHandler {
122 public:
123   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
124                     MachineInstrBuilder &MIB)
125       : MipsIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
126 
127 private:
128   void markPhysRegUsed(unsigned PhysReg) override {
129     MIB.addDef(PhysReg, RegState::Implicit);
130   }
131 
132   MachineInstrBuilder &MIB;
133 };
134 
135 } // end anonymous namespace
136 
137 void MipsIncomingValueHandler::assignValueToReg(Register ValVReg,
138                                                 const CCValAssign &VA,
139                                                 const EVT &VT) {
140   Register PhysReg = VA.getLocReg();
141   if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
142     const MipsSubtarget &STI =
143         static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
144     bool IsEL = STI.isLittle();
145     LLT s32 = LLT::scalar(32);
146     auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1)));
147     auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 1 : 0)));
148     MIRBuilder.buildMerge(ValVReg, {Lo, Hi});
149     markPhysRegUsed(PhysReg);
150     markPhysRegUsed(PhysReg + 1);
151   } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
152     MIRBuilder.buildCopy(ValVReg, PhysReg);
153     markPhysRegUsed(PhysReg);
154   } else {
155     switch (VA.getLocInfo()) {
156     case CCValAssign::LocInfo::SExt:
157     case CCValAssign::LocInfo::ZExt:
158     case CCValAssign::LocInfo::AExt: {
159       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
160       MIRBuilder.buildTrunc(ValVReg, Copy);
161       break;
162     }
163     default:
164       MIRBuilder.buildCopy(ValVReg, PhysReg);
165       break;
166     }
167     markPhysRegUsed(PhysReg);
168   }
169 }
170 
171 Register MipsIncomingValueHandler::getStackAddress(const CCValAssign &VA,
172                                                    MachineMemOperand *&MMO) {
173   MachineFunction &MF = MIRBuilder.getMF();
174   unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
175   unsigned Offset = VA.getLocMemOffset();
176   MachineFrameInfo &MFI = MF.getFrameInfo();
177 
178   // FIXME: This should only be immutable for non-byval memory arguments.
179   int FI = MFI.CreateFixedObject(Size, Offset, true);
180   MachinePointerInfo MPO =
181       MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
182 
183   const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
184   Align Alignment = commonAlignment(TFL->getStackAlign(), Offset);
185   MMO =
186       MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Alignment);
187 
188   return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0);
189 }
190 
191 void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg,
192                                                     const CCValAssign &VA) {
193   if (VA.getLocInfo() == CCValAssign::SExt ||
194       VA.getLocInfo() == CCValAssign::ZExt ||
195       VA.getLocInfo() == CCValAssign::AExt) {
196     auto Load = buildLoad(LLT::scalar(32), VA);
197     MIRBuilder.buildTrunc(ValVReg, Load);
198   } else
199     buildLoad(ValVReg, VA);
200 }
201 
202 bool MipsIncomingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
203                                            ArrayRef<CCValAssign> ArgLocs,
204                                            unsigned ArgLocsStartIndex,
205                                            Register ArgsReg, const EVT &VT) {
206   if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
207     return false;
208   setLeastSignificantFirst(VRegs);
209   MIRBuilder.buildMerge(ArgsReg, VRegs);
210   return true;
211 }
212 
213 namespace {
214 class MipsOutgoingValueHandler : public MipsCallLowering::MipsHandler {
215 public:
216   MipsOutgoingValueHandler(MachineIRBuilder &MIRBuilder,
217                            MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
218       : MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
219 
220 private:
221   void assignValueToReg(Register ValVReg, const CCValAssign &VA,
222                         const EVT &VT) override;
223 
224   Register getStackAddress(const CCValAssign &VA,
225                            MachineMemOperand *&MMO) override;
226 
227   void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
228 
229   bool handleSplit(SmallVectorImpl<Register> &VRegs,
230                    ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
231                    Register ArgsReg, const EVT &VT) override;
232 
233   Register extendRegister(Register ValReg, const CCValAssign &VA);
234 
235   MachineInstrBuilder &MIB;
236 };
237 } // end anonymous namespace
238 
239 void MipsOutgoingValueHandler::assignValueToReg(Register ValVReg,
240                                                 const CCValAssign &VA,
241                                                 const EVT &VT) {
242   Register PhysReg = VA.getLocReg();
243   if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
244     const MipsSubtarget &STI =
245         static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
246     bool IsEL = STI.isLittle();
247     auto Unmerge = MIRBuilder.buildUnmerge(LLT::scalar(32), ValVReg);
248     MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 0 : 1)), Unmerge.getReg(0));
249     MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 1 : 0)), Unmerge.getReg(1));
250   } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
251     MIRBuilder.buildCopy(PhysReg, ValVReg);
252   } else {
253     Register ExtReg = extendRegister(ValVReg, VA);
254     MIRBuilder.buildCopy(PhysReg, ExtReg);
255     MIB.addUse(PhysReg, RegState::Implicit);
256   }
257 }
258 
259 Register MipsOutgoingValueHandler::getStackAddress(const CCValAssign &VA,
260                                                    MachineMemOperand *&MMO) {
261   MachineFunction &MF = MIRBuilder.getMF();
262   const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
263 
264   LLT p0 = LLT::pointer(0, 32);
265   LLT s32 = LLT::scalar(32);
266   auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP));
267 
268   unsigned Offset = VA.getLocMemOffset();
269   auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
270 
271   auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
272 
273   MachinePointerInfo MPO =
274       MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
275   unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
276   Align Alignment = commonAlignment(TFL->getStackAlign(), Offset);
277   MMO =
278       MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Alignment);
279 
280   return AddrReg.getReg(0);
281 }
282 
283 void MipsOutgoingValueHandler::assignValueToAddress(Register ValVReg,
284                                                     const CCValAssign &VA) {
285   MachineMemOperand *MMO;
286   Register Addr = getStackAddress(VA, MMO);
287   Register ExtReg = extendRegister(ValVReg, VA);
288   MIRBuilder.buildStore(ExtReg, Addr, *MMO);
289 }
290 
291 Register MipsOutgoingValueHandler::extendRegister(Register ValReg,
292                                                   const CCValAssign &VA) {
293   LLT LocTy{VA.getLocVT()};
294   switch (VA.getLocInfo()) {
295   case CCValAssign::SExt: {
296     return MIRBuilder.buildSExt(LocTy, ValReg).getReg(0);
297   }
298   case CCValAssign::ZExt: {
299     return MIRBuilder.buildZExt(LocTy, ValReg).getReg(0);
300   }
301   case CCValAssign::AExt: {
302     return MIRBuilder.buildAnyExt(LocTy, ValReg).getReg(0);
303   }
304   // TODO : handle upper extends
305   case CCValAssign::Full:
306     return ValReg;
307   default:
308     break;
309   }
310   llvm_unreachable("unable to extend register");
311 }
312 
313 bool MipsOutgoingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
314                                            ArrayRef<CCValAssign> ArgLocs,
315                                            unsigned ArgLocsStartIndex,
316                                            Register ArgsReg, const EVT &VT) {
317   MIRBuilder.buildUnmerge(VRegs, ArgsReg);
318   setLeastSignificantFirst(VRegs);
319   if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
320     return false;
321 
322   return true;
323 }
324 
325 static bool isSupportedArgumentType(Type *T) {
326   if (T->isIntegerTy())
327     return true;
328   if (T->isPointerTy())
329     return true;
330   if (T->isFloatingPointTy())
331     return true;
332   return false;
333 }
334 
335 static bool isSupportedReturnType(Type *T) {
336   if (T->isIntegerTy())
337     return true;
338   if (T->isPointerTy())
339     return true;
340   if (T->isFloatingPointTy())
341     return true;
342   if (T->isAggregateType())
343     return true;
344   return false;
345 }
346 
347 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
348                                              const ISD::ArgFlagsTy &Flags) {
349   // > does not mean loss of information as type RegisterVT can't hold type VT,
350   // it means that type VT is split into multiple registers of type RegisterVT
351   if (VT.getFixedSizeInBits() >= RegisterVT.getFixedSizeInBits())
352     return CCValAssign::LocInfo::Full;
353   if (Flags.isSExt())
354     return CCValAssign::LocInfo::SExt;
355   if (Flags.isZExt())
356     return CCValAssign::LocInfo::ZExt;
357   return CCValAssign::LocInfo::AExt;
358 }
359 
360 template <typename T>
361 static void setLocInfo(SmallVectorImpl<CCValAssign> &ArgLocs,
362                        const SmallVectorImpl<T> &Arguments) {
363   for (unsigned i = 0; i < ArgLocs.size(); ++i) {
364     const CCValAssign &VA = ArgLocs[i];
365     CCValAssign::LocInfo LocInfo = determineLocInfo(
366         Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
367     if (VA.isMemLoc())
368       ArgLocs[i] =
369           CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
370                               VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
371     else
372       ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
373                                        VA.getLocReg(), VA.getLocVT(), LocInfo);
374   }
375 }
376 
377 bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
378                                    const Value *Val, ArrayRef<Register> VRegs,
379                                    FunctionLoweringInfo &FLI) const {
380 
381   MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
382 
383   if (Val != nullptr && !isSupportedReturnType(Val->getType()))
384     return false;
385 
386   if (!VRegs.empty()) {
387     MachineFunction &MF = MIRBuilder.getMF();
388     const Function &F = MF.getFunction();
389     const DataLayout &DL = MF.getDataLayout();
390     const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
391 
392     SmallVector<ArgInfo, 8> RetInfos;
393 
394     ArgInfo ArgRetInfo(VRegs, Val->getType(), 0);
395     setArgFlags(ArgRetInfo, AttributeList::ReturnIndex, DL, F);
396     splitToValueTypes(ArgRetInfo, RetInfos, DL, F.getCallingConv());
397 
398     SmallVector<ISD::OutputArg, 8> Outs;
399     subTargetRegTypeForCallingConv(F, RetInfos, Outs);
400 
401     SmallVector<CCValAssign, 16> ArgLocs;
402     MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
403                        F.getContext());
404     CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
405     setLocInfo(ArgLocs, Outs);
406 
407     MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
408     if (!RetHandler.handle(ArgLocs, RetInfos)) {
409       return false;
410     }
411   }
412   MIRBuilder.insertInstr(Ret);
413   return true;
414 }
415 
416 bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
417                                             const Function &F,
418                                             ArrayRef<ArrayRef<Register>> VRegs,
419                                             FunctionLoweringInfo &FLI) const {
420 
421   // Quick exit if there aren't any args.
422   if (F.arg_empty())
423     return true;
424 
425   for (auto &Arg : F.args()) {
426     if (!isSupportedArgumentType(Arg.getType()))
427       return false;
428   }
429 
430   MachineFunction &MF = MIRBuilder.getMF();
431   const DataLayout &DL = MF.getDataLayout();
432   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
433 
434   SmallVector<ArgInfo, 8> ArgInfos;
435   unsigned i = 0;
436   for (auto &Arg : F.args()) {
437     ArgInfo AInfo(VRegs[i], Arg.getType(), i);
438     setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
439     ArgInfos.push_back(AInfo);
440     ++i;
441   }
442 
443   SmallVector<ISD::InputArg, 8> Ins;
444   subTargetRegTypeForCallingConv(F, ArgInfos, Ins);
445 
446   SmallVector<CCValAssign, 16> ArgLocs;
447   MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
448                      F.getContext());
449 
450   const MipsTargetMachine &TM =
451       static_cast<const MipsTargetMachine &>(MF.getTarget());
452   const MipsABIInfo &ABI = TM.getABI();
453   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
454                        Align(1));
455   CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
456   setLocInfo(ArgLocs, Ins);
457 
458   MipsIncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
459   if (!Handler.handle(ArgLocs, ArgInfos))
460     return false;
461 
462   if (F.isVarArg()) {
463     ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
464     unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
465 
466     int VaArgOffset;
467     unsigned RegSize = 4;
468     if (ArgRegs.size() == Idx)
469       VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
470     else {
471       VaArgOffset =
472           (int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) -
473           (int)(RegSize * (ArgRegs.size() - Idx));
474     }
475 
476     MachineFrameInfo &MFI = MF.getFrameInfo();
477     int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
478     MF.getInfo<MipsFunctionInfo>()->setVarArgsFrameIndex(FI);
479 
480     for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
481       MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);
482 
483       MachineInstrBuilder Copy =
484           MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
485       FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
486       MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI);
487       MachineInstrBuilder FrameIndex =
488           MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI);
489       MachineMemOperand *MMO = MF.getMachineMemOperand(
490           MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize));
491       MIRBuilder.buildStore(Copy, FrameIndex, *MMO);
492     }
493   }
494 
495   return true;
496 }
497 
498 bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
499                                  CallLoweringInfo &Info) const {
500 
501   if (Info.CallConv != CallingConv::C)
502     return false;
503 
504   for (auto &Arg : Info.OrigArgs) {
505     if (!isSupportedArgumentType(Arg.Ty))
506       return false;
507     if (Arg.Flags[0].isByVal())
508       return false;
509     if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy())
510       return false;
511   }
512 
513   if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedReturnType(Info.OrigRet.Ty))
514     return false;
515 
516   MachineFunction &MF = MIRBuilder.getMF();
517   const Function &F = MF.getFunction();
518   const DataLayout &DL = MF.getDataLayout();
519   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
520   const MipsTargetMachine &TM =
521       static_cast<const MipsTargetMachine &>(MF.getTarget());
522   const MipsABIInfo &ABI = TM.getABI();
523 
524   MachineInstrBuilder CallSeqStart =
525       MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
526 
527   const bool IsCalleeGlobalPIC =
528       Info.Callee.isGlobal() && TM.isPositionIndependent();
529 
530   MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
531       Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
532   MIB.addDef(Mips::SP, RegState::Implicit);
533   if (IsCalleeGlobalPIC) {
534     Register CalleeReg =
535         MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32));
536     MachineInstr *CalleeGlobalValue =
537         MIRBuilder.buildGlobalValue(CalleeReg, Info.Callee.getGlobal());
538     if (!Info.Callee.getGlobal()->hasLocalLinkage())
539       CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL);
540     MIB.addUse(CalleeReg);
541   } else
542     MIB.add(Info.Callee);
543   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
544   MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
545 
546   TargetLowering::ArgListTy FuncOrigArgs;
547   FuncOrigArgs.reserve(Info.OrigArgs.size());
548 
549   SmallVector<ArgInfo, 8> ArgInfos;
550   unsigned i = 0;
551   for (auto &Arg : Info.OrigArgs) {
552 
553     TargetLowering::ArgListEntry Entry;
554     Entry.Ty = Arg.Ty;
555     FuncOrigArgs.push_back(Entry);
556 
557     ArgInfos.push_back(Arg);
558     ++i;
559   }
560 
561   SmallVector<ISD::OutputArg, 8> Outs;
562   subTargetRegTypeForCallingConv(F, ArgInfos, Outs);
563 
564   SmallVector<CCValAssign, 8> ArgLocs;
565   bool IsCalleeVarArg = false;
566   if (Info.Callee.isGlobal()) {
567     const Function *CF = static_cast<const Function *>(Info.Callee.getGlobal());
568     IsCalleeVarArg = CF->isVarArg();
569   }
570   MipsCCState CCInfo(Info.CallConv, IsCalleeVarArg, MF, ArgLocs,
571                      F.getContext());
572 
573   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv),
574                        Align(1));
575   const char *Call =
576       Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr;
577   CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
578   setLocInfo(ArgLocs, Outs);
579 
580   MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
581   if (!RetHandler.handle(ArgLocs, ArgInfos)) {
582     return false;
583   }
584 
585   unsigned NextStackOffset = CCInfo.getNextStackOffset();
586   unsigned StackAlignment = F.getParent()->getOverrideStackAlignment();
587   if (!StackAlignment) {
588     const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
589     StackAlignment = TFL->getStackAlignment();
590   }
591   NextStackOffset = alignTo(NextStackOffset, StackAlignment);
592   CallSeqStart.addImm(NextStackOffset).addImm(0);
593 
594   if (IsCalleeGlobalPIC) {
595     MIRBuilder.buildCopy(
596       Register(Mips::GP),
597       MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel(MF));
598     MIB.addDef(Mips::GP, RegState::Implicit);
599   }
600   MIRBuilder.insertInstr(MIB);
601   if (MIB->getOpcode() == Mips::JALRPseudo) {
602     const MipsSubtarget &STI =
603         static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
604     MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
605                          *STI.getRegBankInfo());
606   }
607 
608   if (!Info.OrigRet.Ty->isVoidTy()) {
609     ArgInfos.clear();
610     splitToValueTypes(Info.OrigRet, ArgInfos, DL, Info.CallConv);
611 
612     SmallVector<ISD::InputArg, 8> Ins;
613     subTargetRegTypeForCallingConv(F, ArgInfos, Ins);
614 
615     SmallVector<CCValAssign, 8> ArgLocs;
616     MipsCCState CCInfo(Info.CallConv, F.isVarArg(), MF, ArgLocs,
617                        F.getContext());
618 
619     CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty,
620                              Call);
621     setLocInfo(ArgLocs, Ins);
622 
623     CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
624     if (!Handler.handle(ArgLocs, ArgInfos))
625       return false;
626   }
627 
628   MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
629 
630   return true;
631 }
632 
633 template <typename T>
634 void MipsCallLowering::subTargetRegTypeForCallingConv(
635     const Function &F, ArrayRef<ArgInfo> Args,
636     SmallVectorImpl<T> &ISDArgs) const {
637   const DataLayout &DL = F.getParent()->getDataLayout();
638   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
639 
640   unsigned ArgNo = 0;
641   for (auto &Arg : Args) {
642 
643     EVT VT = TLI.getValueType(DL, Arg.Ty);
644     MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
645                                                        F.getCallingConv(), VT);
646     unsigned NumRegs = TLI.getNumRegistersForCallingConv(
647         F.getContext(), F.getCallingConv(), VT);
648 
649     for (unsigned i = 0; i < NumRegs; ++i) {
650       ISD::ArgFlagsTy Flags = Arg.Flags[0];
651 
652       if (i == 0)
653         Flags.setOrigAlign(TLI.getABIAlignmentForCallingConv(Arg.Ty, DL));
654       else
655         Flags.setOrigAlign(Align(1));
656 
657       ISDArgs.emplace_back(Flags, RegisterVT, VT, true, Arg.OrigArgIndex,
658                            0);
659     }
660     ++ArgNo;
661   }
662 }
663