1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// shamt must fit in 6 bits. 19def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 20 21// Node immediate fits as 10-bit sign extended on target immediate. 22// e.g. seqi, snei 23def immSExt10_64 : PatLeaf<(i64 imm), 24 [{ return isInt<10>(N->getSExtValue()); }]>; 25 26def immZExt16_64 : PatLeaf<(i64 imm), 27 [{ return isUInt<16>(N->getZExtValue()); }]>; 28 29def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>; 30 31// Transformation function: get log2 of low 32 bits of immediate 32def Log2LO : SDNodeXForm<imm, [{ 33 return getImm(N, Log2_64((unsigned) N->getZExtValue())); 34}]>; 35 36// Transformation function: get log2 of high 32 bits of immediate 37def Log2HI : SDNodeXForm<imm, [{ 38 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32))); 39}]>; 40 41// Predicate: True if immediate is a power of 2 and fits 32 bits 42def PowerOf2LO : PatLeaf<(imm), [{ 43 if (N->getValueType(0) == MVT::i64) { 44 uint64_t Imm = N->getZExtValue(); 45 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm; 46 } 47 else 48 return false; 49}]>; 50 51// Predicate: True if immediate is a power of 2 and exceeds 32 bits 52def PowerOf2HI : PatLeaf<(imm), [{ 53 if (N->getValueType(0) == MVT::i64) { 54 uint64_t Imm = N->getZExtValue(); 55 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm; 56 } 57 else 58 return false; 59}]>; 60 61def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{ 62 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32); 63}]>; 64 65//===----------------------------------------------------------------------===// 66// Instructions specific format 67//===----------------------------------------------------------------------===// 68let usesCustomInserter = 1 in { 69 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 70 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 71 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 72 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 73 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 74 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 75 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 76 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 77} 78 79/// Pseudo instructions for loading and storing accumulator registers. 80let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { 81 def LOAD_ACC128 : Load<"", ACC128>; 82 def STORE_ACC128 : Store<"", ACC128>; 83} 84 85//===----------------------------------------------------------------------===// 86// Instruction definition 87//===----------------------------------------------------------------------===// 88let DecoderNamespace = "Mips64" in { 89/// Arithmetic Instructions (ALU Immediate) 90def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>, 91 ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6; 92let AdditionalPredicates = [NotInMicroMips] in { 93 def DADDiu : StdMMR6Rel, ArithLogicI<"daddiu", simm16_64, GPR64Opnd, 94 II_DADDIU, immSExt16, add>, 95 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3; 96} 97 98let isCodeGenOnly = 1 in { 99def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 100 SLTI_FM<0xa>; 101def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 102 SLTI_FM<0xb>; 103def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>, 104 ADDI_FM<0xc>; 105def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>, 106 ADDI_FM<0xd>; 107def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>, 108 ADDI_FM<0xe>; 109def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM; 110} 111 112/// Arithmetic Instructions (3-Operand, R-Type) 113let AdditionalPredicates = [NotInMicroMips] in { 114 def DADD : StdMMR6Rel, ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, 115 ADD_FM<0, 0x2c>, ISA_MIPS3; 116 def DADDu : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, 117 ADD_FM<0, 0x2d>, ISA_MIPS3; 118 def DSUBu : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>, 119 ISA_MIPS3; 120 def DSUB : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>, 121 ISA_MIPS3; 122} 123 124let isCodeGenOnly = 1 in { 125def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; 126def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>; 127def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>; 128def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>; 129def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>; 130def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>; 131} 132 133/// Shift Instructions 134let AdditionalPredicates = [NotInMicroMips] in { 135 def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, 136 shl, immZExt6>, 137 SRA_FM<0x38, 0>, ISA_MIPS3; 138 def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, 139 srl, immZExt6>, 140 SRA_FM<0x3a, 0>, ISA_MIPS3; 141 def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, 142 sra, immZExt6>, 143 SRA_FM<0x3b, 0>, ISA_MIPS3; 144 def DSLLV : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, 145 SRLV_FM<0x14, 0>, ISA_MIPS3; 146 def DSRAV : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, 147 SRLV_FM<0x17, 0>, ISA_MIPS3; 148 def DSRLV : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, 149 SRLV_FM<0x16, 0>, ISA_MIPS3; 150 def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, 151 II_DSLL32>, 152 SRA_FM<0x3c, 0>, ISA_MIPS3; 153 def DSRL32 : StdMMR6Rel, shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, 154 II_DSRL32>, 155 SRA_FM<0x3e, 0>, ISA_MIPS3; 156 def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, 157 II_DSRA32>, 158 SRA_FM<0x3f, 0>, ISA_MIPS3; 159 160// Rotate Instructions 161 def DROTR : StdMMR6Rel, shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, 162 rotr, immZExt6>, 163 SRA_FM<0x3a, 1>, ISA_MIPS64R2; 164 def DROTRV : StdMMR6Rel, shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, 165 rotr>, 166 SRLV_FM<0x16, 1>, ISA_MIPS64R2; 167 def DROTR32 : StdMMR6Rel, shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, 168 II_DROTR32>, 169 SRA_FM<0x3e, 1>, ISA_MIPS64R2; 170} 171 172/// Load and Store Instructions 173/// aligned 174let isCodeGenOnly = 1 in { 175def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>; 176def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>; 177def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>; 178def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>; 179def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>; 180def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>; 181def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>; 182def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>; 183} 184 185let AdditionalPredicates = [NotInMicroMips] in { 186 def LWu : StdMMR6Rel, MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, 187 LW_FM<0x27>, ISA_MIPS3; 188 def LD : StdMMR6Rel, LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>, 189 LW_FM<0x37>, ISA_MIPS3; 190 def SD : StdMMR6Rel, StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>, 191 LW_FM<0x3f>, ISA_MIPS3; 192} 193 194 195 196/// load/store left/right 197let isCodeGenOnly = 1 in { 198def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>; 199def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>; 200def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>; 201def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>; 202} 203 204def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>, 205 ISA_MIPS3_NOT_32R6_64R6; 206def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>, 207 ISA_MIPS3_NOT_32R6_64R6; 208def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>, 209 ISA_MIPS3_NOT_32R6_64R6; 210def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>, 211 ISA_MIPS3_NOT_32R6_64R6; 212 213/// Load-linked, Store-conditional 214let AdditionalPredicates = [NotInMicroMips] in { 215 def LLD : StdMMR6Rel, LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>, 216 ISA_MIPS3_NOT_32R6_64R6; 217} 218def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6; 219 220let AdditionalPredicates = [NotInMicroMips], 221 DecoderNamespace = "Mips32_64_PTR64" in { 222def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64, 223 ISA_MIPS2_NOT_32R6_64R6; 224def SC64 : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_64, 225 ISA_MIPS2_NOT_32R6_64R6; 226def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>, PTR_64; 227} 228 229def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; 230 231/// Jump and Branch Instructions 232let isCodeGenOnly = 1 in { 233 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>; 234 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>; 235 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>; 236 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; 237 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; 238 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; 239 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; 240} 241 242def TAILCALLREG64 : TailCallReg<GPR64Opnd>; 243 244def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; 245def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>; 246 247/// Multiply and Divide Instructions. 248let AdditionalPredicates = [NotInMicroMips] in { 249 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>, 250 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6; 251 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>, 252 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6; 253} 254def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 255 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6; 256def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 257 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6; 258let AdditionalPredicates = [NotInMicroMips] in { 259 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>, 260 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6; 261 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>, 262 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6; 263} 264def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 265 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 266def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 267 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 268 269let isCodeGenOnly = 1 in { 270def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>, 271 ISA_MIPS3_NOT_32R6_64R6; 272def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>, 273 ISA_MIPS3_NOT_32R6_64R6; 274def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>, 275 ISA_MIPS3_NOT_32R6_64R6; 276def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>, 277 ISA_MIPS3_NOT_32R6_64R6; 278def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>, 279 ISA_MIPS3_NOT_32R6_64R6; 280def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>, 281 ISA_MIPS3_NOT_32R6_64R6; 282def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6; 283 284/// Sign Ext In Register Instructions. 285def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>, 286 ISA_MIPS32R2; 287def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, 288 ISA_MIPS32R2; 289} 290 291/// Count Leading 292let AdditionalPredicates = [NotInMicroMips] in { 293 def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, 294 CLO_FM<0x24>, ISA_MIPS64_NOT_64R6; 295 def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd, II_DCLO>, 296 CLO_FM<0x25>, ISA_MIPS64_NOT_64R6; 297 298/// Double Word Swap Bytes/HalfWords 299 def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>, 300 ISA_MIPS64R2; 301 def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>, 302 ISA_MIPS64R2; 303} 304 305def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; 306 307let isCodeGenOnly = 1 in 308def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; 309 310let AdditionalPredicates = [NotInMicroMips] in { 311 // The 'pos + size' constraints are enforced by the code that lowers into 312 // MipsISD::Ext. 313 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1, 314 immZExt5, immZExt5Plus1, MipsExt>, EXT_FM<3>, 315 ISA_MIPS64R2; 316 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5, 317 immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2; 318 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, 319 immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>, 320 ISA_MIPS64R2; 321 def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, MipsIns>, 322 EXT_FM<7>, ISA_MIPS64R2; 323 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>, 324 EXT_FM<6>, ISA_MIPS64R2; 325 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm5_inssize_plus1>, 326 EXT_FM<5>, ISA_MIPS64R2; 327} 328 329let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 330 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 331 "dsll\t$rd, $rt, 32", [], II_DSLL>; 332 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 333 "sll\t$rd, $rt, 0", [], II_SLL>; 334 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 335 "sll\t$rd, $rt, 0", [], II_SLL>; 336} 337 338// We need the following pseudo instruction to avoid offset calculation for 339// long branches. See the comment in file MipsLongBranch.cpp for detailed 340// explanation. 341 342// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt) 343// where %PART may be %hi or %lo, depending on the relocation kind 344// that $tgt is annotated with. 345def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst), 346 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>; 347 348// Cavium Octeon cnMIPS instructions 349let DecoderNamespace = "CnMips", 350 // FIXME: The lack of HasStdEnc is probably a bug 351 EncodingPredicates = []<Predicate> in { 352 353class Count1s<string opstr, RegisterOperand RO>: 354 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 355 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> { 356 let TwoOperandAliasConstraint = "$rd = $rs"; 357} 358 359class ExtsCins<string opstr, InstrItinClass itin, 360 SDPatternOperator Op = null_frag>: 361 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1), 362 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"), 363 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))], 364 itin, FrmR, opstr> { 365 let TwoOperandAliasConstraint = "$rt = $rs"; 366} 367 368class SetCC64_R<string opstr, PatFrag cond_op> : 369 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 370 !strconcat(opstr, "\t$rd, $rs, $rt"), 371 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs, 372 GPR64Opnd:$rt)))], 373 II_SEQ_SNE, FrmR, opstr> { 374 let TwoOperandAliasConstraint = "$rd = $rs"; 375} 376 377class SetCC64_I<string opstr, PatFrag cond_op>: 378 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10), 379 !strconcat(opstr, "\t$rt, $rs, $imm10"), 380 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs, 381 immSExt10_64:$imm10)))], 382 II_SEQI_SNEI, FrmI, opstr> { 383 let TwoOperandAliasConstraint = "$rt = $rs"; 384} 385 386class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op, 387 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> : 388 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset), 389 !strconcat(opstr, "\t$rs, $p, $offset"), 390 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)), 391 bb:$offset)], II_BBIT, FrmI, opstr> { 392 let isBranch = 1; 393 let isTerminator = 1; 394 let hasDelaySlot = 1; 395 let Defs = [AT]; 396} 397 398class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> : 399 InstSE<(outs RO:$rt, uimm16:$imm16), (ins), 400 !strconcat(asmstr, "\t$rt, $imm16"), [], itin, FrmFR>; 401 402// Unsigned Byte Add 403def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, 404 ADD_FM<0x1c, 0x28>, ASE_CNMIPS { 405 let Pattern = [(set GPR64Opnd:$rd, 406 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))]; 407} 408 409// Branch on Bit Clear /+32 410def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd, 411 uimm5_64_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS; 412def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64, 413 0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS; 414 415// Branch on Bit Set /+32 416def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, 417 uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS; 418def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64, 419 0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS; 420 421// Multiply Doubleword to GPR 422def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, 423 ADD_FM<0x1c, 0x03>, ASE_CNMIPS { 424 let Defs = [HI0, LO0, P0, P1, P2]; 425} 426 427// Extract a signed bit field /+32 428def EXTS : ExtsCins<"exts", II_EXT>, EXTS_FM<0x3a>, ASE_CNMIPS; 429def EXTS32: ExtsCins<"exts32", II_EXT>, EXTS_FM<0x3b>, ASE_CNMIPS; 430 431// Clear and insert a bit field /+32 432def CINS : ExtsCins<"cins", II_INS>, EXTS_FM<0x32>, ASE_CNMIPS; 433def CINS32: ExtsCins<"cins32", II_INS>, EXTS_FM<0x33>, ASE_CNMIPS; 434 435// Move to multiplier/product register 436def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>, 437 ASE_CNMIPS; 438def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>, 439 ASE_CNMIPS; 440def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>, 441 ASE_CNMIPS; 442def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>, ASE_CNMIPS; 443def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>, ASE_CNMIPS; 444def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>, ASE_CNMIPS; 445 446// Count Ones in a Word/Doubleword 447def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>, ASE_CNMIPS; 448def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>, ASE_CNMIPS; 449 450// Set on equal/not equal 451def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>, ASE_CNMIPS; 452def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>, ASE_CNMIPS; 453def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS; 454def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS; 455 456// 192-bit x 64-bit Unsigned Multiply and Add 457def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x11>, 458 ASE_CNMIPS { 459 let Defs = [P0, P1, P2]; 460} 461 462// 64-bit Unsigned Multiply and Add Move 463def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x10>, 464 ASE_CNMIPS { 465 let Defs = [MPL0, P0, P1, P2]; 466} 467 468// 64-bit Unsigned Multiply and Add 469def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>, 470 ASE_CNMIPS { 471 let Defs = [MPL1, MPL2, P0, P1, P2]; 472} 473 474// Move between CPU and coprocessor registers 475def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd, II_DMFC2>, MFC2OP_FM<0x12, 1>, 476 ASE_CNMIPS; 477def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>, 478 ASE_CNMIPS; 479} 480 481} 482 483/// Move between CPU and coprocessor registers 484let DecoderNamespace = "Mips64", Predicates = [HasMips64] in { 485def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd, II_DMFC0>, MFC3OP_FM<0x10, 1>, 486 ISA_MIPS3; 487def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd, II_DMTC0>, MFC3OP_FM<0x10, 5>, 488 ISA_MIPS3; 489def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd, II_DMFC2>, MFC3OP_FM<0x12, 1>, 490 ISA_MIPS3; 491def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, MFC3OP_FM<0x12, 5>, 492 ISA_MIPS3; 493} 494 495//===----------------------------------------------------------------------===// 496// Arbitrary patterns that map to one or more instructions 497//===----------------------------------------------------------------------===// 498 499// Materialize i64 constants. 500defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>; 501 502def : MipsPat<(i64 immZExt32Low16Zero:$imm), 503 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>; 504 505def : MipsPat<(i64 immZExt32:$imm), 506 (ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16), 507 (LO16 imm:$imm))>; 508 509// extended loads 510def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 511def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 512def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 513def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 514 515// hi/lo relocs 516def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 517def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 518def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 519def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 520def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 521def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 522 523let AdditionalPredicates = [NotInMicroMips] in { 524 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 525 def : MipsPat<(MipsLo tblockaddress:$in), 526 (DADDiu ZERO_64, tblockaddress:$in)>; 527 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 528 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 529 def : MipsPat<(MipsLo tglobaltlsaddr:$in), 530 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 531 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 532 533 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)), 534 (DADDiu GPR64:$hi, tglobaladdr:$lo)>; 535 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)), 536 (DADDiu GPR64:$hi, tblockaddress:$lo)>; 537 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)), 538 (DADDiu GPR64:$hi, tjumptable:$lo)>; 539 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)), 540 (DADDiu GPR64:$hi, tconstpool:$lo)>; 541 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)), 542 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>; 543 544 def : WrapperPat<tglobaladdr, DADDiu, GPR64>; 545 def : WrapperPat<tconstpool, DADDiu, GPR64>; 546 def : WrapperPat<texternalsym, DADDiu, GPR64>; 547 def : WrapperPat<tblockaddress, DADDiu, GPR64>; 548 def : WrapperPat<tjumptable, DADDiu, GPR64>; 549 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>; 550} 551 552defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 553 ZERO_64>; 554def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 555 (BLEZ64 i64:$lhs, bb:$dst)>; 556def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 557 (BGEZ64 i64:$lhs, bb:$dst)>; 558 559// setcc patterns 560let AdditionalPredicates = [NotInMicroMips] in { 561 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; 562 defm : SetlePats<GPR64, XORi, SLT64, SLTu64>; 563 defm : SetgtPats<GPR64, SLT64, SLTu64>; 564 defm : SetgePats<GPR64, XORi, SLT64, SLTu64>; 565 defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>; 566} 567// truncate 568def : MipsPat<(trunc (assertsext GPR64:$src)), 569 (EXTRACT_SUBREG GPR64:$src, sub_32)>; 570// The forward compatibility strategy employed by MIPS requires us to treat 571// values as being sign extended to an infinite number of bits. This allows 572// existing software to run without modification on any future MIPS 573// implementation (e.g. 128-bit, or 1024-bit). Being compatible with this 574// strategy requires that truncation acts as a sign-extension for values being 575// fed into instructions operating on 32-bit values. Such instructions have 576// undefined results if this is not true. 577// For our case, this means that we can't issue an extract_subreg for nodes 578// such as (trunc:i32 (assertzext:i64 X, i32)), because the sign-bit of the 579// lower subreg would not be replicated into the upper half. 580def : MipsPat<(trunc (assertzext_lt_i32 GPR64:$src)), 581 (EXTRACT_SUBREG GPR64:$src, sub_32)>; 582def : MipsPat<(i32 (trunc GPR64:$src)), 583 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; 584 585// variable shift instructions patterns 586def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))), 587 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 588def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))), 589 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 590def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))), 591 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 592let AdditionalPredicates = [NotInMicroMips] in { 593 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))), 594 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 595} 596 597// 32-to-64-bit extension 598def : MipsPat<(i64 (anyext GPR32:$src)), 599 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; 600def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; 601def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; 602 603// Sign extend in register 604def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 605 (SLL64_64 GPR64:$src)>; 606 607// bswap MipsPattern 608def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; 609 610// Carry pattern 611let AdditionalPredicates = [NotInMicroMips] in { 612 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), 613 (DSUBu GPR64:$lhs, GPR64:$rhs)>; 614 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), 615 (DADDu GPR64:$lhs, GPR64:$rhs)>, ASE_NOT_DSP; 616 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), 617 (DADDiu GPR64:$lhs, imm:$imm)>, ASE_NOT_DSP; 618} 619 620// Octeon bbit0/bbit1 MipsPattern 621def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 622 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; 623def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 624 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; 625def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 626 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; 627def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 628 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; 629 630// Atomic load patterns. 631def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>; 632def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>; 633def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>; 634def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>; 635 636// Atomic store patterns. 637def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>; 638def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>; 639def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>; 640def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>; 641 642//===----------------------------------------------------------------------===// 643// Instruction aliases 644//===----------------------------------------------------------------------===// 645let AdditionalPredicates = [NotInMicroMips] in { 646 def : MipsInstAlias<"move $dst, $src", 647 (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 648 GPR_64; 649 def : MipsInstAlias<"move $dst, $src", 650 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 651 GPR_64; 652 def : MipsInstAlias<"dadd $rs, $rt, $imm", 653 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 654 0>, ISA_MIPS3_NOT_32R6_64R6; 655 def : MipsInstAlias<"dadd $rs, $imm", 656 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 657 0>, ISA_MIPS3_NOT_32R6_64R6; 658 def : MipsInstAlias<"daddu $rs, $rt, $imm", 659 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 660 0>, ISA_MIPS3; 661 def : MipsInstAlias<"daddu $rs, $imm", 662 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 663 0>, ISA_MIPS3; 664} 665def : MipsInstAlias<"dsll $rd, $rt, $rs", 666 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 667 ISA_MIPS3; 668let AdditionalPredicates = [NotInMicroMips] in { 669 def : MipsInstAlias<"dneg $rt, $rs", 670 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 671 ISA_MIPS3; 672 def : MipsInstAlias<"dneg $rt", 673 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, 674 ISA_MIPS3; 675 def : MipsInstAlias<"dnegu $rt, $rs", 676 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 677 ISA_MIPS3; 678 def : MipsInstAlias<"dnegu $rt", 679 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, 680 ISA_MIPS3; 681} 682def : MipsInstAlias<"dsubi $rs, $rt, $imm", 683 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 684 InvertedImOperand64:$imm), 685 0>, ISA_MIPS3_NOT_32R6_64R6; 686def : MipsInstAlias<"dsubi $rs, $imm", 687 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 688 InvertedImOperand64:$imm), 689 0>, ISA_MIPS3_NOT_32R6_64R6; 690def : MipsInstAlias<"dsub $rs, $rt, $imm", 691 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 692 InvertedImOperand64:$imm), 693 0>, ISA_MIPS3_NOT_32R6_64R6; 694def : MipsInstAlias<"dsub $rs, $imm", 695 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 696 InvertedImOperand64:$imm), 697 0>, ISA_MIPS3_NOT_32R6_64R6; 698let AdditionalPredicates = [NotInMicroMips] in { 699 def : MipsInstAlias<"dsubu $rt, $rs, $imm", 700 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, 701 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 702 def : MipsInstAlias<"dsubu $rs, $imm", 703 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, 704 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 705} 706def : MipsInstAlias<"dsra $rd, $rt, $rs", 707 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 708 ISA_MIPS3; 709let AdditionalPredicates = [NotInMicroMips] in { 710 def : MipsInstAlias<"dsrl $rd, $rt, $rs", 711 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 712 ISA_MIPS3; 713 714// Two operand (implicit 0 selector) versions: 715 def : MipsInstAlias<"dmtc0 $rt, $rd", 716 (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 717 def : MipsInstAlias<"dmfc0 $rt, $rd", 718 (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>; 719} 720def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; 721def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 722 723def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS; 724def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS; 725def : MipsInstAlias<"syncw", (SYNC 0x4), 0>, ASE_MIPS64_CNMIPS; 726def : MipsInstAlias<"syncws", (SYNC 0x5), 0>, ASE_MIPS64_CNMIPS; 727 728// cnMIPS Aliases. 729 730// bbit* with $p 32-63 converted to bbit*32 with $p 0-31 731def : MipsInstAlias<"bbit0 $rs, $p, $offset", 732 (BBIT032 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 733 brtarget:$offset), 0>, 734 ASE_CNMIPS; 735def : MipsInstAlias<"bbit1 $rs, $p, $offset", 736 (BBIT132 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 737 brtarget:$offset), 0>, 738 ASE_CNMIPS; 739 740// exts with $pos 32-63 in converted to exts32 with $pos 0-31 741def : MipsInstAlias<"exts $rt, $rs, $pos, $lenm1", 742 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 743 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 744 ASE_CNMIPS; 745def : MipsInstAlias<"exts $rt, $pos, $lenm1", 746 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 747 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 748 ASE_CNMIPS; 749 750// cins with $pos 32-63 in converted to cins32 with $pos 0-31 751def : MipsInstAlias<"cins $rt, $rs, $pos, $lenm1", 752 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 753 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 754 ASE_CNMIPS; 755def : MipsInstAlias<"cins $rt, $pos, $lenm1", 756 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 757 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 758 ASE_CNMIPS; 759 760//===----------------------------------------------------------------------===// 761// Assembler Pseudo Instructions 762//===----------------------------------------------------------------------===// 763 764class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> : 765 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64), 766 !strconcat(instr_asm, "\t$rt, $imm64")> ; 767def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>; 768 769def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr), 770 "dla\t$rt, $addr">; 771def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64), 772 "dla\t$rt, $imm64">; 773