1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Mips16InstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 
25 using namespace llvm;
26 
27 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
28   : MipsInstrInfo(tm, /* FIXME: set mips16 unconditional br */ 0),
29     RI(*tm.getSubtargetImpl()) {}
30 
31 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
32   return RI;
33 }
34 
35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot.  If
38 /// not, return 0.  This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
40 unsigned Mips16InstrInfo::
41 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
42 {
43   return 0;
44 }
45 
46 /// isStoreToStackSlot - If the specified machine instruction is a direct
47 /// store to a stack slot, return the virtual or physical register number of
48 /// the source reg along with the FrameIndex of the loaded stack slot.  If
49 /// not, return 0.  This predicate must return 0 if the instruction has
50 /// any side effects other than storing to the stack slot.
51 unsigned Mips16InstrInfo::
52 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
53 {
54   return 0;
55 }
56 
57 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
58                                   MachineBasicBlock::iterator I, DebugLoc DL,
59                                   unsigned DestReg, unsigned SrcReg,
60                                   bool KillSrc) const {
61   unsigned Opc = 0, ZeroReg = 0;
62 
63   if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
64     if (Mips::CPURegsRegClass.contains(SrcReg))
65       Opc = Mips::Move32R16;
66   }
67 
68   assert(Opc && "Cannot copy registers");
69 
70   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
71 
72   if (DestReg)
73     MIB.addReg(DestReg, RegState::Define);
74 
75   if (ZeroReg)
76     MIB.addReg(ZeroReg);
77 
78   if (SrcReg)
79     MIB.addReg(SrcReg, getKillRegState(KillSrc));
80 }
81 
82 void Mips16InstrInfo::
83 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
84                     unsigned SrcReg, bool isKill, int FI,
85                     const TargetRegisterClass *RC,
86                     const TargetRegisterInfo *TRI) const {
87   DebugLoc DL;
88   if (I != MBB.end()) DL = I->getDebugLoc();
89   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
90   unsigned Opc = 0;
91   if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
92     Opc = Mips::SwRxSpImmX16;
93   assert(Opc && "Register class not handled!");
94   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
95     .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
96 }
97 
98 void Mips16InstrInfo::
99 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
100                      unsigned DestReg, int FI,
101                      const TargetRegisterClass *RC,
102                      const TargetRegisterInfo *TRI) const {
103   DebugLoc DL;
104   if (I != MBB.end()) DL = I->getDebugLoc();
105   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
106   unsigned Opc = 0;
107 
108   if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
109     Opc = Mips::LwRxSpImmX16;
110   assert(Opc && "Register class not handled!");
111   BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
112     .addMemOperand(MMO);
113 }
114 
115 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
116   MachineBasicBlock &MBB = *MI->getParent();
117 
118   switch(MI->getDesc().getOpcode()) {
119   default:
120     return false;
121   case Mips::RetRA16:
122     ExpandRetRA16(MBB, MI, Mips::JrRa16);
123     break;
124   }
125 
126   MBB.erase(MI);
127   return true;
128 }
129 
130 /// GetOppositeBranchOpc - Return the inverse of the specified
131 /// opcode, e.g. turning BEQ to BNE.
132 unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
133   assert(false && "Implement this function.");
134   return 0;
135 }
136 
137 unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
138   return 0;
139 }
140 
141 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
142                                   MachineBasicBlock::iterator I,
143                                   unsigned Opc) const {
144   BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
145 }
146 
147 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
148   return new Mips16InstrInfo(TM);
149 }
150