1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Subclass of MipsTargetLowering specialized for mips16. 11 // 12 //===----------------------------------------------------------------------===// 13 #include "Mips16ISelLowering.h" 14 #include "MCTargetDesc/MipsBaseInfo.h" 15 #include "Mips16HardFloatInfo.h" 16 #include "MipsMachineFunction.h" 17 #include "MipsRegisterInfo.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/Support/CommandLine.h" 22 #include "llvm/Target/TargetInstrInfo.h" 23 #include <string> 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-lower" 28 29 static cl::opt<bool> DontExpandCondPseudos16( 30 "mips16-dont-expand-cond-pseudo", 31 cl::init(false), 32 cl::desc("Don't expand conditional move related " 33 "pseudos for Mips 16"), 34 cl::Hidden); 35 36 namespace { 37 struct Mips16Libcall { 38 RTLIB::Libcall Libcall; 39 const char *Name; 40 41 bool operator<(const Mips16Libcall &RHS) const { 42 return std::strcmp(Name, RHS.Name) < 0; 43 } 44 }; 45 46 struct Mips16IntrinsicHelperType{ 47 const char* Name; 48 const char* Helper; 49 50 bool operator<(const Mips16IntrinsicHelperType &RHS) const { 51 return std::strcmp(Name, RHS.Name) < 0; 52 } 53 bool operator==(const Mips16IntrinsicHelperType &RHS) const { 54 return std::strcmp(Name, RHS.Name) == 0; 55 } 56 }; 57 } 58 59 // Libcalls for which no helper is generated. Sorted by name for binary search. 60 static const Mips16Libcall HardFloatLibCalls[] = { 61 { RTLIB::ADD_F64, "__mips16_adddf3" }, 62 { RTLIB::ADD_F32, "__mips16_addsf3" }, 63 { RTLIB::DIV_F64, "__mips16_divdf3" }, 64 { RTLIB::DIV_F32, "__mips16_divsf3" }, 65 { RTLIB::OEQ_F64, "__mips16_eqdf2" }, 66 { RTLIB::OEQ_F32, "__mips16_eqsf2" }, 67 { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" }, 68 { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" }, 69 { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" }, 70 { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" }, 71 { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" }, 72 { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" }, 73 { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" }, 74 { RTLIB::OGE_F64, "__mips16_gedf2" }, 75 { RTLIB::OGE_F32, "__mips16_gesf2" }, 76 { RTLIB::OGT_F64, "__mips16_gtdf2" }, 77 { RTLIB::OGT_F32, "__mips16_gtsf2" }, 78 { RTLIB::OLE_F64, "__mips16_ledf2" }, 79 { RTLIB::OLE_F32, "__mips16_lesf2" }, 80 { RTLIB::OLT_F64, "__mips16_ltdf2" }, 81 { RTLIB::OLT_F32, "__mips16_ltsf2" }, 82 { RTLIB::MUL_F64, "__mips16_muldf3" }, 83 { RTLIB::MUL_F32, "__mips16_mulsf3" }, 84 { RTLIB::UNE_F64, "__mips16_nedf2" }, 85 { RTLIB::UNE_F32, "__mips16_nesf2" }, 86 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall. 87 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall. 88 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall. 89 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall. 90 { RTLIB::SUB_F64, "__mips16_subdf3" }, 91 { RTLIB::SUB_F32, "__mips16_subsf3" }, 92 { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" }, 93 { RTLIB::UO_F64, "__mips16_unorddf2" }, 94 { RTLIB::UO_F32, "__mips16_unordsf2" } 95 }; 96 97 static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = { 98 {"__fixunsdfsi", "__mips16_call_stub_2" }, 99 {"ceil", "__mips16_call_stub_df_2"}, 100 {"ceilf", "__mips16_call_stub_sf_1"}, 101 {"copysign", "__mips16_call_stub_df_10"}, 102 {"copysignf", "__mips16_call_stub_sf_5"}, 103 {"cos", "__mips16_call_stub_df_2"}, 104 {"cosf", "__mips16_call_stub_sf_1"}, 105 {"exp2", "__mips16_call_stub_df_2"}, 106 {"exp2f", "__mips16_call_stub_sf_1"}, 107 {"floor", "__mips16_call_stub_df_2"}, 108 {"floorf", "__mips16_call_stub_sf_1"}, 109 {"log2", "__mips16_call_stub_df_2"}, 110 {"log2f", "__mips16_call_stub_sf_1"}, 111 {"nearbyint", "__mips16_call_stub_df_2"}, 112 {"nearbyintf", "__mips16_call_stub_sf_1"}, 113 {"rint", "__mips16_call_stub_df_2"}, 114 {"rintf", "__mips16_call_stub_sf_1"}, 115 {"sin", "__mips16_call_stub_df_2"}, 116 {"sinf", "__mips16_call_stub_sf_1"}, 117 {"sqrt", "__mips16_call_stub_df_2"}, 118 {"sqrtf", "__mips16_call_stub_sf_1"}, 119 {"trunc", "__mips16_call_stub_df_2"}, 120 {"truncf", "__mips16_call_stub_sf_1"}, 121 }; 122 123 Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM, 124 const MipsSubtarget &STI) 125 : MipsTargetLowering(TM, STI) { 126 127 // Set up the register classes 128 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 129 130 if (!TM.Options.UseSoftFloat) 131 setMips16HardFloatLibCalls(); 132 133 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 134 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 135 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 136 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 137 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 138 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 139 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 140 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 141 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 142 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 143 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 144 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 145 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 146 147 setOperationAction(ISD::ROTR, MVT::i32, Expand); 148 setOperationAction(ISD::ROTR, MVT::i64, Expand); 149 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 150 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 151 152 computeRegisterProperties(); 153 } 154 155 const MipsTargetLowering * 156 llvm::createMips16TargetLowering(const MipsTargetMachine &TM, 157 const MipsSubtarget &STI) { 158 return new Mips16TargetLowering(TM, STI); 159 } 160 161 bool 162 Mips16TargetLowering::allowsMisalignedMemoryAccesses(EVT VT, 163 unsigned, 164 unsigned, 165 bool *Fast) const { 166 return false; 167 } 168 169 MachineBasicBlock * 170 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 171 MachineBasicBlock *BB) const { 172 switch (MI->getOpcode()) { 173 default: 174 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 175 case Mips::SelBeqZ: 176 return emitSel16(Mips::BeqzRxImm16, MI, BB); 177 case Mips::SelBneZ: 178 return emitSel16(Mips::BnezRxImm16, MI, BB); 179 case Mips::SelTBteqZCmpi: 180 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB); 181 case Mips::SelTBteqZSlti: 182 return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB); 183 case Mips::SelTBteqZSltiu: 184 return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB); 185 case Mips::SelTBtneZCmpi: 186 return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB); 187 case Mips::SelTBtneZSlti: 188 return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB); 189 case Mips::SelTBtneZSltiu: 190 return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB); 191 case Mips::SelTBteqZCmp: 192 return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB); 193 case Mips::SelTBteqZSlt: 194 return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB); 195 case Mips::SelTBteqZSltu: 196 return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB); 197 case Mips::SelTBtneZCmp: 198 return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB); 199 case Mips::SelTBtneZSlt: 200 return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB); 201 case Mips::SelTBtneZSltu: 202 return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB); 203 case Mips::BteqzT8CmpX16: 204 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB); 205 case Mips::BteqzT8SltX16: 206 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB); 207 case Mips::BteqzT8SltuX16: 208 // TBD: figure out a way to get this or remove the instruction 209 // altogether. 210 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB); 211 case Mips::BtnezT8CmpX16: 212 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB); 213 case Mips::BtnezT8SltX16: 214 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB); 215 case Mips::BtnezT8SltuX16: 216 // TBD: figure out a way to get this or remove the instruction 217 // altogether. 218 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB); 219 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins( 220 Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 221 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins( 222 Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 223 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins( 224 Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 225 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins( 226 Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 227 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins( 228 Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 229 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins( 230 Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 231 break; 232 case Mips::SltCCRxRy16: 233 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB); 234 break; 235 case Mips::SltiCCRxImmX16: 236 return emitFEXT_CCRXI16_ins 237 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); 238 case Mips::SltiuCCRxImmX16: 239 return emitFEXT_CCRXI16_ins 240 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB); 241 case Mips::SltuCCRxRy16: 242 return emitFEXT_CCRX16_ins 243 (Mips::SltuRxRy16, MI, BB); 244 } 245 } 246 247 bool Mips16TargetLowering:: 248 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 249 unsigned NextStackOffset, 250 const MipsFunctionInfo& FI) const { 251 // No tail call optimization for mips16. 252 return false; 253 } 254 255 void Mips16TargetLowering::setMips16HardFloatLibCalls() { 256 for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) { 257 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) && 258 "Array not sorted!"); 259 if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL) 260 setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name); 261 } 262 263 setLibcallName(RTLIB::O_F64, "__mips16_unorddf2"); 264 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2"); 265 } 266 267 // 268 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much 269 // cleaner way to do all of this but it will have to wait until the traditional 270 // gcc mechanism is completed. 271 // 272 // For Pic, in order for Mips16 code to call Mips32 code which according the abi 273 // have either arguments or returned values placed in floating point registers, 274 // we use a set of helper functions. (This includes functions which return type 275 // complex which on Mips are returned in a pair of floating point registers). 276 // 277 // This is an encoding that we inherited from gcc. 278 // In Mips traditional O32, N32 ABI, floating point numbers are passed in 279 // floating point argument registers 1,2 only when the first and optionally 280 // the second arguments are float (sf) or double (df). 281 // For Mips16 we are only concerned with the situations where floating point 282 // arguments are being passed in floating point registers by the ABI, because 283 // Mips16 mode code cannot execute floating point instructions to load those 284 // values and hence helper functions are needed. 285 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df) 286 // the helper function suffixs for these are: 287 // 0, 1, 5, 9, 2, 6, 10 288 // this suffix can then be calculated as follows: 289 // for a given argument Arg: 290 // Arg1x, Arg2x = 1 : Arg is sf 291 // 2 : Arg is df 292 // 0: Arg is neither sf or df 293 // So this stub is the string for number Arg1x + Arg2x*4. 294 // However not all numbers between 0 and 10 are possible, we check anyway and 295 // assert if the impossible exists. 296 // 297 298 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber 299 (ArgListTy &Args) const { 300 unsigned int resultNum = 0; 301 if (Args.size() >= 1) { 302 Type *t = Args[0].Ty; 303 if (t->isFloatTy()) { 304 resultNum = 1; 305 } 306 else if (t->isDoubleTy()) { 307 resultNum = 2; 308 } 309 } 310 if (resultNum) { 311 if (Args.size() >=2) { 312 Type *t = Args[1].Ty; 313 if (t->isFloatTy()) { 314 resultNum += 4; 315 } 316 else if (t->isDoubleTy()) { 317 resultNum += 8; 318 } 319 } 320 } 321 return resultNum; 322 } 323 324 // 325 // Prefixes are attached to stub numbers depending on the return type. 326 // return type: float sf_ 327 // double df_ 328 // single complex sc_ 329 // double complext dc_ 330 // others NO PREFIX 331 // 332 // 333 // The full name of a helper function is__mips16_call_stub + 334 // return type dependent prefix + stub number 335 // 336 // FIXME: This is something that probably should be in a different source file 337 // and perhaps done differently but my main purpose is to not waste runtime 338 // on something that we can enumerate in the source. Another possibility is 339 // to have a python script to generate these mapping tables. This will do 340 // for now. There are a whole series of helper function mapping arrays, one 341 // for each return type class as outlined above. There there are 11 possible 342 // entries. Ones with 0 are ones which should never be selected. 343 // 344 // All the arrays are similar except for ones which return neither 345 // sf, df, sc, dc, in which we only care about ones which have sf or df as a 346 // first parameter. 347 // 348 #define P_ "__mips16_call_stub_" 349 #define MAX_STUB_NUMBER 10 350 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10" 351 #define T P "0" , T1 352 #define P P_ 353 static char const * vMips16Helper[MAX_STUB_NUMBER+1] = 354 {nullptr, T1 }; 355 #undef P 356 #define P P_ "sf_" 357 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] = 358 { T }; 359 #undef P 360 #define P P_ "df_" 361 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] = 362 { T }; 363 #undef P 364 #define P P_ "sc_" 365 static char const * scMips16Helper[MAX_STUB_NUMBER+1] = 366 { T }; 367 #undef P 368 #define P P_ "dc_" 369 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] = 370 { T }; 371 #undef P 372 #undef P_ 373 374 375 const char* Mips16TargetLowering:: 376 getMips16HelperFunction 377 (Type* RetTy, ArgListTy &Args, bool &needHelper) const { 378 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args); 379 #ifndef NDEBUG 380 const unsigned int maxStubNum = 10; 381 assert(stubNum <= maxStubNum); 382 const bool validStubNum[maxStubNum+1] = 383 {true, true, true, false, false, true, true, false, false, true, true}; 384 assert(validStubNum[stubNum]); 385 #endif 386 const char *result; 387 if (RetTy->isFloatTy()) { 388 result = sfMips16Helper[stubNum]; 389 } 390 else if (RetTy ->isDoubleTy()) { 391 result = dfMips16Helper[stubNum]; 392 } 393 else if (RetTy->isStructTy()) { 394 // check if it's complex 395 if (RetTy->getNumContainedTypes() == 2) { 396 if ((RetTy->getContainedType(0)->isFloatTy()) && 397 (RetTy->getContainedType(1)->isFloatTy())) { 398 result = scMips16Helper[stubNum]; 399 } 400 else if ((RetTy->getContainedType(0)->isDoubleTy()) && 401 (RetTy->getContainedType(1)->isDoubleTy())) { 402 result = dcMips16Helper[stubNum]; 403 } 404 else { 405 llvm_unreachable("Uncovered condition"); 406 } 407 } 408 else { 409 llvm_unreachable("Uncovered condition"); 410 } 411 } 412 else { 413 if (stubNum == 0) { 414 needHelper = false; 415 return ""; 416 } 417 result = vMips16Helper[stubNum]; 418 } 419 needHelper = true; 420 return result; 421 } 422 423 void Mips16TargetLowering:: 424 getOpndList(SmallVectorImpl<SDValue> &Ops, 425 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 426 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 427 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 428 SDValue Chain) const { 429 SelectionDAG &DAG = CLI.DAG; 430 MachineFunction &MF = DAG.getMachineFunction(); 431 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 432 const char* Mips16HelperFunction = nullptr; 433 bool NeedMips16Helper = false; 434 435 if (Subtarget.inMips16HardFloat()) { 436 // 437 // currently we don't have symbols tagged with the mips16 or mips32 438 // qualifier so we will assume that we don't know what kind it is. 439 // and generate the helper 440 // 441 bool LookupHelper = true; 442 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) { 443 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() }; 444 445 if (std::binary_search(std::begin(HardFloatLibCalls), 446 std::end(HardFloatLibCalls), Find)) 447 LookupHelper = false; 448 else { 449 const char *Symbol = S->getSymbol(); 450 Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" }; 451 const Mips16HardFloatInfo::FuncSignature *Signature = 452 Mips16HardFloatInfo::findFuncSignature(Symbol); 453 if (!IsPICCall && (Signature && (FuncInfo->StubsNeeded.find(Symbol) == 454 FuncInfo->StubsNeeded.end()))) { 455 FuncInfo->StubsNeeded[Symbol] = Signature; 456 // 457 // S2 is normally saved if the stub is for a function which 458 // returns a float or double value and is not otherwise. This is 459 // because more work is required after the function the stub 460 // is calling completes, and so the stub cannot directly return 461 // and the stub has no stack space to store the return address so 462 // S2 is used for that purpose. 463 // In order to take advantage of not saving S2, we need to also 464 // optimize the call in the stub and this requires some further 465 // functionality in MipsAsmPrinter which we don't have yet. 466 // So for now we always save S2. The optimization will be done 467 // in a follow-on patch. 468 // 469 if (1 || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet)) 470 FuncInfo->setSaveS2(); 471 } 472 // one more look at list of intrinsics 473 const Mips16IntrinsicHelperType *Helper = 474 std::lower_bound(std::begin(Mips16IntrinsicHelper), 475 std::end(Mips16IntrinsicHelper), IntrinsicFind); 476 if (Helper != std::end(Mips16IntrinsicHelper) && 477 *Helper == IntrinsicFind) { 478 Mips16HelperFunction = Helper->Helper; 479 NeedMips16Helper = true; 480 LookupHelper = false; 481 } 482 483 } 484 } else if (GlobalAddressSDNode *G = 485 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 486 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, 487 G->getGlobal()->getName().data() }; 488 489 if (std::binary_search(std::begin(HardFloatLibCalls), 490 std::end(HardFloatLibCalls), Find)) 491 LookupHelper = false; 492 } 493 if (LookupHelper) 494 Mips16HelperFunction = 495 getMips16HelperFunction(CLI.RetTy, CLI.getArgs(), NeedMips16Helper); 496 } 497 498 SDValue JumpTarget = Callee; 499 500 // T9 should contain the address of the callee function if 501 // -reloction-model=pic or it is an indirect call. 502 if (IsPICCall || !GlobalOrExternal) { 503 unsigned V0Reg = Mips::V0; 504 if (NeedMips16Helper) { 505 RegsToPass.push_front(std::make_pair(V0Reg, Callee)); 506 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy()); 507 ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget); 508 JumpTarget = getAddrGlobal(S, JumpTarget.getValueType(), DAG, 509 MipsII::MO_GOT, Chain, 510 FuncInfo->callPtrInfo(S->getSymbol())); 511 } else 512 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee)); 513 } 514 515 Ops.push_back(JumpTarget); 516 517 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 518 InternalLinkage, IsCallReloc, CLI, Callee, 519 Chain); 520 } 521 522 MachineBasicBlock *Mips16TargetLowering:: 523 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { 524 if (DontExpandCondPseudos16) 525 return BB; 526 const TargetInstrInfo *TII = 527 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 528 DebugLoc DL = MI->getDebugLoc(); 529 // To "insert" a SELECT_CC instruction, we actually have to insert the 530 // diamond control-flow pattern. The incoming instruction knows the 531 // destination vreg to set, the condition code register to branch on, the 532 // true/false values to select between, and a branch opcode to use. 533 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 534 MachineFunction::iterator It = BB; 535 ++It; 536 537 // thisMBB: 538 // ... 539 // TrueVal = ... 540 // setcc r1, r2, r3 541 // bNE r1, r0, copy1MBB 542 // fallthrough --> copy0MBB 543 MachineBasicBlock *thisMBB = BB; 544 MachineFunction *F = BB->getParent(); 545 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 546 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 547 F->insert(It, copy0MBB); 548 F->insert(It, sinkMBB); 549 550 // Transfer the remainder of BB and its successor edges to sinkMBB. 551 sinkMBB->splice(sinkMBB->begin(), BB, 552 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 553 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 554 555 // Next, add the true and fallthrough blocks as its successors. 556 BB->addSuccessor(copy0MBB); 557 BB->addSuccessor(sinkMBB); 558 559 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) 560 .addMBB(sinkMBB); 561 562 // copy0MBB: 563 // %FalseValue = ... 564 // # fallthrough to sinkMBB 565 BB = copy0MBB; 566 567 // Update machine-CFG edges 568 BB->addSuccessor(sinkMBB); 569 570 // sinkMBB: 571 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 572 // ... 573 BB = sinkMBB; 574 575 BuildMI(*BB, BB->begin(), DL, 576 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 577 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 578 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 579 580 MI->eraseFromParent(); // The pseudo instruction is gone now. 581 return BB; 582 } 583 584 MachineBasicBlock *Mips16TargetLowering::emitSelT16 585 (unsigned Opc1, unsigned Opc2, 586 MachineInstr *MI, MachineBasicBlock *BB) const { 587 if (DontExpandCondPseudos16) 588 return BB; 589 const TargetInstrInfo *TII = 590 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 591 DebugLoc DL = MI->getDebugLoc(); 592 // To "insert" a SELECT_CC instruction, we actually have to insert the 593 // diamond control-flow pattern. The incoming instruction knows the 594 // destination vreg to set, the condition code register to branch on, the 595 // true/false values to select between, and a branch opcode to use. 596 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 597 MachineFunction::iterator It = BB; 598 ++It; 599 600 // thisMBB: 601 // ... 602 // TrueVal = ... 603 // setcc r1, r2, r3 604 // bNE r1, r0, copy1MBB 605 // fallthrough --> copy0MBB 606 MachineBasicBlock *thisMBB = BB; 607 MachineFunction *F = BB->getParent(); 608 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 609 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 610 F->insert(It, copy0MBB); 611 F->insert(It, sinkMBB); 612 613 // Transfer the remainder of BB and its successor edges to sinkMBB. 614 sinkMBB->splice(sinkMBB->begin(), BB, 615 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 616 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 617 618 // Next, add the true and fallthrough blocks as its successors. 619 BB->addSuccessor(copy0MBB); 620 BB->addSuccessor(sinkMBB); 621 622 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 623 .addReg(MI->getOperand(4).getReg()); 624 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 625 626 // copy0MBB: 627 // %FalseValue = ... 628 // # fallthrough to sinkMBB 629 BB = copy0MBB; 630 631 // Update machine-CFG edges 632 BB->addSuccessor(sinkMBB); 633 634 // sinkMBB: 635 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 636 // ... 637 BB = sinkMBB; 638 639 BuildMI(*BB, BB->begin(), DL, 640 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 641 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 642 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 643 644 MI->eraseFromParent(); // The pseudo instruction is gone now. 645 return BB; 646 647 } 648 649 MachineBasicBlock *Mips16TargetLowering::emitSeliT16 650 (unsigned Opc1, unsigned Opc2, 651 MachineInstr *MI, MachineBasicBlock *BB) const { 652 if (DontExpandCondPseudos16) 653 return BB; 654 const TargetInstrInfo *TII = 655 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 656 DebugLoc DL = MI->getDebugLoc(); 657 // To "insert" a SELECT_CC instruction, we actually have to insert the 658 // diamond control-flow pattern. The incoming instruction knows the 659 // destination vreg to set, the condition code register to branch on, the 660 // true/false values to select between, and a branch opcode to use. 661 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 662 MachineFunction::iterator It = BB; 663 ++It; 664 665 // thisMBB: 666 // ... 667 // TrueVal = ... 668 // setcc r1, r2, r3 669 // bNE r1, r0, copy1MBB 670 // fallthrough --> copy0MBB 671 MachineBasicBlock *thisMBB = BB; 672 MachineFunction *F = BB->getParent(); 673 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 674 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 675 F->insert(It, copy0MBB); 676 F->insert(It, sinkMBB); 677 678 // Transfer the remainder of BB and its successor edges to sinkMBB. 679 sinkMBB->splice(sinkMBB->begin(), BB, 680 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 681 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 682 683 // Next, add the true and fallthrough blocks as its successors. 684 BB->addSuccessor(copy0MBB); 685 BB->addSuccessor(sinkMBB); 686 687 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 688 .addImm(MI->getOperand(4).getImm()); 689 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 690 691 // copy0MBB: 692 // %FalseValue = ... 693 // # fallthrough to sinkMBB 694 BB = copy0MBB; 695 696 // Update machine-CFG edges 697 BB->addSuccessor(sinkMBB); 698 699 // sinkMBB: 700 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 701 // ... 702 BB = sinkMBB; 703 704 BuildMI(*BB, BB->begin(), DL, 705 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 706 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 707 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 708 709 MI->eraseFromParent(); // The pseudo instruction is gone now. 710 return BB; 711 712 } 713 714 MachineBasicBlock 715 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, 716 MachineInstr *MI, 717 MachineBasicBlock *BB) const { 718 if (DontExpandCondPseudos16) 719 return BB; 720 const TargetInstrInfo *TII = 721 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 722 unsigned regX = MI->getOperand(0).getReg(); 723 unsigned regY = MI->getOperand(1).getReg(); 724 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 725 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 726 .addReg(regY); 727 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 728 MI->eraseFromParent(); // The pseudo instruction is gone now. 729 return BB; 730 } 731 732 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( 733 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, 734 MachineInstr *MI, MachineBasicBlock *BB) const { 735 if (DontExpandCondPseudos16) 736 return BB; 737 const TargetInstrInfo *TII = 738 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 739 unsigned regX = MI->getOperand(0).getReg(); 740 int64_t imm = MI->getOperand(1).getImm(); 741 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 742 unsigned CmpOpc; 743 if (isUInt<8>(imm)) 744 CmpOpc = CmpiOpc; 745 else if ((!ImmSigned && isUInt<16>(imm)) || 746 (ImmSigned && isInt<16>(imm))) 747 CmpOpc = CmpiXOpc; 748 else 749 llvm_unreachable("immediate field not usable"); 750 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 751 .addImm(imm); 752 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 753 MI->eraseFromParent(); // The pseudo instruction is gone now. 754 return BB; 755 } 756 757 static unsigned Mips16WhichOp8uOr16simm 758 (unsigned shortOp, unsigned longOp, int64_t Imm) { 759 if (isUInt<8>(Imm)) 760 return shortOp; 761 else if (isInt<16>(Imm)) 762 return longOp; 763 else 764 llvm_unreachable("immediate field not usable"); 765 } 766 767 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins( 768 unsigned SltOpc, 769 MachineInstr *MI, MachineBasicBlock *BB) const { 770 if (DontExpandCondPseudos16) 771 return BB; 772 const TargetInstrInfo *TII = 773 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 774 unsigned CC = MI->getOperand(0).getReg(); 775 unsigned regX = MI->getOperand(1).getReg(); 776 unsigned regY = MI->getOperand(2).getReg(); 777 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(SltOpc)).addReg(regX).addReg( 778 regY); 779 BuildMI(*BB, MI, MI->getDebugLoc(), 780 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 781 MI->eraseFromParent(); // The pseudo instruction is gone now. 782 return BB; 783 } 784 785 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins( 786 unsigned SltiOpc, unsigned SltiXOpc, 787 MachineInstr *MI, MachineBasicBlock *BB )const { 788 if (DontExpandCondPseudos16) 789 return BB; 790 const TargetInstrInfo *TII = 791 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 792 unsigned CC = MI->getOperand(0).getReg(); 793 unsigned regX = MI->getOperand(1).getReg(); 794 int64_t Imm = MI->getOperand(2).getImm(); 795 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm); 796 BuildMI(*BB, MI, MI->getDebugLoc(), 797 TII->get(SltOpc)).addReg(regX).addImm(Imm); 798 BuildMI(*BB, MI, MI->getDebugLoc(), 799 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 800 MI->eraseFromParent(); // The pseudo instruction is gone now. 801 return BB; 802 803 } 804