1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Subclass of MipsTargetLowering specialized for mips16. 11 // 12 //===----------------------------------------------------------------------===// 13 #define DEBUG_TYPE "mips-lower" 14 #include "Mips16ISelLowering.h" 15 #include "MCTargetDesc/MipsBaseInfo.h" 16 #include "MipsRegisterInfo.h" 17 #include "MipsTargetMachine.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/Support/CommandLine.h" 20 #include "llvm/Target/TargetInstrInfo.h" 21 22 using namespace llvm; 23 24 static cl::opt<bool> DontExpandCondPseudos16( 25 "mips16-dont-expand-cond-pseudo", 26 cl::init(false), 27 cl::desc("Dont expand conditional move related " 28 "pseudos for Mips 16"), 29 cl::Hidden); 30 31 namespace { 32 struct Mips16Libcall { 33 RTLIB::Libcall Libcall; 34 const char *Name; 35 36 bool operator<(const Mips16Libcall &RHS) const { 37 return std::strcmp(Name, RHS.Name) < 0; 38 } 39 }; 40 41 struct Mips16IntrinsicHelperType{ 42 const char* Name; 43 const char* Helper; 44 45 bool operator<(const Mips16IntrinsicHelperType &RHS) const { 46 return std::strcmp(Name, RHS.Name) < 0; 47 } 48 bool operator==(const Mips16IntrinsicHelperType &RHS) const { 49 return std::strcmp(Name, RHS.Name) == 0; 50 } 51 }; 52 } 53 54 // Libcalls for which no helper is generated. Sorted by name for binary search. 55 static const Mips16Libcall HardFloatLibCalls[] = { 56 { RTLIB::ADD_F64, "__mips16_adddf3" }, 57 { RTLIB::ADD_F32, "__mips16_addsf3" }, 58 { RTLIB::DIV_F64, "__mips16_divdf3" }, 59 { RTLIB::DIV_F32, "__mips16_divsf3" }, 60 { RTLIB::OEQ_F64, "__mips16_eqdf2" }, 61 { RTLIB::OEQ_F32, "__mips16_eqsf2" }, 62 { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" }, 63 { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" }, 64 { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" }, 65 { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" }, 66 { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" }, 67 { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" }, 68 { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" }, 69 { RTLIB::OGE_F64, "__mips16_gedf2" }, 70 { RTLIB::OGE_F32, "__mips16_gesf2" }, 71 { RTLIB::OGT_F64, "__mips16_gtdf2" }, 72 { RTLIB::OGT_F32, "__mips16_gtsf2" }, 73 { RTLIB::OLE_F64, "__mips16_ledf2" }, 74 { RTLIB::OLE_F32, "__mips16_lesf2" }, 75 { RTLIB::OLT_F64, "__mips16_ltdf2" }, 76 { RTLIB::OLT_F32, "__mips16_ltsf2" }, 77 { RTLIB::MUL_F64, "__mips16_muldf3" }, 78 { RTLIB::MUL_F32, "__mips16_mulsf3" }, 79 { RTLIB::UNE_F64, "__mips16_nedf2" }, 80 { RTLIB::UNE_F32, "__mips16_nesf2" }, 81 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall. 82 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall. 83 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall. 84 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall. 85 { RTLIB::SUB_F64, "__mips16_subdf3" }, 86 { RTLIB::SUB_F32, "__mips16_subsf3" }, 87 { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" }, 88 { RTLIB::UO_F64, "__mips16_unorddf2" }, 89 { RTLIB::UO_F32, "__mips16_unordsf2" } 90 }; 91 92 static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = { 93 {"__fixunsdfsi", "__mips16_call_stub_2" }, 94 {"ceil", "__mips16_call_stub_df_2"}, 95 {"ceilf", "__mips16_call_stub_sf_1"}, 96 {"copysign", "__mips16_call_stub_df_10"}, 97 {"copysignf", "__mips16_call_stub_sf_5"}, 98 {"cos", "__mips16_call_stub_df_2"}, 99 {"cosf", "__mips16_call_stub_sf_1"}, 100 {"exp2", "__mips16_call_stub_df_2"}, 101 {"exp2f", "__mips16_call_stub_sf_1"}, 102 {"floor", "__mips16_call_stub_df_2"}, 103 {"floorf", "__mips16_call_stub_sf_1"}, 104 {"log2", "__mips16_call_stub_df_2"}, 105 {"log2f", "__mips16_call_stub_sf_1"}, 106 {"nearbyint", "__mips16_call_stub_df_2"}, 107 {"nearbyintf", "__mips16_call_stub_sf_1"}, 108 {"rint", "__mips16_call_stub_df_2"}, 109 {"rintf", "__mips16_call_stub_sf_1"}, 110 {"sin", "__mips16_call_stub_df_2"}, 111 {"sinf", "__mips16_call_stub_sf_1"}, 112 {"sqrt", "__mips16_call_stub_df_2"}, 113 {"sqrtf", "__mips16_call_stub_sf_1"}, 114 {"trunc", "__mips16_call_stub_df_2"}, 115 {"truncf", "__mips16_call_stub_sf_1"}, 116 }; 117 118 Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM) 119 : MipsTargetLowering(TM) { 120 // 121 // set up as if mips32 and then revert so we can test the mechanism 122 // for switching 123 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 124 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 125 computeRegisterProperties(); 126 clearRegisterClasses(); 127 128 // Set up the register classes 129 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 130 131 if (Subtarget->inMips16HardFloat()) 132 setMips16HardFloatLibCalls(); 133 134 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 135 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 136 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 137 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 138 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 139 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 140 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 141 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 142 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 143 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 144 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 145 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 146 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 147 148 setOperationAction(ISD::ROTR, MVT::i32, Expand); 149 setOperationAction(ISD::ROTR, MVT::i64, Expand); 150 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 151 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 152 153 computeRegisterProperties(); 154 } 155 156 const MipsTargetLowering * 157 llvm::createMips16TargetLowering(MipsTargetMachine &TM) { 158 return new Mips16TargetLowering(TM); 159 } 160 161 bool 162 Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 163 return false; 164 } 165 166 MachineBasicBlock * 167 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 168 MachineBasicBlock *BB) const { 169 switch (MI->getOpcode()) { 170 default: 171 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 172 case Mips::SelBeqZ: 173 return emitSel16(Mips::BeqzRxImm16, MI, BB); 174 case Mips::SelBneZ: 175 return emitSel16(Mips::BnezRxImm16, MI, BB); 176 case Mips::SelTBteqZCmpi: 177 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB); 178 case Mips::SelTBteqZSlti: 179 return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB); 180 case Mips::SelTBteqZSltiu: 181 return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB); 182 case Mips::SelTBtneZCmpi: 183 return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB); 184 case Mips::SelTBtneZSlti: 185 return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB); 186 case Mips::SelTBtneZSltiu: 187 return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB); 188 case Mips::SelTBteqZCmp: 189 return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB); 190 case Mips::SelTBteqZSlt: 191 return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB); 192 case Mips::SelTBteqZSltu: 193 return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB); 194 case Mips::SelTBtneZCmp: 195 return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB); 196 case Mips::SelTBtneZSlt: 197 return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB); 198 case Mips::SelTBtneZSltu: 199 return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB); 200 case Mips::BteqzT8CmpX16: 201 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB); 202 case Mips::BteqzT8SltX16: 203 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB); 204 case Mips::BteqzT8SltuX16: 205 // TBD: figure out a way to get this or remove the instruction 206 // altogether. 207 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB); 208 case Mips::BtnezT8CmpX16: 209 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB); 210 case Mips::BtnezT8SltX16: 211 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB); 212 case Mips::BtnezT8SltuX16: 213 // TBD: figure out a way to get this or remove the instruction 214 // altogether. 215 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB); 216 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins( 217 Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 218 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins( 219 Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 220 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins( 221 Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 222 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins( 223 Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 224 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins( 225 Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 226 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins( 227 Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 228 break; 229 case Mips::SltCCRxRy16: 230 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB); 231 break; 232 case Mips::SltiCCRxImmX16: 233 return emitFEXT_CCRXI16_ins 234 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); 235 case Mips::SltiuCCRxImmX16: 236 return emitFEXT_CCRXI16_ins 237 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB); 238 case Mips::SltuCCRxRy16: 239 return emitFEXT_CCRX16_ins 240 (Mips::SltuRxRy16, MI, BB); 241 } 242 } 243 244 bool Mips16TargetLowering:: 245 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 246 unsigned NextStackOffset, 247 const MipsFunctionInfo& FI) const { 248 // No tail call optimization for mips16. 249 return false; 250 } 251 252 void Mips16TargetLowering::setMips16HardFloatLibCalls() { 253 for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) { 254 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) && 255 "Array not sorted!"); 256 if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL) 257 setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name); 258 } 259 260 setLibcallName(RTLIB::O_F64, "__mips16_unorddf2"); 261 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2"); 262 } 263 264 // 265 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much 266 // cleaner way to do all of this but it will have to wait until the traditional 267 // gcc mechanism is completed. 268 // 269 // For Pic, in order for Mips16 code to call Mips32 code which according the abi 270 // have either arguments or returned values placed in floating point registers, 271 // we use a set of helper functions. (This includes functions which return type 272 // complex which on Mips are returned in a pair of floating point registers). 273 // 274 // This is an encoding that we inherited from gcc. 275 // In Mips traditional O32, N32 ABI, floating point numbers are passed in 276 // floating point argument registers 1,2 only when the first and optionally 277 // the second arguments are float (sf) or double (df). 278 // For Mips16 we are only concerned with the situations where floating point 279 // arguments are being passed in floating point registers by the ABI, because 280 // Mips16 mode code cannot execute floating point instructions to load those 281 // values and hence helper functions are needed. 282 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df) 283 // the helper function suffixs for these are: 284 // 0, 1, 5, 9, 2, 6, 10 285 // this suffix can then be calculated as follows: 286 // for a given argument Arg: 287 // Arg1x, Arg2x = 1 : Arg is sf 288 // 2 : Arg is df 289 // 0: Arg is neither sf or df 290 // So this stub is the string for number Arg1x + Arg2x*4. 291 // However not all numbers between 0 and 10 are possible, we check anyway and 292 // assert if the impossible exists. 293 // 294 295 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber 296 (ArgListTy &Args) const { 297 unsigned int resultNum = 0; 298 if (Args.size() >= 1) { 299 Type *t = Args[0].Ty; 300 if (t->isFloatTy()) { 301 resultNum = 1; 302 } 303 else if (t->isDoubleTy()) { 304 resultNum = 2; 305 } 306 } 307 if (resultNum) { 308 if (Args.size() >=2) { 309 Type *t = Args[1].Ty; 310 if (t->isFloatTy()) { 311 resultNum += 4; 312 } 313 else if (t->isDoubleTy()) { 314 resultNum += 8; 315 } 316 } 317 } 318 return resultNum; 319 } 320 321 // 322 // prefixs are attached to stub numbers depending on the return type . 323 // return type: float sf_ 324 // double df_ 325 // single complex sc_ 326 // double complext dc_ 327 // others NO PREFIX 328 // 329 // 330 // The full name of a helper function is__mips16_call_stub + 331 // return type dependent prefix + stub number 332 // 333 // 334 // This is something that probably should be in a different source file and 335 // perhaps done differently but my main purpose is to not waste runtime 336 // on something that we can enumerate in the source. Another possibility is 337 // to have a python script to generate these mapping tables. This will do 338 // for now. There are a whole series of helper function mapping arrays, one 339 // for each return type class as outlined above. There there are 11 possible 340 // entries. Ones with 0 are ones which should never be selected 341 // 342 // All the arrays are similar except for ones which return neither 343 // sf, df, sc, dc, in which only care about ones which have sf or df as a 344 // first parameter. 345 // 346 #define P_ "__mips16_call_stub_" 347 #define MAX_STUB_NUMBER 10 348 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10" 349 #define T P "0" , T1 350 #define P P_ 351 static char const * vMips16Helper[MAX_STUB_NUMBER+1] = 352 {0, T1 }; 353 #undef P 354 #define P P_ "sf_" 355 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] = 356 { T }; 357 #undef P 358 #define P P_ "df_" 359 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] = 360 { T }; 361 #undef P 362 #define P P_ "sc_" 363 static char const * scMips16Helper[MAX_STUB_NUMBER+1] = 364 { T }; 365 #undef P 366 #define P P_ "dc_" 367 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] = 368 { T }; 369 #undef P 370 #undef P_ 371 372 373 const char* Mips16TargetLowering:: 374 getMips16HelperFunction 375 (Type* RetTy, ArgListTy &Args, bool &needHelper) const { 376 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args); 377 #ifndef NDEBUG 378 const unsigned int maxStubNum = 10; 379 assert(stubNum <= maxStubNum); 380 const bool validStubNum[maxStubNum+1] = 381 {true, true, true, false, false, true, true, false, false, true, true}; 382 assert(validStubNum[stubNum]); 383 #endif 384 const char *result; 385 if (RetTy->isFloatTy()) { 386 result = sfMips16Helper[stubNum]; 387 } 388 else if (RetTy ->isDoubleTy()) { 389 result = dfMips16Helper[stubNum]; 390 } 391 else if (RetTy->isStructTy()) { 392 // check if it's complex 393 if (RetTy->getNumContainedTypes() == 2) { 394 if ((RetTy->getContainedType(0)->isFloatTy()) && 395 (RetTy->getContainedType(1)->isFloatTy())) { 396 result = scMips16Helper[stubNum]; 397 } 398 else if ((RetTy->getContainedType(0)->isDoubleTy()) && 399 (RetTy->getContainedType(1)->isDoubleTy())) { 400 result = dcMips16Helper[stubNum]; 401 } 402 else { 403 llvm_unreachable("Uncovered condition"); 404 } 405 } 406 else { 407 llvm_unreachable("Uncovered condition"); 408 } 409 } 410 else { 411 if (stubNum == 0) { 412 needHelper = false; 413 return ""; 414 } 415 result = vMips16Helper[stubNum]; 416 } 417 needHelper = true; 418 return result; 419 } 420 421 void Mips16TargetLowering:: 422 getOpndList(SmallVectorImpl<SDValue> &Ops, 423 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 424 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 425 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 426 SelectionDAG &DAG = CLI.DAG; 427 MachineFunction &MF = DAG.getMachineFunction(); 428 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 429 const char* Mips16HelperFunction = 0; 430 bool NeedMips16Helper = false; 431 432 if (Subtarget->inMips16HardFloat()) { 433 // 434 // currently we don't have symbols tagged with the mips16 or mips32 435 // qualifier so we will assume that we don't know what kind it is. 436 // and generate the helper 437 // 438 bool LookupHelper = true; 439 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) { 440 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() }; 441 442 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls), 443 Find)) 444 LookupHelper = false; 445 else { 446 Mips16IntrinsicHelperType IntrinsicFind = {S->getSymbol(), ""}; 447 // one more look at list of intrinsics 448 if (std::binary_search(Mips16IntrinsicHelper, 449 array_endof(Mips16IntrinsicHelper), 450 IntrinsicFind)) { 451 const Mips16IntrinsicHelperType *h =(std::find(Mips16IntrinsicHelper, 452 array_endof(Mips16IntrinsicHelper), 453 IntrinsicFind)); 454 Mips16HelperFunction = h->Helper; 455 NeedMips16Helper = true; 456 LookupHelper = false; 457 } 458 459 } 460 } else if (GlobalAddressSDNode *G = 461 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 462 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, 463 G->getGlobal()->getName().data() }; 464 465 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls), 466 Find)) 467 LookupHelper = false; 468 } 469 if (LookupHelper) Mips16HelperFunction = 470 getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper); 471 472 } 473 474 SDValue JumpTarget = Callee; 475 476 // T9 should contain the address of the callee function if 477 // -reloction-model=pic or it is an indirect call. 478 if (IsPICCall || !GlobalOrExternal) { 479 unsigned V0Reg = Mips::V0; 480 if (NeedMips16Helper) { 481 RegsToPass.push_front(std::make_pair(V0Reg, Callee)); 482 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy()); 483 ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget); 484 JumpTarget = getAddrGlobal(S, JumpTarget.getValueType(), DAG, 485 MipsII::MO_GOT, Chain, 486 FuncInfo->callPtrInfo(S->getSymbol())); 487 } else 488 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee)); 489 } 490 491 Ops.push_back(JumpTarget); 492 493 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 494 InternalLinkage, CLI, Callee, Chain); 495 } 496 497 MachineBasicBlock *Mips16TargetLowering:: 498 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { 499 if (DontExpandCondPseudos16) 500 return BB; 501 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 502 DebugLoc DL = MI->getDebugLoc(); 503 // To "insert" a SELECT_CC instruction, we actually have to insert the 504 // diamond control-flow pattern. The incoming instruction knows the 505 // destination vreg to set, the condition code register to branch on, the 506 // true/false values to select between, and a branch opcode to use. 507 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 508 MachineFunction::iterator It = BB; 509 ++It; 510 511 // thisMBB: 512 // ... 513 // TrueVal = ... 514 // setcc r1, r2, r3 515 // bNE r1, r0, copy1MBB 516 // fallthrough --> copy0MBB 517 MachineBasicBlock *thisMBB = BB; 518 MachineFunction *F = BB->getParent(); 519 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 520 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 521 F->insert(It, copy0MBB); 522 F->insert(It, sinkMBB); 523 524 // Transfer the remainder of BB and its successor edges to sinkMBB. 525 sinkMBB->splice(sinkMBB->begin(), BB, 526 llvm::next(MachineBasicBlock::iterator(MI)), 527 BB->end()); 528 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 529 530 // Next, add the true and fallthrough blocks as its successors. 531 BB->addSuccessor(copy0MBB); 532 BB->addSuccessor(sinkMBB); 533 534 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) 535 .addMBB(sinkMBB); 536 537 // copy0MBB: 538 // %FalseValue = ... 539 // # fallthrough to sinkMBB 540 BB = copy0MBB; 541 542 // Update machine-CFG edges 543 BB->addSuccessor(sinkMBB); 544 545 // sinkMBB: 546 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 547 // ... 548 BB = sinkMBB; 549 550 BuildMI(*BB, BB->begin(), DL, 551 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 552 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 553 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 554 555 MI->eraseFromParent(); // The pseudo instruction is gone now. 556 return BB; 557 } 558 559 MachineBasicBlock *Mips16TargetLowering::emitSelT16 560 (unsigned Opc1, unsigned Opc2, 561 MachineInstr *MI, MachineBasicBlock *BB) const { 562 if (DontExpandCondPseudos16) 563 return BB; 564 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 565 DebugLoc DL = MI->getDebugLoc(); 566 // To "insert" a SELECT_CC instruction, we actually have to insert the 567 // diamond control-flow pattern. The incoming instruction knows the 568 // destination vreg to set, the condition code register to branch on, the 569 // true/false values to select between, and a branch opcode to use. 570 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 571 MachineFunction::iterator It = BB; 572 ++It; 573 574 // thisMBB: 575 // ... 576 // TrueVal = ... 577 // setcc r1, r2, r3 578 // bNE r1, r0, copy1MBB 579 // fallthrough --> copy0MBB 580 MachineBasicBlock *thisMBB = BB; 581 MachineFunction *F = BB->getParent(); 582 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 583 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 584 F->insert(It, copy0MBB); 585 F->insert(It, sinkMBB); 586 587 // Transfer the remainder of BB and its successor edges to sinkMBB. 588 sinkMBB->splice(sinkMBB->begin(), BB, 589 llvm::next(MachineBasicBlock::iterator(MI)), 590 BB->end()); 591 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 592 593 // Next, add the true and fallthrough blocks as its successors. 594 BB->addSuccessor(copy0MBB); 595 BB->addSuccessor(sinkMBB); 596 597 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 598 .addReg(MI->getOperand(4).getReg()); 599 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 600 601 // copy0MBB: 602 // %FalseValue = ... 603 // # fallthrough to sinkMBB 604 BB = copy0MBB; 605 606 // Update machine-CFG edges 607 BB->addSuccessor(sinkMBB); 608 609 // sinkMBB: 610 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 611 // ... 612 BB = sinkMBB; 613 614 BuildMI(*BB, BB->begin(), DL, 615 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 616 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 617 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 618 619 MI->eraseFromParent(); // The pseudo instruction is gone now. 620 return BB; 621 622 } 623 624 MachineBasicBlock *Mips16TargetLowering::emitSeliT16 625 (unsigned Opc1, unsigned Opc2, 626 MachineInstr *MI, MachineBasicBlock *BB) const { 627 if (DontExpandCondPseudos16) 628 return BB; 629 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 630 DebugLoc DL = MI->getDebugLoc(); 631 // To "insert" a SELECT_CC instruction, we actually have to insert the 632 // diamond control-flow pattern. The incoming instruction knows the 633 // destination vreg to set, the condition code register to branch on, the 634 // true/false values to select between, and a branch opcode to use. 635 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 636 MachineFunction::iterator It = BB; 637 ++It; 638 639 // thisMBB: 640 // ... 641 // TrueVal = ... 642 // setcc r1, r2, r3 643 // bNE r1, r0, copy1MBB 644 // fallthrough --> copy0MBB 645 MachineBasicBlock *thisMBB = BB; 646 MachineFunction *F = BB->getParent(); 647 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 648 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 649 F->insert(It, copy0MBB); 650 F->insert(It, sinkMBB); 651 652 // Transfer the remainder of BB and its successor edges to sinkMBB. 653 sinkMBB->splice(sinkMBB->begin(), BB, 654 llvm::next(MachineBasicBlock::iterator(MI)), 655 BB->end()); 656 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 657 658 // Next, add the true and fallthrough blocks as its successors. 659 BB->addSuccessor(copy0MBB); 660 BB->addSuccessor(sinkMBB); 661 662 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 663 .addImm(MI->getOperand(4).getImm()); 664 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 665 666 // copy0MBB: 667 // %FalseValue = ... 668 // # fallthrough to sinkMBB 669 BB = copy0MBB; 670 671 // Update machine-CFG edges 672 BB->addSuccessor(sinkMBB); 673 674 // sinkMBB: 675 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 676 // ... 677 BB = sinkMBB; 678 679 BuildMI(*BB, BB->begin(), DL, 680 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 681 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 682 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 683 684 MI->eraseFromParent(); // The pseudo instruction is gone now. 685 return BB; 686 687 } 688 689 MachineBasicBlock 690 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, 691 MachineInstr *MI, 692 MachineBasicBlock *BB) const { 693 if (DontExpandCondPseudos16) 694 return BB; 695 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 696 unsigned regX = MI->getOperand(0).getReg(); 697 unsigned regY = MI->getOperand(1).getReg(); 698 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 699 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 700 .addReg(regY); 701 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 702 MI->eraseFromParent(); // The pseudo instruction is gone now. 703 return BB; 704 } 705 706 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( 707 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, 708 MachineInstr *MI, MachineBasicBlock *BB) const { 709 if (DontExpandCondPseudos16) 710 return BB; 711 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 712 unsigned regX = MI->getOperand(0).getReg(); 713 int64_t imm = MI->getOperand(1).getImm(); 714 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 715 unsigned CmpOpc; 716 if (isUInt<8>(imm)) 717 CmpOpc = CmpiOpc; 718 else if ((!ImmSigned && isUInt<16>(imm)) || 719 (ImmSigned && isInt<16>(imm))) 720 CmpOpc = CmpiXOpc; 721 else 722 llvm_unreachable("immediate field not usable"); 723 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 724 .addImm(imm); 725 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 726 MI->eraseFromParent(); // The pseudo instruction is gone now. 727 return BB; 728 } 729 730 static unsigned Mips16WhichOp8uOr16simm 731 (unsigned shortOp, unsigned longOp, int64_t Imm) { 732 if (isUInt<8>(Imm)) 733 return shortOp; 734 else if (isInt<16>(Imm)) 735 return longOp; 736 else 737 llvm_unreachable("immediate field not usable"); 738 } 739 740 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins( 741 unsigned SltOpc, 742 MachineInstr *MI, MachineBasicBlock *BB) const { 743 if (DontExpandCondPseudos16) 744 return BB; 745 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 746 unsigned CC = MI->getOperand(0).getReg(); 747 unsigned regX = MI->getOperand(1).getReg(); 748 unsigned regY = MI->getOperand(2).getReg(); 749 BuildMI(*BB, MI, MI->getDebugLoc(), 750 TII->get(SltOpc)).addReg(regX).addReg(regY); 751 BuildMI(*BB, MI, MI->getDebugLoc(), 752 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 753 MI->eraseFromParent(); // The pseudo instruction is gone now. 754 return BB; 755 } 756 757 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins( 758 unsigned SltiOpc, unsigned SltiXOpc, 759 MachineInstr *MI, MachineBasicBlock *BB )const { 760 if (DontExpandCondPseudos16) 761 return BB; 762 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 763 unsigned CC = MI->getOperand(0).getReg(); 764 unsigned regX = MI->getOperand(1).getReg(); 765 int64_t Imm = MI->getOperand(2).getImm(); 766 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm); 767 BuildMI(*BB, MI, MI->getDebugLoc(), 768 TII->get(SltOpc)).addReg(regX).addImm(Imm); 769 BuildMI(*BB, MI, MI->getDebugLoc(), 770 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 771 MI->eraseFromParent(); // The pseudo instruction is gone now. 772 return BB; 773 774 } 775