1 //===-- Mips16ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips16 ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Subclass of MipsDAGToDAGISel specialized for mips16.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Mips16ISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "Mips.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 #include "llvm/IR/CFG.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetMachine.h"
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "mips-isel"
37 
38 bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39   Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
40   if (!Subtarget->inMips16Mode())
41     return false;
42   return MipsDAGToDAGISel::runOnMachineFunction(MF);
43 }
44 /// Select multiply instructions.
45 std::pair<SDNode*, SDNode*>
46 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
47                                bool HasLo, bool HasHi) {
48   SDNode *Lo = nullptr, *Hi = nullptr;
49   SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
50                                        N->getOperand(1));
51   SDValue InFlag = SDValue(Mul, 0);
52 
53   if (HasLo) {
54     unsigned Opcode = Mips::Mflo16;
55     Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
56     InFlag = SDValue(Lo, 1);
57   }
58   if (HasHi) {
59     unsigned Opcode = Mips::Mfhi16;
60     Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
61   }
62   return std::make_pair(Lo, Hi);
63 }
64 
65 void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
66   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
67 
68   if (!MipsFI->globalBaseRegSet())
69     return;
70 
71   MachineBasicBlock &MBB = MF.front();
72   MachineBasicBlock::iterator I = MBB.begin();
73   MachineRegisterInfo &RegInfo = MF.getRegInfo();
74   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
75   DebugLoc DL;
76   unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
77   const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
78 
79   V0 = RegInfo.createVirtualRegister(RC);
80   V1 = RegInfo.createVirtualRegister(RC);
81   V2 = RegInfo.createVirtualRegister(RC);
82 
83   BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).
84     addReg(V1, RegState::Define).
85     addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI).
86     addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
87 
88   BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
89   BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
90     .addReg(V1).addReg(V2);
91 }
92 
93 // Insert instructions to initialize the Mips16 SP Alias register in the
94 // first MBB of the function.
95 //
96 void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) {
97   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
98 
99   if (!MipsFI->mips16SPAliasRegSet())
100     return;
101 
102   MachineBasicBlock &MBB = MF.front();
103   MachineBasicBlock::iterator I = MBB.begin();
104   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
105   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
106   unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
107 
108   BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
109     .addReg(Mips::SP);
110 }
111 
112 void Mips16DAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
113   initGlobalBaseReg(MF);
114   initMips16SPAliasReg(MF);
115 }
116 
117 /// getMips16SPAliasReg - Output the instructions required to put the
118 /// SP into a Mips16 accessible aliased register.
119 SDValue Mips16DAGToDAGISel::getMips16SPAliasReg() {
120   unsigned Mips16SPAliasReg =
121     MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg();
122   auto PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
123   return CurDAG->getRegister(Mips16SPAliasReg, PtrVT);
124 }
125 
126 void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
127   auto PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
128   SDValue AliasFPReg = CurDAG->getRegister(Mips::S0, PtrVT);
129   if (Parent) {
130     switch (Parent->getOpcode()) {
131       case ISD::LOAD: {
132         LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
133         switch (SD->getMemoryVT().getSizeInBits()) {
134         case 8:
135         case 16:
136           AliasReg = Subtarget->getFrameLowering()->hasFP(*MF)
137                          ? AliasFPReg
138                          : getMips16SPAliasReg();
139           return;
140         }
141         break;
142       }
143       case ISD::STORE: {
144         StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
145         switch (SD->getMemoryVT().getSizeInBits()) {
146         case 8:
147         case 16:
148           AliasReg = Subtarget->getFrameLowering()->hasFP(*MF)
149                          ? AliasFPReg
150                          : getMips16SPAliasReg();
151           return;
152         }
153         break;
154       }
155     }
156   }
157   AliasReg = CurDAG->getRegister(Mips::SP, PtrVT);
158   return;
159 
160 }
161 
162 bool Mips16DAGToDAGISel::selectAddr16(
163   SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
164   SDValue &Alias) {
165   SDLoc DL(Addr);
166   EVT ValTy = Addr.getValueType();
167 
168   Alias = CurDAG->getTargetConstant(0, DL, ValTy);
169 
170   // if Address is FI, get the TargetFrameIndex.
171   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
172     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
173     Offset = CurDAG->getTargetConstant(0, DL, ValTy);
174     getMips16SPRefReg(Parent, Alias);
175     return true;
176   }
177   // on PIC code Load GA
178   if (Addr.getOpcode() == MipsISD::Wrapper) {
179     Base   = Addr.getOperand(0);
180     Offset = Addr.getOperand(1);
181     return true;
182   }
183   if (TM.getRelocationModel() != Reloc::PIC_) {
184     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
185         Addr.getOpcode() == ISD::TargetGlobalAddress))
186       return false;
187   }
188   // Addresses of the form FI+const or FI|const
189   if (CurDAG->isBaseWithConstantOffset(Addr)) {
190     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
191     if (isInt<16>(CN->getSExtValue())) {
192 
193       // If the first operand is a FI, get the TargetFI Node
194       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
195                                   (Addr.getOperand(0))) {
196         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
197         getMips16SPRefReg(Parent, Alias);
198       }
199       else
200         Base = Addr.getOperand(0);
201 
202       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), DL, ValTy);
203       return true;
204     }
205   }
206   // Operand is a result from an ADD.
207   if (Addr.getOpcode() == ISD::ADD) {
208     // When loading from constant pools, load the lower address part in
209     // the instruction itself. Example, instead of:
210     //  lui $2, %hi($CPI1_0)
211     //  addiu $2, $2, %lo($CPI1_0)
212     //  lwc1 $f0, 0($2)
213     // Generate:
214     //  lui $2, %hi($CPI1_0)
215     //  lwc1 $f0, %lo($CPI1_0)($2)
216     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
217         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
218       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
219       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
220           isa<JumpTableSDNode>(Opnd0)) {
221         Base = Addr.getOperand(0);
222         Offset = Opnd0;
223         return true;
224       }
225     }
226 
227     // If an indexed floating point load/store can be emitted, return false.
228     const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
229 
230     if (LS) {
231       if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2())
232         return false;
233       if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2())
234         return false;
235     }
236   }
237   Base   = Addr;
238   Offset = CurDAG->getTargetConstant(0, DL, ValTy);
239   return true;
240 }
241 
242 /// Select instructions not customized! Used for
243 /// expanded, promoted and normal instructions
244 std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
245   unsigned Opcode = Node->getOpcode();
246   SDLoc DL(Node);
247 
248   ///
249   // Instruction Selection not handled by the auto-generated
250   // tablegen selection should be handled here.
251   ///
252   EVT NodeTy = Node->getValueType(0);
253   unsigned MultOpc;
254 
255   switch(Opcode) {
256   default: break;
257 
258   case ISD::SUBE:
259   case ISD::ADDE: {
260     SDValue InFlag = Node->getOperand(2), CmpLHS;
261     unsigned Opc = InFlag.getOpcode(); (void)Opc;
262     assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
263             (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
264            "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
265 
266     unsigned MOp;
267     if (Opcode == ISD::ADDE) {
268       CmpLHS = InFlag.getValue(0);
269       MOp = Mips::AdduRxRyRz16;
270     } else {
271       CmpLHS = InFlag.getOperand(0);
272       MOp = Mips::SubuRxRyRz16;
273     }
274 
275     SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
276 
277     SDValue LHS = Node->getOperand(0);
278     SDValue RHS = Node->getOperand(1);
279 
280     EVT VT = LHS.getValueType();
281 
282     unsigned Sltu_op = Mips::SltuRxRyRz16;
283     SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops);
284     unsigned Addu_op = Mips::AdduRxRyRz16;
285     SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
286                                               SDValue(Carry,0), RHS);
287 
288     SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
289                                           SDValue(AddCarry,0));
290     return std::make_pair(true, Result);
291   }
292 
293   /// Mul with two results
294   case ISD::SMUL_LOHI:
295   case ISD::UMUL_LOHI: {
296     MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
297     std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
298                                                   true, true);
299     if (!SDValue(Node, 0).use_empty())
300       ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
301 
302     if (!SDValue(Node, 1).use_empty())
303       ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
304 
305     return std::make_pair(true, nullptr);
306   }
307 
308   case ISD::MULHS:
309   case ISD::MULHU: {
310     MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
311     SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
312     return std::make_pair(true, Result);
313   }
314   }
315 
316   return std::make_pair(false, nullptr);
317 }
318 
319 FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
320   return new Mips16DAGToDAGISel(TM);
321 }
322