1 //===-- Mips16ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips16 ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Subclass of MipsDAGToDAGISel specialized for mips16.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mips-isel"
15 #include "Mips16ISelDAGToDAG.h"
16 #include "Mips.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsRegisterInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CFG.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 using namespace llvm;
37 
38 bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39   if (!Subtarget.inMips16Mode())
40     return false;
41   return MipsDAGToDAGISel::runOnMachineFunction(MF);
42 }
43 /// Select multiply instructions.
44 std::pair<SDNode*, SDNode*>
45 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty,
46                                bool HasLo, bool HasHi) {
47   SDNode *Lo = 0, *Hi = 0;
48   SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
49                                        N->getOperand(1));
50   SDValue InFlag = SDValue(Mul, 0);
51 
52   if (HasLo) {
53     unsigned Opcode = Mips::Mflo16;
54     Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
55     InFlag = SDValue(Lo, 1);
56   }
57   if (HasHi) {
58     unsigned Opcode = Mips::Mfhi16;
59     Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
60   }
61   return std::make_pair(Lo, Hi);
62 }
63 
64 void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
65   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
66 
67   if (!MipsFI->globalBaseRegSet())
68     return;
69 
70   MachineBasicBlock &MBB = MF.front();
71   MachineBasicBlock::iterator I = MBB.begin();
72   MachineRegisterInfo &RegInfo = MF.getRegInfo();
73   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
74   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
75   unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
76   const TargetRegisterClass *RC =
77     (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
78 
79   V0 = RegInfo.createVirtualRegister(RC);
80   V1 = RegInfo.createVirtualRegister(RC);
81   V2 = RegInfo.createVirtualRegister(RC);
82 
83   BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
84     .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
85   BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
86     .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
87   BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
88   BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
89     .addReg(V1).addReg(V2);
90 }
91 
92 // Insert instructions to initialize the Mips16 SP Alias register in the
93 // first MBB of the function.
94 //
95 void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) {
96   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
97 
98   if (!MipsFI->mips16SPAliasRegSet())
99     return;
100 
101   MachineBasicBlock &MBB = MF.front();
102   MachineBasicBlock::iterator I = MBB.begin();
103   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
104   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
105   unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
106 
107   BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
108     .addReg(Mips::SP);
109 }
110 
111 void Mips16DAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
112   initGlobalBaseReg(MF);
113   initMips16SPAliasReg(MF);
114 }
115 
116 /// getMips16SPAliasReg - Output the instructions required to put the
117 /// SP into a Mips16 accessible aliased register.
118 SDValue Mips16DAGToDAGISel::getMips16SPAliasReg() {
119   unsigned Mips16SPAliasReg =
120     MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg();
121   return CurDAG->getRegister(Mips16SPAliasReg, TLI.getPointerTy());
122 }
123 
124 void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
125   SDValue AliasFPReg = CurDAG->getRegister(Mips::S0, TLI.getPointerTy());
126   if (Parent) {
127     switch (Parent->getOpcode()) {
128       case ISD::LOAD: {
129         LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
130         switch (SD->getMemoryVT().getSizeInBits()) {
131         case 8:
132         case 16:
133           AliasReg = TM.getFrameLowering()->hasFP(*MF)?
134             AliasFPReg: getMips16SPAliasReg();
135           return;
136         }
137         break;
138       }
139       case ISD::STORE: {
140         StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
141         switch (SD->getMemoryVT().getSizeInBits()) {
142         case 8:
143         case 16:
144           AliasReg = TM.getFrameLowering()->hasFP(*MF)?
145             AliasFPReg: getMips16SPAliasReg();
146           return;
147         }
148         break;
149       }
150     }
151   }
152   AliasReg = CurDAG->getRegister(Mips::SP, TLI.getPointerTy());
153   return;
154 
155 }
156 
157 bool Mips16DAGToDAGISel::selectAddr16(
158   SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
159   SDValue &Alias) {
160   EVT ValTy = Addr.getValueType();
161 
162   Alias = CurDAG->getTargetConstant(0, ValTy);
163 
164   // if Address is FI, get the TargetFrameIndex.
165   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
166     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
167     Offset = CurDAG->getTargetConstant(0, ValTy);
168     getMips16SPRefReg(Parent, Alias);
169     return true;
170   }
171   // on PIC code Load GA
172   if (Addr.getOpcode() == MipsISD::Wrapper) {
173     Base   = Addr.getOperand(0);
174     Offset = Addr.getOperand(1);
175     return true;
176   }
177   if (TM.getRelocationModel() != Reloc::PIC_) {
178     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
179         Addr.getOpcode() == ISD::TargetGlobalAddress))
180       return false;
181   }
182   // Addresses of the form FI+const or FI|const
183   if (CurDAG->isBaseWithConstantOffset(Addr)) {
184     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
185     if (isInt<16>(CN->getSExtValue())) {
186 
187       // If the first operand is a FI, get the TargetFI Node
188       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
189                                   (Addr.getOperand(0))) {
190         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
191         getMips16SPRefReg(Parent, Alias);
192       }
193       else
194         Base = Addr.getOperand(0);
195 
196       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
197       return true;
198     }
199   }
200   // Operand is a result from an ADD.
201   if (Addr.getOpcode() == ISD::ADD) {
202     // When loading from constant pools, load the lower address part in
203     // the instruction itself. Example, instead of:
204     //  lui $2, %hi($CPI1_0)
205     //  addiu $2, $2, %lo($CPI1_0)
206     //  lwc1 $f0, 0($2)
207     // Generate:
208     //  lui $2, %hi($CPI1_0)
209     //  lwc1 $f0, %lo($CPI1_0)($2)
210     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
211         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
212       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
213       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
214           isa<JumpTableSDNode>(Opnd0)) {
215         Base = Addr.getOperand(0);
216         Offset = Opnd0;
217         return true;
218       }
219     }
220 
221     // If an indexed floating point load/store can be emitted, return false.
222     const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
223 
224     if (LS &&
225         (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
226         Subtarget.hasFPIdx())
227       return false;
228   }
229   Base   = Addr;
230   Offset = CurDAG->getTargetConstant(0, ValTy);
231   return true;
232 }
233 
234 /// Select instructions not customized! Used for
235 /// expanded, promoted and normal instructions
236 std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
237   unsigned Opcode = Node->getOpcode();
238   DebugLoc DL = Node->getDebugLoc();
239 
240   ///
241   // Instruction Selection not handled by the auto-generated
242   // tablegen selection should be handled here.
243   ///
244   EVT NodeTy = Node->getValueType(0);
245   unsigned MultOpc;
246 
247   switch(Opcode) {
248   default: break;
249 
250   case ISD::SUBE:
251   case ISD::ADDE: {
252     SDValue InFlag = Node->getOperand(2), CmpLHS;
253     unsigned Opc = InFlag.getOpcode(); (void)Opc;
254     assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
255             (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
256            "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
257 
258     unsigned MOp;
259     if (Opcode == ISD::ADDE) {
260       CmpLHS = InFlag.getValue(0);
261       MOp = Mips::AdduRxRyRz16;
262     } else {
263       CmpLHS = InFlag.getOperand(0);
264       MOp = Mips::SubuRxRyRz16;
265     }
266 
267     SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
268 
269     SDValue LHS = Node->getOperand(0);
270     SDValue RHS = Node->getOperand(1);
271 
272     EVT VT = LHS.getValueType();
273 
274     unsigned Sltu_op = Mips::SltuRxRyRz16;
275     SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops);
276     unsigned Addu_op = Mips::AdduRxRyRz16;
277     SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
278                                               SDValue(Carry,0), RHS);
279 
280     SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
281                                           SDValue(AddCarry,0));
282     return std::make_pair(true, Result);
283   }
284 
285   /// Mul with two results
286   case ISD::SMUL_LOHI:
287   case ISD::UMUL_LOHI: {
288     MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
289     std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
290                                                   true, true);
291     if (!SDValue(Node, 0).use_empty())
292       ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
293 
294     if (!SDValue(Node, 1).use_empty())
295       ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
296 
297     return std::make_pair(true, (SDNode*)NULL);
298   }
299 
300   case ISD::MULHS:
301   case ISD::MULHU: {
302     MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
303     SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
304     return std::make_pair(true, Result);
305   }
306   }
307 
308   return std::make_pair(false, (SDNode*)NULL);
309 }
310 
311 FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
312   return new Mips16DAGToDAGISel(TM);
313 }
314