1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the Mips target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18// The overall idea of the PredicateControl class is to chop the Predicates list
19// into subsets that are usually overridden independently. This allows
20// subclasses to partially override the predicates of their superclasses without
21// having to re-add all the existing predicates.
22class PredicateControl {
23  // Predicates for the encoding scheme in use such as HasStdEnc
24  list<Predicate> EncodingPredicates = [];
25  // Predicates for the GPR size such as IsGP64bit
26  list<Predicate> GPRPredicates = [];
27  // Predicates for the PTR size such as IsPTR64bit
28  list<Predicate> PTRPredicates = [];
29  // Predicates for the FGR size and layout such as IsFP64bit
30  list<Predicate> FGRPredicates = [];
31  // Predicates for the instruction group membership such as ISA's and ASE's
32  list<Predicate> InsnPredicates = [];
33  // Predicate for marking the instruction as usable in hard-float mode only.
34  list<Predicate> HardFloatPredicate = [];
35  // Predicates for anything else
36  list<Predicate> AdditionalPredicates = [];
37  list<Predicate> Predicates = !listconcat(EncodingPredicates,
38                                           GPRPredicates,
39                                           PTRPredicates,
40                                           FGRPredicates,
41                                           InsnPredicates,
42                                           HardFloatPredicate,
43                                           AdditionalPredicates);
44}
45
46// Like Requires<> but for the AdditionalPredicates list
47class AdditionalRequires<list<Predicate> preds> {
48  list<Predicate> AdditionalPredicates = preds;
49}
50
51//===----------------------------------------------------------------------===//
52// Register File, Calling Conv, Instruction Descriptions
53//===----------------------------------------------------------------------===//
54
55include "MipsRegisterInfo.td"
56include "MipsSchedule.td"
57include "MipsInstrInfo.td"
58include "MipsCallingConv.td"
59
60// Avoid forward declaration issues.
61include "MipsScheduleP5600.td"
62include "MipsScheduleGeneric.td"
63
64def MipsInstrInfo : InstrInfo;
65
66//===----------------------------------------------------------------------===//
67// Mips Subtarget features                                                    //
68//===----------------------------------------------------------------------===//
69
70def FeatureNoABICalls  : SubtargetFeature<"noabicalls", "NoABICalls", "true",
71                                "Disable SVR4-style position-independent code">;
72def FeaturePTR64Bit    : SubtargetFeature<"ptr64", "IsPTR64bit", "true",
73                                "Pointers are 64-bit wide">;
74def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
75                                "General Purpose Registers are 64-bit wide">;
76def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
77                                "Support 64-bit FP registers">;
78def FeatureFPXX        : SubtargetFeature<"fpxx", "IsFPXX", "true",
79                                "Support for FPXX">;
80def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
81                                "IEEE 754-2008 NaN encoding">;
82def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
83                                "true", "Only supports single precision float">;
84def FeatureSoftFloat   : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
85                                "Does not support floating point instructions">;
86def FeatureNoOddSPReg  : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
87                              "Disable odd numbered single-precision "
88                              "registers">;
89def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
90                                "true", "Enable vector FPU instructions">;
91def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
92                                "Mips I ISA Support [highly experimental]">;
93def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
94                                "Mips II ISA Support [highly experimental]",
95                                [FeatureMips1]>;
96def FeatureMips3_32    : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
97                                "Subset of MIPS-III that is also in MIPS32 "
98                                "[highly experimental]">;
99def FeatureMips3_32r2  : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
100                                "Subset of MIPS-III that is also in MIPS32r2 "
101                                "[highly experimental]">;
102def FeatureMips3       : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
103                                "MIPS III ISA Support [highly experimental]",
104                                [FeatureMips2, FeatureMips3_32,
105                                 FeatureMips3_32r2, FeatureGP64Bit,
106                                 FeatureFP64Bit]>;
107def FeatureMips4_32    : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
108                                "Subset of MIPS-IV that is also in MIPS32 "
109                                "[highly experimental]">;
110def FeatureMips4_32r2  : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
111                                "Subset of MIPS-IV that is also in MIPS32r2 "
112                                "[highly experimental]">;
113def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
114                                "Mips4", "MIPS IV ISA Support",
115                                [FeatureMips3, FeatureMips4_32,
116                                 FeatureMips4_32r2]>;
117def FeatureMips5_32r2  : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
118                                "Subset of MIPS-V that is also in MIPS32r2 "
119                                "[highly experimental]">;
120def FeatureMips5       : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
121                                "MIPS V ISA Support [highly experimental]",
122                                [FeatureMips4, FeatureMips5_32r2]>;
123def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
124                                "Mips32 ISA Support",
125                                [FeatureMips2, FeatureMips3_32,
126                                 FeatureMips4_32]>;
127def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
128                                "Mips32r2", "Mips32r2 ISA Support",
129                                [FeatureMips3_32r2, FeatureMips4_32r2,
130                                 FeatureMips5_32r2, FeatureMips32]>;
131def FeatureMips32r3    : SubtargetFeature<"mips32r3", "MipsArchVersion",
132                                "Mips32r3", "Mips32r3 ISA Support",
133                                [FeatureMips32r2]>;
134def FeatureMips32r5    : SubtargetFeature<"mips32r5", "MipsArchVersion",
135                                "Mips32r5", "Mips32r5 ISA Support",
136                                [FeatureMips32r3]>;
137def FeatureMips32r6    : SubtargetFeature<"mips32r6", "MipsArchVersion",
138                                "Mips32r6",
139                                "Mips32r6 ISA Support [experimental]",
140                                [FeatureMips32r5, FeatureFP64Bit,
141                                 FeatureNaN2008]>;
142def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
143                                "Mips64", "Mips64 ISA Support",
144                                [FeatureMips5, FeatureMips32]>;
145def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
146                                "Mips64r2", "Mips64r2 ISA Support",
147                                [FeatureMips64, FeatureMips32r2]>;
148def FeatureMips64r3    : SubtargetFeature<"mips64r3", "MipsArchVersion",
149                                "Mips64r3", "Mips64r3 ISA Support",
150                                [FeatureMips64r2, FeatureMips32r3]>;
151def FeatureMips64r5    : SubtargetFeature<"mips64r5", "MipsArchVersion",
152                                "Mips64r5", "Mips64r5 ISA Support",
153                                [FeatureMips64r3, FeatureMips32r5]>;
154def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
155                                "Mips64r6",
156                                "Mips64r6 ISA Support [experimental]",
157                                [FeatureMips32r6, FeatureMips64r5,
158                                 FeatureNaN2008]>;
159
160def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
161                                      "Mips16 mode">;
162
163def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
164def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
165                                    "Mips DSP-R2 ASE", [FeatureDSP]>;
166def FeatureDSPR3
167    : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
168                       [ FeatureDSP, FeatureDSPR2 ]>;
169
170def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
171
172def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
173
174def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
175                                         "microMips mode">;
176
177def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
178                                "true", "Octeon cnMIPS Support",
179                                [FeatureMips64r2]>;
180
181def FeatureUseTCCInDIV : SubtargetFeature<
182                               "use-tcc-in-div",
183                               "UseTCCInDIV", "false",
184                               "Force the assembler to use trapping">;
185
186//===----------------------------------------------------------------------===//
187// Mips processors supported.
188//===----------------------------------------------------------------------===//
189
190def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
191                                 "MipsSubtarget::CPU::P5600",
192                                 "The P5600 Processor", [FeatureMips32r5]>;
193
194class Proc<string Name, list<SubtargetFeature> Features>
195 : ProcessorModel<Name, MipsGenericModel, Features>;
196
197def : Proc<"mips1", [FeatureMips1]>;
198def : Proc<"mips2", [FeatureMips2]>;
199def : Proc<"mips32", [FeatureMips32]>;
200def : Proc<"mips32r2", [FeatureMips32r2]>;
201def : Proc<"mips32r3", [FeatureMips32r3]>;
202def : Proc<"mips32r5", [FeatureMips32r5]>;
203def : Proc<"mips32r6", [FeatureMips32r6]>;
204
205def : Proc<"mips3", [FeatureMips3]>;
206def : Proc<"mips4", [FeatureMips4]>;
207def : Proc<"mips5", [FeatureMips5]>;
208def : Proc<"mips64", [FeatureMips64]>;
209def : Proc<"mips64r2", [FeatureMips64r2]>;
210def : Proc<"mips64r3", [FeatureMips64r3]>;
211def : Proc<"mips64r5", [FeatureMips64r5]>;
212def : Proc<"mips64r6", [FeatureMips64r6]>;
213def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
214def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
215
216def MipsAsmParser : AsmParser {
217  let ShouldEmitMatchRegisterName = 0;
218}
219
220def MipsAsmParserVariant : AsmParserVariant {
221  int Variant = 0;
222
223  // Recognize hard coded registers.
224  string RegisterPrefix = "$";
225}
226
227def Mips : Target {
228  let InstructionSet = MipsInstrInfo;
229  let AssemblyParsers = [MipsAsmParser];
230  let AssemblyParserVariants = [MipsAsmParserVariant];
231}
232