1 //=== MicroMipsSizeReduction.cpp - MicroMips size reduction pass --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///\file
10 /// This pass is used to reduce the size of instructions where applicable.
11 ///
12 /// TODO: Implement microMIPS64 support.
13 /// TODO: Implement support for reducing into lwp/swp instruction.
14 //===----------------------------------------------------------------------===//
15 #include "Mips.h"
16 #include "MipsInstrInfo.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/Support/Debug.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "micromips-reduce-size"
25 
26 STATISTIC(NumReduced, "Number of 32-bit instructions reduced to 16-bit ones");
27 
28 namespace {
29 
30 /// Order of operands to transfer
31 // TODO: Will be extended when additional optimizations are added
32 enum OperandTransfer {
33   OT_NA,          ///< Not applicable
34   OT_OperandsAll, ///< Transfer all operands
35   OT_Operands02,  ///< Transfer operands 0 and 2
36   OT_Operand2,    ///< Transfer just operand 2
37   OT_OperandsXOR, ///< Transfer operands for XOR16
38 };
39 
40 /// Reduction type
41 // TODO: Will be extended when additional optimizations are added
42 enum ReduceType {
43   RT_OneInstr ///< Reduce one instruction into a smaller instruction
44 };
45 
46 // Information about immediate field restrictions
47 struct ImmField {
48   ImmField() : ImmFieldOperand(-1), Shift(0), LBound(0), HBound(0) {}
49   ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,
50            int8_t ImmFieldOperand)
51       : ImmFieldOperand(ImmFieldOperand), Shift(Shift), LBound(LBound),
52         HBound(HBound) {}
53   int8_t ImmFieldOperand; // Immediate operand, -1 if it does not exist
54   uint8_t Shift;          // Shift value
55   int16_t LBound;         // Low bound of the immediate operand
56   int16_t HBound;         // High bound of the immediate operand
57 };
58 
59 /// Information about operands
60 // TODO: Will be extended when additional optimizations are added
61 struct OpInfo {
62   OpInfo(enum OperandTransfer TransferOperands)
63       : TransferOperands(TransferOperands) {}
64   OpInfo() : TransferOperands(OT_NA) {}
65 
66   enum OperandTransfer
67       TransferOperands; ///< Operands to transfer to the new instruction
68 };
69 
70 // Information about opcodes
71 struct OpCodes {
72   OpCodes(unsigned WideOpc, unsigned NarrowOpc)
73       : WideOpc(WideOpc), NarrowOpc(NarrowOpc) {}
74 
75   unsigned WideOpc;   ///< Wide opcode
76   unsigned NarrowOpc; ///< Narrow opcode
77 };
78 
79 /// ReduceTable - A static table with information on mapping from wide
80 /// opcodes to narrow
81 struct ReduceEntry {
82 
83   enum ReduceType eRType; ///< Reduction type
84   bool (*ReduceFunction)(
85       MachineInstr *MI,
86       const ReduceEntry &Entry); ///< Pointer to reduce function
87   struct OpCodes Ops;            ///< All relevant OpCodes
88   struct OpInfo OpInf;           ///< Characteristics of operands
89   struct ImmField Imm;           ///< Characteristics of immediate field
90 
91   ReduceEntry(enum ReduceType RType, struct OpCodes Op,
92               bool (*F)(MachineInstr *MI, const ReduceEntry &Entry),
93               struct OpInfo OpInf, struct ImmField Imm)
94       : eRType(RType), ReduceFunction(F), Ops(Op), OpInf(OpInf), Imm(Imm) {}
95 
96   unsigned NarrowOpc() const { return Ops.NarrowOpc; }
97   unsigned WideOpc() const { return Ops.WideOpc; }
98   int16_t LBound() const { return Imm.LBound; }
99   int16_t HBound() const { return Imm.HBound; }
100   uint8_t Shift() const { return Imm.Shift; }
101   int8_t ImmField() const { return Imm.ImmFieldOperand; }
102   enum OperandTransfer TransferOperands() const {
103     return OpInf.TransferOperands;
104   }
105   enum ReduceType RType() const { return eRType; }
106 
107   // operator used by std::equal_range
108   bool operator<(const unsigned int r) const { return (WideOpc() < r); }
109 
110   // operator used by std::equal_range
111   friend bool operator<(const unsigned int r, const struct ReduceEntry &re) {
112     return (r < re.WideOpc());
113   }
114 };
115 
116 class MicroMipsSizeReduce : public MachineFunctionPass {
117 public:
118   static char ID;
119   MicroMipsSizeReduce();
120 
121   static const MipsInstrInfo *MipsII;
122   const MipsSubtarget *Subtarget;
123 
124   bool runOnMachineFunction(MachineFunction &MF) override;
125 
126   llvm::StringRef getPassName() const override {
127     return "microMIPS instruction size reduction pass";
128   }
129 
130 private:
131   /// Reduces width of instructions in the specified basic block.
132   bool ReduceMBB(MachineBasicBlock &MBB);
133 
134   /// Attempts to reduce MI, returns true on success.
135   bool ReduceMI(const MachineBasicBlock::instr_iterator &MII);
136 
137   // Attempts to reduce LW/SW instruction into LWSP/SWSP,
138   // returns true on success.
139   static bool ReduceXWtoXWSP(MachineInstr *MI, const ReduceEntry &Entry);
140 
141   // Attempts to reduce LBU/LHU instruction into LBU16/LHU16,
142   // returns true on success.
143   static bool ReduceLXUtoLXU16(MachineInstr *MI, const ReduceEntry &Entry);
144 
145   // Attempts to reduce SB/SH instruction into SB16/SH16,
146   // returns true on success.
147   static bool ReduceSXtoSX16(MachineInstr *MI, const ReduceEntry &Entry);
148 
149   // Attempts to reduce arithmetic instructions, returns true on success.
150   static bool ReduceArithmeticInstructions(MachineInstr *MI,
151                                            const ReduceEntry &Entry);
152 
153   // Attempts to reduce ADDIU into ADDIUSP instruction,
154   // returns true on success.
155   static bool ReduceADDIUToADDIUSP(MachineInstr *MI, const ReduceEntry &Entry);
156 
157   // Attempts to reduce ADDIU into ADDIUR1SP instruction,
158   // returns true on success.
159   static bool ReduceADDIUToADDIUR1SP(MachineInstr *MI,
160                                      const ReduceEntry &Entry);
161 
162   // Attempts to reduce XOR into XOR16 instruction,
163   // returns true on success.
164   static bool ReduceXORtoXOR16(MachineInstr *MI, const ReduceEntry &Entry);
165 
166   // Changes opcode of an instruction.
167   static bool ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry);
168 
169   // Table with transformation rules for each instruction.
170   static llvm::SmallVector<ReduceEntry, 16> ReduceTable;
171 };
172 
173 char MicroMipsSizeReduce::ID = 0;
174 const MipsInstrInfo *MicroMipsSizeReduce::MipsII;
175 
176 // This table must be sorted by WideOpc as a main criterion and
177 // ReduceType as a sub-criterion (when wide opcodes are the same).
178 llvm::SmallVector<ReduceEntry, 16> MicroMipsSizeReduce::ReduceTable = {
179 
180     // ReduceType, OpCodes, ReduceFunction,
181     // OpInfo(TransferOperands),
182     // ImmField(Shift, LBound, HBound, ImmFieldPosition)
183     {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
184      ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
185     {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
186      OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},
187     {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
188      ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
189     {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
190      ReduceADDIUToADDIUSP, OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},
191     {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
192      ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
193      ImmField(0, 0, 0, -1)},
194     {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
195      ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
196      ImmField(0, 0, 0, -1)},
197     {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
198      OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
199     {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
200      OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},
201     {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
202      ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},
203     {RT_OneInstr, OpCodes(Mips::LHu, Mips::LHU16_MM), ReduceLXUtoLXU16,
204      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
205     {RT_OneInstr, OpCodes(Mips::LHu_MM, Mips::LHU16_MM), ReduceLXUtoLXU16,
206      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
207     {RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,
208      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
209     {RT_OneInstr, OpCodes(Mips::LW_MM, Mips::LWSP_MM), ReduceXWtoXWSP,
210      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
211     {RT_OneInstr, OpCodes(Mips::SB, Mips::SB16_MM), ReduceSXtoSX16,
212      OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
213     {RT_OneInstr, OpCodes(Mips::SB_MM, Mips::SB16_MM), ReduceSXtoSX16,
214      OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},
215     {RT_OneInstr, OpCodes(Mips::SH, Mips::SH16_MM), ReduceSXtoSX16,
216      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
217     {RT_OneInstr, OpCodes(Mips::SH_MM, Mips::SH16_MM), ReduceSXtoSX16,
218      OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},
219     {RT_OneInstr, OpCodes(Mips::SUBu, Mips::SUBU16_MM),
220      ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
221      ImmField(0, 0, 0, -1)},
222     {RT_OneInstr, OpCodes(Mips::SUBu_MM, Mips::SUBU16_MM),
223      ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
224      ImmField(0, 0, 0, -1)},
225     {RT_OneInstr, OpCodes(Mips::SW, Mips::SWSP_MM), ReduceXWtoXWSP,
226      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
227     {RT_OneInstr, OpCodes(Mips::SW_MM, Mips::SWSP_MM), ReduceXWtoXWSP,
228      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
229     {RT_OneInstr, OpCodes(Mips::XOR, Mips::XOR16_MM), ReduceXORtoXOR16,
230      OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)},
231     {RT_OneInstr, OpCodes(Mips::XOR_MM, Mips::XOR16_MM), ReduceXORtoXOR16,
232      OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)}};
233 } // namespace
234 
235 // Returns true if the machine operand MO is register SP.
236 static bool IsSP(const MachineOperand &MO) {
237   if (MO.isReg() && ((MO.getReg() == Mips::SP)))
238     return true;
239   return false;
240 }
241 
242 // Returns true if the machine operand MO is register $16, $17, or $2-$7.
243 static bool isMMThreeBitGPRegister(const MachineOperand &MO) {
244   if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))
245     return true;
246   return false;
247 }
248 
249 // Returns true if the machine operand MO is register $0, $17, or $2-$7.
250 static bool isMMSourceRegister(const MachineOperand &MO) {
251   if (MO.isReg() && Mips::GPRMM16ZeroRegClass.contains(MO.getReg()))
252     return true;
253   return false;
254 }
255 
256 // Returns true if the operand Op is an immediate value
257 // and writes the immediate value into variable Imm.
258 static bool GetImm(MachineInstr *MI, unsigned Op, int64_t &Imm) {
259 
260   if (!MI->getOperand(Op).isImm())
261     return false;
262   Imm = MI->getOperand(Op).getImm();
263   return true;
264 }
265 
266 // Returns true if the value is a valid immediate for ADDIUSP.
267 static bool AddiuspImmValue(int64_t Value) {
268   int64_t Value2 = Value >> 2;
269   if (((Value & (int64_t)maskTrailingZeros<uint64_t>(2)) == Value) &&
270       ((Value2 >= 2 && Value2 <= 257) || (Value2 >= -258 && Value2 <= -3)))
271     return true;
272   return false;
273 }
274 
275 // Returns true if the variable Value has the number of least-significant zero
276 // bits equal to Shift and if the shifted value is between the bounds.
277 static bool InRange(int64_t Value, unsigned short Shift, int LBound,
278                     int HBound) {
279   int64_t Value2 = Value >> Shift;
280   if (((Value & (int64_t)maskTrailingZeros<uint64_t>(Shift)) == Value) &&
281       (Value2 >= LBound) && (Value2 < HBound))
282     return true;
283   return false;
284 }
285 
286 // Returns true if immediate operand is in range.
287 static bool ImmInRange(MachineInstr *MI, const ReduceEntry &Entry) {
288 
289   int64_t offset;
290 
291   if (!GetImm(MI, Entry.ImmField(), offset))
292     return false;
293 
294   if (!InRange(offset, Entry.Shift(), Entry.LBound(), Entry.HBound()))
295     return false;
296 
297   return true;
298 }
299 
300 MicroMipsSizeReduce::MicroMipsSizeReduce() : MachineFunctionPass(ID) {}
301 
302 bool MicroMipsSizeReduce::ReduceMI(
303     const MachineBasicBlock::instr_iterator &MII) {
304 
305   MachineInstr *MI = &*MII;
306   unsigned Opcode = MI->getOpcode();
307 
308   // Search the table.
309   llvm::SmallVector<ReduceEntry, 16>::const_iterator Start =
310       std::begin(ReduceTable);
311   llvm::SmallVector<ReduceEntry, 16>::const_iterator End =
312       std::end(ReduceTable);
313 
314   std::pair<llvm::SmallVector<ReduceEntry, 16>::const_iterator,
315             llvm::SmallVector<ReduceEntry, 16>::const_iterator>
316       Range = std::equal_range(Start, End, Opcode);
317 
318   if (Range.first == Range.second)
319     return false;
320 
321   for (llvm::SmallVector<ReduceEntry, 16>::const_iterator Entry = Range.first;
322        Entry != Range.second; ++Entry)
323     if (((*Entry).ReduceFunction)(&(*MII), *Entry))
324       return true;
325 
326   return false;
327 }
328 
329 bool MicroMipsSizeReduce::ReduceXWtoXWSP(MachineInstr *MI,
330                                          const ReduceEntry &Entry) {
331 
332   if (!ImmInRange(MI, Entry))
333     return false;
334 
335   if (!IsSP(MI->getOperand(1)))
336     return false;
337 
338   return ReplaceInstruction(MI, Entry);
339 }
340 
341 bool MicroMipsSizeReduce::ReduceArithmeticInstructions(
342     MachineInstr *MI, const ReduceEntry &Entry) {
343 
344   if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
345       !isMMThreeBitGPRegister(MI->getOperand(1)) ||
346       !isMMThreeBitGPRegister(MI->getOperand(2)))
347     return false;
348 
349   return ReplaceInstruction(MI, Entry);
350 }
351 
352 bool MicroMipsSizeReduce::ReduceADDIUToADDIUR1SP(MachineInstr *MI,
353                                                  const ReduceEntry &Entry) {
354 
355   if (!ImmInRange(MI, Entry))
356     return false;
357 
358   if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
359     return false;
360 
361   return ReplaceInstruction(MI, Entry);
362 }
363 
364 bool MicroMipsSizeReduce::ReduceADDIUToADDIUSP(MachineInstr *MI,
365                                                const ReduceEntry &Entry) {
366 
367   int64_t ImmValue;
368   if (!GetImm(MI, Entry.ImmField(), ImmValue))
369     return false;
370 
371   if (!AddiuspImmValue(ImmValue))
372     return false;
373 
374   if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
375     return false;
376 
377   return ReplaceInstruction(MI, Entry);
378 }
379 
380 bool MicroMipsSizeReduce::ReduceLXUtoLXU16(MachineInstr *MI,
381                                            const ReduceEntry &Entry) {
382 
383   if (!ImmInRange(MI, Entry))
384     return false;
385 
386   if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
387       !isMMThreeBitGPRegister(MI->getOperand(1)))
388     return false;
389 
390   return ReplaceInstruction(MI, Entry);
391 }
392 
393 bool MicroMipsSizeReduce::ReduceSXtoSX16(MachineInstr *MI,
394                                          const ReduceEntry &Entry) {
395 
396   if (!ImmInRange(MI, Entry))
397     return false;
398 
399   if (!isMMSourceRegister(MI->getOperand(0)) ||
400       !isMMThreeBitGPRegister(MI->getOperand(1)))
401     return false;
402 
403   return ReplaceInstruction(MI, Entry);
404 }
405 
406 bool MicroMipsSizeReduce::ReduceXORtoXOR16(MachineInstr *MI,
407                                            const ReduceEntry &Entry) {
408   if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
409       !isMMThreeBitGPRegister(MI->getOperand(1)) ||
410       !isMMThreeBitGPRegister(MI->getOperand(2)))
411     return false;
412 
413   if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
414       !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
415     return false;
416 
417   return ReplaceInstruction(MI, Entry);
418 }
419 
420 bool MicroMipsSizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
421   bool Modified = false;
422   MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
423                                     E = MBB.instr_end();
424   MachineBasicBlock::instr_iterator NextMII;
425 
426   // Iterate through the instructions in the basic block
427   for (; MII != E; MII = NextMII) {
428     NextMII = std::next(MII);
429     MachineInstr *MI = &*MII;
430 
431     // Don't reduce bundled instructions or pseudo operations
432     if (MI->isBundle() || MI->isTransient())
433       continue;
434 
435     // Try to reduce 32-bit instruction into 16-bit instruction
436     Modified |= ReduceMI(MII);
437   }
438 
439   return Modified;
440 }
441 
442 bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI,
443                                              const ReduceEntry &Entry) {
444 
445   enum OperandTransfer OpTransfer = Entry.TransferOperands();
446 
447   DEBUG(dbgs() << "Converting 32-bit: " << *MI);
448   ++NumReduced;
449 
450   if (OpTransfer == OT_OperandsAll) {
451     MI->setDesc(MipsII->get(Entry.NarrowOpc()));
452     DEBUG(dbgs() << "       to 16-bit: " << *MI);
453     return true;
454   } else {
455     MachineBasicBlock &MBB = *MI->getParent();
456     const MCInstrDesc &NewMCID = MipsII->get(Entry.NarrowOpc());
457     DebugLoc dl = MI->getDebugLoc();
458     MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
459     switch (OpTransfer) {
460     case OT_Operand2:
461       MIB.add(MI->getOperand(2));
462       break;
463     case OT_Operands02: {
464       MIB.add(MI->getOperand(0));
465       MIB.add(MI->getOperand(2));
466       break;
467     }
468     case OT_OperandsXOR: {
469       if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
470         MIB.add(MI->getOperand(0));
471         MIB.add(MI->getOperand(1));
472         MIB.add(MI->getOperand(2));
473       } else {
474         MIB.add(MI->getOperand(0));
475         MIB.add(MI->getOperand(2));
476         MIB.add(MI->getOperand(1));
477       }
478       break;
479     }
480     default:
481       llvm_unreachable("Unknown operand transfer!");
482     }
483 
484     // Transfer MI flags.
485     MIB.setMIFlags(MI->getFlags());
486 
487     DEBUG(dbgs() << "       to 16-bit: " << *MIB);
488     MBB.erase_instr(MI);
489     return true;
490   }
491   return false;
492 }
493 
494 bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) {
495 
496   Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
497 
498   // TODO: Add support for the subtarget microMIPS32R6.
499   if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() ||
500       Subtarget->hasMips32r6())
501     return false;
502 
503   MipsII = static_cast<const MipsInstrInfo *>(Subtarget->getInstrInfo());
504 
505   bool Modified = false;
506   MachineFunction::iterator I = MF.begin(), E = MF.end();
507 
508   for (; I != E; ++I)
509     Modified |= ReduceMBB(*I);
510   return Modified;
511 }
512 
513 /// Returns an instance of the MicroMips size reduction pass.
514 FunctionPass *llvm::createMicroMipsSizeReductionPass() {
515   return new MicroMipsSizeReduce();
516 }
517