1def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2
3def simm12 : Operand<i32> {
4  let DecoderMethod = "DecodeSimm12";
5}
6
7def mem_mm_12 : Operand<i32> {
8  let PrintMethod = "printMemOperand";
9  let MIOperandInfo = (ops GPR32, simm12);
10  let EncoderMethod = "getMemEncodingMMImm12";
11  let ParserMatchClass = MipsMemAsmOperand;
12  let OperandType = "OPERAND_MEMORY";
13}
14
15def jmptarget_mm : Operand<OtherVT> {
16  let EncoderMethod = "getJumpTargetOpValueMM";
17}
18
19def calltarget_mm : Operand<iPTR> {
20  let EncoderMethod = "getJumpTargetOpValueMM";
21}
22
23def brtarget_mm : Operand<OtherVT> {
24  let EncoderMethod = "getBranchTargetOpValueMM";
25  let OperandType   = "OPERAND_PCREL";
26  let DecoderMethod = "DecodeBranchTargetMM";
27}
28
29let canFoldAsLoad = 1 in
30class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
31                      Operand MemOpnd> :
32  InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
33         !strconcat(opstr, "\t$rt, $addr"),
34         [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
35         NoItinerary, FrmI> {
36  let DecoderMethod = "DecodeMemMMImm12";
37  string Constraints = "$src = $rt";
38}
39
40class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
41                       Operand MemOpnd>:
42  InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
43         !strconcat(opstr, "\t$rt, $addr"),
44         [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
45  let DecoderMethod = "DecodeMemMMImm12";
46}
47
48class LLBaseMM<string opstr, RegisterOperand RO> :
49  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
50         !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
51  let DecoderMethod = "DecodeMemMMImm12";
52  let mayLoad = 1;
53}
54
55class SCBaseMM<string opstr, RegisterOperand RO> :
56  InstSE<(outs), (ins RO:$rt, mem_mm_12:$addr),
57         !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
58  let DecoderMethod = "DecodeMemMMImm12";
59  let mayStore = 1;
60}
61
62class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
63             InstrItinClass Itin = NoItinerary> :
64  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
65         !strconcat(opstr, "\t$rt, $addr"),
66         [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
67  let DecoderMethod = "DecodeMemMMImm12";
68  let canFoldAsLoad = 1;
69  let mayLoad = 1;
70}
71
72let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
73  /// Arithmetic Instructions (ALU Immediate)
74  def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
75                 ADDI_FM_MM<0xc>;
76  def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
77                 ADDI_FM_MM<0x4>;
78  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
79                 SLTI_FM_MM<0x24>;
80  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
81                 SLTI_FM_MM<0x2c>;
82  def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
83                 ADDI_FM_MM<0x34>;
84  def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
85                 ADDI_FM_MM<0x14>;
86  def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
87                 ADDI_FM_MM<0x1c>;
88  def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
89
90  def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
91                     LW_FM_MM<0xc>;
92
93  /// Arithmetic Instructions (3-Operand, R-Type)
94  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
95  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
96  def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
97  def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
98  def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
99  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
100  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
101                 ADD_FM_MM<0, 0x390>;
102  def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
103                 ADD_FM_MM<0, 0x250>;
104  def OR_MM    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
105                 ADD_FM_MM<0, 0x290>;
106  def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
107                 ADD_FM_MM<0, 0x310>;
108  def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
109  def MULT_MM  : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
110                 MULT_FM_MM<0x22c>;
111  def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
112                 MULT_FM_MM<0x26c>;
113  def SDIV_MM  : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
114                 MULT_FM_MM<0x2ac>;
115  def UDIV_MM  : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
116                 MULT_FM_MM<0x2ec>;
117
118  /// Shift Instructions
119  def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
120                 SRA_FM_MM<0, 0>;
121  def SRL_MM   : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
122                 SRA_FM_MM<0x40, 0>;
123  def SRA_MM   : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
124                 SRA_FM_MM<0x80, 0>;
125  def SLLV_MM  : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
126                 SRLV_FM_MM<0x10, 0>;
127  def SRLV_MM  : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
128                 SRLV_FM_MM<0x50, 0>;
129  def SRAV_MM  : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
130                 SRLV_FM_MM<0x90, 0>;
131  def ROTR_MM  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
132                 SRA_FM_MM<0xc0, 0>;
133  def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
134                 SRLV_FM_MM<0xd0, 0>;
135
136  /// Load and Store Instructions - aligned
137  let DecoderMethod = "DecodeMemMMImm16" in {
138    def LB_MM  : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
139    def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
140    def LH_MM  : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
141    def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
142    def LW_MM  : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
143    def SB_MM  : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
144    def SH_MM  : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
145    def SW_MM  : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
146  }
147
148  def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
149
150  /// Load and Store Instructions - unaligned
151  def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
152               LWL_FM_MM<0x0>;
153  def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
154               LWL_FM_MM<0x1>;
155  def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
156               LWL_FM_MM<0x8>;
157  def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
158               LWL_FM_MM<0x9>;
159
160  /// Move Conditional
161  def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
162                  NoItinerary>, ADD_FM_MM<0, 0x58>;
163  def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
164                  NoItinerary>, ADD_FM_MM<0, 0x18>;
165  def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
166                  CMov_F_I_FM_MM<0x25>;
167  def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
168                  CMov_F_I_FM_MM<0x5>;
169
170  /// Move to/from HI/LO
171  def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
172                MTLO_FM_MM<0x0b5>;
173  def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
174                MTLO_FM_MM<0x0f5>;
175  def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
176                MFLO_FM_MM<0x035>;
177  def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
178                MFLO_FM_MM<0x075>;
179
180  /// Multiply Add/Sub Instructions
181  def MADD_MM  : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
182  def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
183  def MSUB_MM  : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
184  def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
185
186  /// Count Leading
187  def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>;
188  def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>;
189
190  /// Sign Ext In Register Instructions.
191  def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM_MM<0x0ac>;
192  def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM_MM<0x0ec>;
193
194  /// Word Swap Bytes Within Halfwords
195  def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>;
196
197  def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
198               EXT_FM_MM<0x2c>;
199  def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
200               EXT_FM_MM<0x0c>;
201
202  /// Jump Instructions
203  let DecoderMethod = "DecodeJumpTargetMM" in {
204    def J_MM        : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
205                      J_FM_MM<0x35>;
206    def JAL_MM      : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
207  }
208  def JR_MM   : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
209  def JALR_MM : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
210  def RET_MM : MMRel, RetBase<"ret", GPR32Opnd>, JR_FM_MM<0x3c>;
211
212  /// Branch Instructions
213  def BEQ_MM  : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
214                BEQ_FM_MM<0x25>;
215  def BNE_MM  : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
216                BEQ_FM_MM<0x2d>;
217  def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
218                BGEZ_FM_MM<0x2>;
219  def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
220                BGEZ_FM_MM<0x6>;
221  def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
222                BGEZ_FM_MM<0x4>;
223  def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
224                BGEZ_FM_MM<0x0>;
225  def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
226                  BGEZAL_FM_MM<0x03>;
227  def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
228                  BGEZAL_FM_MM<0x01>;
229
230  /// Control Instructions
231  def SYNC_MM    : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
232  def BREAK_MM   : MMRel, BRK_FT<"break">, BRK_FM_MM;
233  def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
234  def WAIT_MM    : MMRel, WAIT_FT<"wait">, WAIT_FM_MM;
235  def ERET_MM    : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
236  def DERET_MM   : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
237  def EI_MM      : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>;
238  def DI_MM      : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>;
239
240  /// Trap Instructions
241  def TEQ_MM  : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
242  def TGE_MM  : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
243  def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
244  def TLT_MM  : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
245  def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
246  def TNE_MM  : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
247
248  def TEQI_MM  : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
249  def TGEI_MM  : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
250  def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
251  def TLTI_MM  : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
252  def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
253  def TNEI_MM  : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
254
255  /// Load-linked, Store-conditional
256  def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
257  def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
258}
259