1//==- MicroMipsInstrFPU.td - microMIPS FPU Instruction Info -*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the microMIPS FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14let isCodeGenOnly = 1 in { 15def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 16 ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS; 17def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 18 ADDS_FM_MM<0, 0xf0>, ISA_MICROMIPS; 19def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 20 ADDS_FM_MM<0, 0xb0>, ISA_MICROMIPS; 21def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 22 ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS; 23 24def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>, 25 ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; 26def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>, 27 ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; 28def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>, 29 ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; 30def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, 31 ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; 32 33def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, 34 LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6; 35def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, 36 SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6; 37 38// FIXME: These instruction definitions are incorrect. They should be 64-bit 39// FPU only. 40def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, 41 LWXC1_FM_MM<0x148>, ISA_MICROMIPS32_NOT_MIPS32R6; 42def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, 43 SWXC1_FM_MM<0x188>, ISA_MICROMIPS32_NOT_MIPS32R6; 44 45def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, 46 CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 { 47 // FIXME: This is a required to work around the fact that these instructions 48 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 49 // fcc register set is used directly. 50 bits<3> fcc = 0; 51} 52 53def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, 54 CEQS_FM_MM<1>, ISA_MICROMIPS32_NOT_MIPS32R6 { 55 // FIXME: This is a required to work around the fact that these instructions 56 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 57 // fcc register set is used directly. 58 bits<3> fcc = 0; 59} 60 61} 62 63let DecoderNamespace = "MicroMips" in { 64 def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, 65 BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6; 66 def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>, 67 BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6; 68} 69 70let isCodeGenOnly = 1 in { 71def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 72 ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS; 73def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, 74 II_ROUND>, ROUND_W_FM_MM<0, 0xec>, 75 ISA_MICROMIPS; 76 77def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, 78 ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; 79def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 80 ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; 81def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, 82 ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; 83def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, 84 II_ROUND>, ROUND_W_FM_MM<1, 0xec>, 85 ISA_MICROMIPS, FGR_32; 86def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, 87 ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; 88 89def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D, 90 fsqrt>, ROUND_W_FM_MM<1, 0x28>, 91 ISA_MICROMIPS, FGR_32; 92 93def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 94 ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; 95def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 96 ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; 97 98def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 99 ABS_FM_MM<0, 0xd>, ISA_MICROMIPS; 100def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 101 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS; 102def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 103 ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS; 104def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 105 ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32; 106def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 107 ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32; 108def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 109 ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; 110def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 111 ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; 112 113def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>, 114 ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32; 115def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>, 116 ABS_FM_MM<1, 0x2d>, ISA_MICROMIPS, FGR_32; 117 118def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 119 ABS_FM_MM<1, 0x1>, ISA_MICROMIPS, FGR_32; 120 121def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, 122 II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, 123 ISA_MICROMIPS32_NOT_MIPS32R6; 124def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, 125 II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>, 126 ISA_MICROMIPS32_NOT_MIPS32R6; 127def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, 128 II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>, 129 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 130def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, 131 II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>, 132 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 133 134def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, 135 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>, 136 ISA_MICROMIPS32_NOT_MIPS32R6; 137def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, 138 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>, 139 ISA_MICROMIPS32_NOT_MIPS32R6; 140def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, 141 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>, 142 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 143def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, 144 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>, 145 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 146def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, 147 II_MFC1, bitconvert>, MFC1_FM_MM<0x80>, 148 ISA_MICROMIPS; 149def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, 150 II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, 151 ISA_MICROMIPS; 152 153def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 154 MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6; 155def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 156 MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6; 157def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 158 MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; 159def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 160 MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6; 161 162def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, 163 MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 164def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, 165 MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 166def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 167 MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 168def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 169 MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 170} 171 172def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, 173 II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, 174 ISA_MICROMIPS; 175def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, 176 FGR32Opnd, II_TRUNC>, 177 ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; 178def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 179 ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; 180def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, 181 fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS; 182def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 183 MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; 184def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 185 MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; 186 187let DecoderNamespace = "MicroMips" in { 188 def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, 189 MFC1_FM_MM<0x40>, ISA_MICROMIPS; 190 def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, 191 MFC1_FM_MM<0x60>, ISA_MICROMIPS; 192 def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, 193 II_RECIP_S>, 194 ROUND_W_FM_MM<0b0, 0b01001000>, ISA_MICROMIPS; 195 def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, 196 II_RECIP_D>, 197 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_32 { 198 let BaseOpcode = "RECIP_D32"; 199 } 200 let DecoderNamespace = "MicroMipsFP64" in 201 def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, 202 II_RECIP_D>, 203 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_64; 204 def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, 205 II_RECIP_S>, 206 ROUND_W_FM_MM<0b0, 0b00001000>; 207 def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, 208 II_RECIP_D>, 209 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_32 { 210 let BaseOpcode = "RSQRT_D32"; 211 } 212 let DecoderNamespace = "MicroMipsFP64" in 213 def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, 214 II_RECIP_D>, 215 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_64; 216} 217 218let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in { 219 def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>, 220 LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_32 { 221 let BaseOpcode = "LDC132"; 222 } 223 def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>, 224 LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_32; 225 def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>, 226 LW_FM_MM<0x27>, ISA_MICROMIPS; 227 def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>, 228 LW_FM_MM<0x26>, ISA_MICROMIPS; 229} 230 231multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt, 232 InstrItinClass itin> { 233 def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, 234 C_COND_FM_MM<fmt, 0> { 235 let BaseOpcode = "c.f."#NAME; 236 let isCommutable = 1; 237 } 238 def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, 239 C_COND_FM_MM<fmt, 1> { 240 let BaseOpcode = "c.un."#NAME; 241 let isCommutable = 1; 242 } 243 def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, 244 C_COND_FM_MM<fmt, 2> { 245 let BaseOpcode = "c.eq."#NAME; 246 let isCommutable = 1; 247 } 248 def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, 249 C_COND_FM_MM<fmt, 3> { 250 let BaseOpcode = "c.ueq."#NAME; 251 let isCommutable = 1; 252 } 253 def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, 254 C_COND_FM_MM<fmt, 4> { 255 let BaseOpcode = "c.olt."#NAME; 256 } 257 def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, 258 C_COND_FM_MM<fmt, 5> { 259 let BaseOpcode = "c.ult."#NAME; 260 } 261 def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, 262 C_COND_FM_MM<fmt, 6> { 263 let BaseOpcode = "c.ole."#NAME; 264 } 265 def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, 266 C_COND_FM_MM<fmt, 7> { 267 let BaseOpcode = "c.ule."#NAME; 268 } 269 def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, 270 C_COND_FM_MM<fmt, 8> { 271 let BaseOpcode = "c.sf."#NAME; 272 let isCommutable = 1; 273 } 274 def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, 275 C_COND_FM_MM<fmt, 9> { 276 let BaseOpcode = "c.ngle."#NAME; 277 } 278 def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, 279 C_COND_FM_MM<fmt, 10> { 280 let BaseOpcode = "c.seq."#NAME; 281 let isCommutable = 1; 282 } 283 def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, 284 C_COND_FM_MM<fmt, 11> { 285 let BaseOpcode = "c.ngl."#NAME; 286 } 287 def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, 288 C_COND_FM_MM<fmt, 12> { 289 let BaseOpcode = "c.lt."#NAME; 290 } 291 def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, 292 C_COND_FM_MM<fmt, 13> { 293 let BaseOpcode = "c.nge."#NAME; 294 } 295 def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, 296 C_COND_FM_MM<fmt, 14> { 297 let BaseOpcode = "c.le."#NAME; 298 } 299 def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, 300 C_COND_FM_MM<fmt, 15> { 301 let BaseOpcode = "c.ngt."#NAME; 302 } 303} 304 305defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>, 306 ISA_MICROMIPS32_NOT_MIPS32R6; 307defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, 308 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 309let DecoderNamespace = "Mips64" in 310 defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>, 311 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64; 312 313defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, 314 ISA_MICROMIPS32_NOT_MIPS32R6; 315defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, 316 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 317defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, 318 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64; 319 320defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">, 321 ISA_MICROMIPS32_NOT_MIPS32R6, HARDFLOAT; 322 323 324// To generate NMADD and NMSUB instructions when fneg node is present 325let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, 326 InMicroMips, NotMips32r6] in { 327 defm : NMADD_NMSUB<NMADD_S_MM, NMSUB_S_MM, FGR32Opnd>, 328 ISA_MICROMIPS32_NOT_MIPS32R6; 329 defm : NMADD_NMSUB<NMADD_D32_MM, NMSUB_D32_MM, AFGR64Opnd>, 330 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 331} 332 333//===----------------------------------------------------------------------===// 334// Floating Point Patterns 335//===----------------------------------------------------------------------===// 336 337// Patterns for loads/stores with a reg+imm operand. 338let AddedComplexity = 40 in { 339 def : LoadRegImmPat<LDC1_MM, f64, load>, ISA_MICROMIPS, FGR_32; 340 def : StoreRegImmPat<SDC1_MM, f64>, ISA_MICROMIPS, FGR_32; 341 def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS; 342 def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS; 343} 344