1//==- MicroMipsInstrFPU.td - microMIPS FPU Instruction Info -*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the microMIPS FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14let isCodeGenOnly = 1 in { 15def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 16 ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS; 17def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 18 ADDS_FM_MM<0, 0xf0>, ISA_MICROMIPS; 19def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 20 ADDS_FM_MM<0, 0xb0>, ISA_MICROMIPS; 21def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 22 ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS; 23 24def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>, 25 ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; 26def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>, 27 ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; 28def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>, 29 ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; 30def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, 31 ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; 32 33def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, 34 LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6; 35def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, 36 SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6; 37 38// FIXME: These instruction definitions are incorrect. They should be 64-bit 39// FPU only. 40def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, 41 LWXC1_FM_MM<0x148>, ISA_MICROMIPS32_NOT_MIPS32R6; 42def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, 43 SWXC1_FM_MM<0x188>, ISA_MICROMIPS32_NOT_MIPS32R6; 44 45def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, 46 CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 { 47 // FIXME: This is a required to work around the fact that these instructions 48 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 49 // fcc register set is used directly. 50 bits<3> fcc = 0; 51} 52 53def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, 54 CEQS_FM_MM<1>, ISA_MICROMIPS32_NOT_MIPS32R6 { 55 // FIXME: This is a required to work around the fact that these instructions 56 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 57 // fcc register set is used directly. 58 bits<3> fcc = 0; 59} 60 61} 62 63let DecoderNamespace = "MicroMips" in { 64 def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, 65 BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6; 66 def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>, 67 BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6; 68} 69 70let isCodeGenOnly = 1 in { 71def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 72 ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS; 73def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, 74 II_ROUND>, ROUND_W_FM_MM<0, 0xec>, 75 ISA_MICROMIPS; 76 77def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, 78 ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; 79def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 80 ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; 81def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, 82 ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; 83def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, 84 II_ROUND>, ROUND_W_FM_MM<1, 0xec>, 85 ISA_MICROMIPS, FGR_32; 86def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, 87 ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; 88 89def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D, 90 fsqrt>, ROUND_W_FM_MM<1, 0x28>, 91 ISA_MICROMIPS, FGR_32; 92 93def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 94 ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; 95def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 96 ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; 97 98} 99 100let DecoderNamespace = "MicroMips" in { 101 def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 102 ABS_FM_MM<0, 0xd>, ISA_MICROMIPS; 103 def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>, 104 ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32; 105} 106 107let isCodeGenOnly = 1 in { 108def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 109 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS; 110def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 111 ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS; 112def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 113 ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32; 114def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 115 ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32; 116def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 117 ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; 118def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 119 ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; 120 121def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>, 122 ABS_FM_MM<1, 0x2d>, ISA_MICROMIPS, FGR_32; 123 124def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 125 ABS_FM_MM<1, 0x1>, ISA_MICROMIPS, FGR_32; 126 127def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, 128 II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, 129 ISA_MICROMIPS32_NOT_MIPS32R6; 130def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, 131 II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>, 132 ISA_MICROMIPS32_NOT_MIPS32R6; 133def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, 134 II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>, 135 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 136def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, 137 II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>, 138 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 139 140def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, 141 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>, 142 ISA_MICROMIPS32_NOT_MIPS32R6; 143def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, 144 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>, 145 ISA_MICROMIPS32_NOT_MIPS32R6; 146def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, 147 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>, 148 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 149def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, 150 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>, 151 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 152def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, 153 II_MFC1, bitconvert>, MFC1_FM_MM<0x80>, 154 ISA_MICROMIPS; 155def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, 156 II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, 157 ISA_MICROMIPS; 158 159def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 160 MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6; 161def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 162 MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6; 163def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 164 MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; 165def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 166 MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6; 167 168def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, 169 MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 170def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, 171 MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 172def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 173 MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 174def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 175 MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 176} 177 178def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, 179 II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, 180 ISA_MICROMIPS; 181def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, 182 FGR32Opnd, II_TRUNC>, 183 ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; 184def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 185 ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; 186def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, 187 fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS; 188def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 189 MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; 190def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 191 MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; 192 193let DecoderNamespace = "MicroMips" in { 194 def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, 195 MFC1_FM_MM<0x40>, ISA_MICROMIPS; 196 def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, 197 MFC1_FM_MM<0x60>, ISA_MICROMIPS; 198 def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, 199 II_RECIP_S>, 200 ROUND_W_FM_MM<0b0, 0b01001000>, ISA_MICROMIPS; 201 def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, 202 II_RECIP_D>, 203 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_32 { 204 let BaseOpcode = "RECIP_D32"; 205 } 206 let DecoderNamespace = "MicroMipsFP64" in 207 def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, 208 II_RECIP_D>, 209 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_64; 210 def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, 211 II_RECIP_S>, 212 ROUND_W_FM_MM<0b0, 0b00001000>; 213 def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, 214 II_RECIP_D>, 215 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_32 { 216 let BaseOpcode = "RSQRT_D32"; 217 } 218 let DecoderNamespace = "MicroMipsFP64" in 219 def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, 220 II_RECIP_D>, 221 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_64; 222} 223 224let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in { 225 def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>, 226 LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_32 { 227 let BaseOpcode = "LDC132"; 228 } 229 def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>, 230 LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_32; 231 def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>, 232 LW_FM_MM<0x27>, ISA_MICROMIPS; 233 def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>, 234 LW_FM_MM<0x26>, ISA_MICROMIPS; 235} 236 237multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt, 238 InstrItinClass itin> { 239 def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, 240 C_COND_FM_MM<fmt, 0> { 241 let BaseOpcode = "c.f."#NAME; 242 let isCommutable = 1; 243 } 244 def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, 245 C_COND_FM_MM<fmt, 1> { 246 let BaseOpcode = "c.un."#NAME; 247 let isCommutable = 1; 248 } 249 def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, 250 C_COND_FM_MM<fmt, 2> { 251 let BaseOpcode = "c.eq."#NAME; 252 let isCommutable = 1; 253 } 254 def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, 255 C_COND_FM_MM<fmt, 3> { 256 let BaseOpcode = "c.ueq."#NAME; 257 let isCommutable = 1; 258 } 259 def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, 260 C_COND_FM_MM<fmt, 4> { 261 let BaseOpcode = "c.olt."#NAME; 262 } 263 def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, 264 C_COND_FM_MM<fmt, 5> { 265 let BaseOpcode = "c.ult."#NAME; 266 } 267 def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, 268 C_COND_FM_MM<fmt, 6> { 269 let BaseOpcode = "c.ole."#NAME; 270 } 271 def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, 272 C_COND_FM_MM<fmt, 7> { 273 let BaseOpcode = "c.ule."#NAME; 274 } 275 def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, 276 C_COND_FM_MM<fmt, 8> { 277 let BaseOpcode = "c.sf."#NAME; 278 let isCommutable = 1; 279 } 280 def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, 281 C_COND_FM_MM<fmt, 9> { 282 let BaseOpcode = "c.ngle."#NAME; 283 } 284 def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, 285 C_COND_FM_MM<fmt, 10> { 286 let BaseOpcode = "c.seq."#NAME; 287 let isCommutable = 1; 288 } 289 def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, 290 C_COND_FM_MM<fmt, 11> { 291 let BaseOpcode = "c.ngl."#NAME; 292 } 293 def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, 294 C_COND_FM_MM<fmt, 12> { 295 let BaseOpcode = "c.lt."#NAME; 296 } 297 def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, 298 C_COND_FM_MM<fmt, 13> { 299 let BaseOpcode = "c.nge."#NAME; 300 } 301 def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, 302 C_COND_FM_MM<fmt, 14> { 303 let BaseOpcode = "c.le."#NAME; 304 } 305 def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, 306 C_COND_FM_MM<fmt, 15> { 307 let BaseOpcode = "c.ngt."#NAME; 308 } 309} 310 311defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>, 312 ISA_MICROMIPS32_NOT_MIPS32R6; 313defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, 314 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 315let DecoderNamespace = "Mips64" in 316 defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>, 317 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64; 318 319defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, 320 ISA_MICROMIPS32_NOT_MIPS32R6; 321defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, 322 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 323defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, 324 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64; 325 326defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">, 327 ISA_MICROMIPS32_NOT_MIPS32R6, HARDFLOAT; 328 329 330// To generate NMADD and NMSUB instructions when fneg node is present 331let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, 332 InMicroMips, NotMips32r6] in { 333 defm : NMADD_NMSUB<NMADD_S_MM, NMSUB_S_MM, FGR32Opnd>, 334 ISA_MICROMIPS32_NOT_MIPS32R6; 335 defm : NMADD_NMSUB<NMADD_D32_MM, NMSUB_D32_MM, AFGR64Opnd>, 336 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 337} 338 339//===----------------------------------------------------------------------===// 340// Floating Point Patterns 341//===----------------------------------------------------------------------===// 342 343// Patterns for loads/stores with a reg+imm operand. 344let AddedComplexity = 40 in { 345 def : LoadRegImmPat<LDC1_MM, f64, load>, ISA_MICROMIPS, FGR_32; 346 def : StoreRegImmPat<SDC1_MM, f64>, ISA_MICROMIPS, FGR_32; 347 def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS; 348 def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS; 349} 350