1//==- MicroMipsInstrFPU.td - microMIPS FPU Instruction Info -*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the microMIPS FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14multiclass ADDS_MMM<string opstr, InstrItinClass Itin, bit IsComm, 15 SDPatternOperator OpNode = null_frag> { 16 def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, 17 FGR_32 { 18 string DecoderNamespace = "MicroMips"; 19 } 20 // FIXME: This needs to be part of the instruction mapping tables. 21 def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 { 22 string DecoderNamespace = "MicroMipsFP64"; 23 } 24} 25 26def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 27 ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS; 28def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 29 ADDS_FM_MM<0, 0xf0>, ISA_MICROMIPS; 30def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 31 ADDS_FM_MM<0, 0xb0>, ISA_MICROMIPS; 32def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 33 ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS; 34 35defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>, 36 ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; 37defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>, 38 ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; 39defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>, 40 ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; 41defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>, 42 ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; 43 44let DecoderNamespace = "MicroMips" in { 45 def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, 46 LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6; 47 def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, 48 SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6; 49 50 def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, 51 LWXC1_FM_MM<0x148>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6; 52 def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, 53 SWXC1_FM_MM<0x188>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6; 54} 55let isCodeGenOnly = 1 in { 56def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, 57 CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 { 58 // FIXME: This is a required to work around the fact that these instructions 59 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 60 // fcc register set is used directly. 61 bits<3> fcc = 0; 62} 63 64def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, 65 CEQS_FM_MM<1>, ISA_MICROMIPS32_NOT_MIPS32R6 { 66 // FIXME: This is a required to work around the fact that these instructions 67 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 68 // fcc register set is used directly. 69 bits<3> fcc = 0; 70} 71 72} 73 74let DecoderNamespace = "MicroMips" in { 75 def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, 76 BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6; 77 def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>, 78 BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6; 79 def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 80 ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS; 81} 82 83let DecoderNamespace = "MicroMips" in { 84 def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, 85 FGR32Opnd, II_ROUND>, 86 ROUND_W_FM_MM<0, 0xec>, ISA_MICROMIPS; 87 88 def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, 89 ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; 90 def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, 91 ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; 92 def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, 93 AFGR64Opnd, II_ROUND>, 94 ROUND_W_FM_MM<1, 0xec>, ISA_MICROMIPS, FGR_32; 95 def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, 96 ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; 97 98 def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 99 ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; 100 def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 101 ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; 102 103 def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 104 ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; 105} 106let DecoderNamespace = "MicroMipsFP64" in { 107 def CVT_W_D64_MM : ABSS_FT<"cvt.w.d", FGR32Opnd, FGR64Opnd, II_CVT>, 108 ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_64; 109} 110 111multiclass ABSS_MMM<string opstr, InstrItinClass Itin, 112 SDPatternOperator OpNode = null_frag> { 113 def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 114 ISA_MICROMIPS, FGR_32 { 115 string DecoderNamespace = "MicroMips"; 116 } 117 // FIXME: This needs to be part of the instruction mapping tables. 118 def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 119 ISA_MICROMIPS, FGR_64 { 120 string DecoderNamespace = "MicroMipsFP64"; 121 } 122} 123 124defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>; 125defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>; 126 127let DecoderNamespace = "MicroMips" in { 128 def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 129 ABS_FM_MM<0, 0xd>, ISA_MICROMIPS; 130} 131 132def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 133 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS { 134 let isMoveReg = 1; 135} 136def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 137 ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS; 138 139let DecoderNamespace = "MicroMips" in { 140 def CVT_D32_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 141 ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32; 142 def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 143 ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32; 144} 145 146let DecoderNamespace = "MicroMipsFP64" in { 147 def CVT_D64_S_MM : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 148 ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_64; 149 def CVT_D64_W_MM : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 150 ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_64; 151 def CVT_S_D64_MM : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 152 ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_64; 153} 154 155let DecoderNamespace = "MicroMips" in { 156 def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 157 ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; 158 def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 159 ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; 160} 161 162 163defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>; 164defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>; 165 166let DecoderNamespace = "MicroMips" in { 167 def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, 168 II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, 169 ISA_MICROMIPS32_NOT_MIPS32R6; 170 def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, 171 II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>, 172 ISA_MICROMIPS32_NOT_MIPS32R6; 173 def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, 174 II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>, 175 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 176 def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, 177 II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>, 178 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 179 180 def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, 181 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>, 182 ISA_MICROMIPS32_NOT_MIPS32R6; 183 def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, 184 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>, 185 ISA_MICROMIPS32_NOT_MIPS32R6; 186 def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, 187 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>, 188 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 189 def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, 190 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>, 191 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 192 193 def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, 194 II_MFC1, bitconvert>, MFC1_FM_MM<0x80>, 195 ISA_MICROMIPS; 196 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, 197 II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, 198 ISA_MICROMIPS; 199 200 def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>, 201 MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4; 202 def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>, 203 MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4; 204 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { 205 def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>, 206 MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; 207 def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>, 208 MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6; 209 } 210 def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D>, 211 MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32, 212 MADD4; 213 def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D>, 214 MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32, 215 MADD4; 216 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { 217 def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D>, 218 MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 219 def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>, 220 MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 221 } 222 223 def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, 224 II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, 225 ISA_MICROMIPS; 226 def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, 227 FGR32Opnd, II_TRUNC>, 228 ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; 229 def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 230 ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; 231 232 def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, 233 fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS; 234 235 def MTHC1_D32_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 236 MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; 237 def MFHC1_D32_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 238 MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; 239} 240 241let DecoderNamespace = "MicroMipsFP64" in { 242 def MTHC1_D64_MM : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 243 MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_64; 244 def MFHC1_D64_MM : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 245 MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_64; 246 def MTC1_D64_MM : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, 247 MFC1_FM_MM<0xa0>, ISA_MICROMIPS, FGR_64; 248} 249 250let DecoderNamespace = "MicroMips" in { 251 def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, 252 MFC1_FM_MM<0x40>, ISA_MICROMIPS; 253 def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, 254 MFC1_FM_MM<0x60>, ISA_MICROMIPS; 255 def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, 256 II_RECIP_S>, 257 ROUND_W_FM_MM<0b0, 0b01001000>, ISA_MICROMIPS; 258 def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, 259 II_RECIP_D>, 260 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_32 { 261 let BaseOpcode = "RECIP_D32"; 262 } 263 let DecoderNamespace = "MicroMipsFP64" in 264 def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, 265 II_RECIP_D>, 266 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_64; 267 def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, 268 II_RECIP_S>, 269 ROUND_W_FM_MM<0b0, 0b00001000>; 270 def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, 271 II_RECIP_D>, 272 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_32 { 273 let BaseOpcode = "RSQRT_D32"; 274 } 275 let DecoderNamespace = "MicroMipsFP64" in 276 def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, 277 II_RECIP_D>, 278 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_64; 279} 280 281let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in { 282 def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>, 283 LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_32 { 284 let BaseOpcode = "LDC132"; 285 } 286 def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>, 287 LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_32; 288 def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>, 289 LW_FM_MM<0x27>, ISA_MICROMIPS; 290 def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>, 291 LW_FM_MM<0x26>, ISA_MICROMIPS; 292} 293 294multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt, 295 InstrItinClass itin> { 296 def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, 297 C_COND_FM_MM<fmt, 0> { 298 let BaseOpcode = "c.f."#NAME; 299 let isCommutable = 1; 300 } 301 def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, 302 C_COND_FM_MM<fmt, 1> { 303 let BaseOpcode = "c.un."#NAME; 304 let isCommutable = 1; 305 } 306 def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, 307 C_COND_FM_MM<fmt, 2> { 308 let BaseOpcode = "c.eq."#NAME; 309 let isCommutable = 1; 310 } 311 def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, 312 C_COND_FM_MM<fmt, 3> { 313 let BaseOpcode = "c.ueq."#NAME; 314 let isCommutable = 1; 315 } 316 def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, 317 C_COND_FM_MM<fmt, 4> { 318 let BaseOpcode = "c.olt."#NAME; 319 } 320 def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, 321 C_COND_FM_MM<fmt, 5> { 322 let BaseOpcode = "c.ult."#NAME; 323 } 324 def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, 325 C_COND_FM_MM<fmt, 6> { 326 let BaseOpcode = "c.ole."#NAME; 327 } 328 def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, 329 C_COND_FM_MM<fmt, 7> { 330 let BaseOpcode = "c.ule."#NAME; 331 } 332 def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, 333 C_COND_FM_MM<fmt, 8> { 334 let BaseOpcode = "c.sf."#NAME; 335 let isCommutable = 1; 336 } 337 def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, 338 C_COND_FM_MM<fmt, 9> { 339 let BaseOpcode = "c.ngle."#NAME; 340 } 341 def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, 342 C_COND_FM_MM<fmt, 10> { 343 let BaseOpcode = "c.seq."#NAME; 344 let isCommutable = 1; 345 } 346 def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, 347 C_COND_FM_MM<fmt, 11> { 348 let BaseOpcode = "c.ngl."#NAME; 349 } 350 def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, 351 C_COND_FM_MM<fmt, 12> { 352 let BaseOpcode = "c.lt."#NAME; 353 } 354 def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, 355 C_COND_FM_MM<fmt, 13> { 356 let BaseOpcode = "c.nge."#NAME; 357 } 358 def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, 359 C_COND_FM_MM<fmt, 14> { 360 let BaseOpcode = "c.le."#NAME; 361 } 362 def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, 363 C_COND_FM_MM<fmt, 15> { 364 let BaseOpcode = "c.ngt."#NAME; 365 } 366} 367let DecoderNamespace = "MicroMips" in { 368 defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>, 369 ISA_MICROMIPS32_NOT_MIPS32R6; 370 defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, 371 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 372} 373 374let DecoderNamespace = "Mips64" in 375 defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>, 376 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64; 377 378defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, 379 ISA_MICROMIPS32_NOT_MIPS32R6; 380defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, 381 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 382defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, 383 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64; 384 385defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">, 386 ISA_MICROMIPS32_NOT_MIPS32R6, HARDFLOAT; 387 388 389// To generate NMADD and NMSUB instructions when fneg node is present 390let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, 391 InMicroMips, NotMips32r6] in { 392 defm : NMADD_NMSUB<NMADD_S_MM, NMSUB_S_MM, FGR32Opnd>, 393 ISA_MICROMIPS32_NOT_MIPS32R6; 394 defm : NMADD_NMSUB<NMADD_D32_MM, NMSUB_D32_MM, AFGR64Opnd>, 395 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 396} 397 398//===----------------------------------------------------------------------===// 399// Floating Point Patterns 400//===----------------------------------------------------------------------===// 401 402// Patterns for loads/stores with a reg+imm operand. 403let AddedComplexity = 40 in { 404 def : LoadRegImmPat<LDC1_MM, f64, load>, ISA_MICROMIPS, FGR_32; 405 def : StoreRegImmPat<SDC1_MM, f64>, ISA_MICROMIPS, FGR_32; 406 def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS; 407 def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS; 408} 409 410def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), 411 (MTC1_D64_MM GPR32Opnd:$src)>, ISA_MICROMIPS, FGR_64; 412 413def : MipsPat<(f32 fpimm0), (MTC1_MM ZERO)>, ISA_MICROMIPS32_NOT_MIPS32R6; 414def : MipsPat<(f32 fpimm0neg), (FNEG_S_MM (MTC1_MM ZERO))>, 415 ISA_MICROMIPS32_NOT_MIPS32R6; 416 417def : MipsPat<(f32 (fpround FGR64Opnd:$src)), 418 (CVT_S_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS, FGR_64; 419def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 420 (CVT_D64_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_64; 421def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), 422 (CVT_S_D32_MM AFGR64Opnd:$src)>, ISA_MICROMIPS, FGR_32; 423def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 424 (CVT_D32_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_32; 425def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 426 (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6, 427 FGR_32; 428 429// Selects 430defm : MovzPats0<GPR32, FGR32, MOVZ_I_S_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>, 431 ISA_MICROMIPS32_NOT_MIPS32R6; 432defm : MovzPats1<GPR32, FGR32, MOVZ_I_S_MM, XOR_MM>, 433 ISA_MICROMIPS32_NOT_MIPS32R6; 434 435defm : MovnPats<GPR32, FGR32, MOVN_I_S_MM, XOR_MM>, 436 ISA_MICROMIPS32_NOT_MIPS32R6; 437 438defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32_MM, SLT_MM, SLTu_MM, SLTi_MM, 439 SLTiu_MM>, 440 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 441defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32_MM, XOR_MM>, 442 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 443defm : MovnPats<GPR32, AFGR64, MOVN_I_D32_MM, XOR_MM>, 444 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 445