1//==- MicroMipsInstrFPU.td - microMIPS FPU Instruction Info -*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the microMIPS FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14let isCodeGenOnly = 1 in { 15def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 16 ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS; 17def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 18 ADDS_FM_MM<0, 0xf0>, ISA_MICROMIPS; 19def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 20 ADDS_FM_MM<0, 0xb0>, ISA_MICROMIPS; 21def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 22 ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS; 23 24def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>, 25 ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; 26def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>, 27 ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; 28def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>, 29 ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; 30def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, 31 ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; 32 33def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, 34 LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6; 35def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, 36 SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6; 37 38// FIXME: These instruction definitions are incorrect. They should be 64-bit 39// FPU only. 40def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, 41 LWXC1_FM_MM<0x148>, ISA_MICROMIPS32_NOT_MIPS32R6; 42def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, 43 SWXC1_FM_MM<0x188>, ISA_MICROMIPS32_NOT_MIPS32R6; 44 45def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, 46 CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 { 47 // FIXME: This is a required to work around the fact that these instructions 48 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 49 // fcc register set is used directly. 50 bits<3> fcc = 0; 51} 52 53def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, 54 CEQS_FM_MM<1>, ISA_MICROMIPS32_NOT_MIPS32R6 { 55 // FIXME: This is a required to work around the fact that these instructions 56 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 57 // fcc register set is used directly. 58 bits<3> fcc = 0; 59} 60 61def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, 62 BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6; 63def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>, 64 BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6; 65def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 66 ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS; 67def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, 68 II_ROUND>, ROUND_W_FM_MM<0, 0xec>, 69 ISA_MICROMIPS; 70 71def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, 72 ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; 73def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 74 ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; 75def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, 76 ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; 77def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, 78 II_ROUND>, ROUND_W_FM_MM<1, 0xec>, 79 ISA_MICROMIPS, FGR_32; 80def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, 81 ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; 82 83def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D, 84 fsqrt>, ROUND_W_FM_MM<1, 0x28>, 85 ISA_MICROMIPS, FGR_32; 86 87def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 88 ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; 89def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 90 ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; 91 92def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 93 ABS_FM_MM<0, 0xd>, ISA_MICROMIPS; 94def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 95 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS; 96def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 97 ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS; 98def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 99 ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32; 100def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 101 ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32; 102def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 103 ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; 104def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 105 ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; 106 107def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>, 108 ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32; 109def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>, 110 ABS_FM_MM<1, 0x2d>, ISA_MICROMIPS, FGR_32; 111 112def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 113 ABS_FM_MM<1, 0x1>, ISA_MICROMIPS, FGR_32; 114 115def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, 116 II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, 117 ISA_MICROMIPS32_NOT_MIPS32R6; 118def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, 119 II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>, 120 ISA_MICROMIPS32_NOT_MIPS32R6; 121def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, 122 II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>, 123 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 124def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, 125 II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>, 126 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 127 128def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, 129 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>, 130 ISA_MICROMIPS32_NOT_MIPS32R6; 131def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, 132 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>, 133 ISA_MICROMIPS32_NOT_MIPS32R6; 134def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, 135 MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>, 136 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 137def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, 138 MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>, 139 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 140def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, 141 II_MFC1, bitconvert>, MFC1_FM_MM<0x80>, 142 ISA_MICROMIPS; 143def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, 144 II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, 145 ISA_MICROMIPS; 146 147def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 148 MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6; 149def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 150 MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6; 151def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 152 MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; 153def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 154 MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6; 155 156def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, 157 MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 158def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, 159 MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 160def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 161 MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 162def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 163 MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 164} 165 166def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, 167 II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, 168 ISA_MICROMIPS; 169def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, 170 FGR32Opnd, II_TRUNC>, 171 ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; 172def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 173 ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; 174def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, 175 fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS; 176def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 177 MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; 178def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 179 MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; 180 181let DecoderNamespace = "MicroMips" in { 182 def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, 183 MFC1_FM_MM<0x40>, ISA_MICROMIPS; 184 def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, 185 MFC1_FM_MM<0x60>, ISA_MICROMIPS; 186 def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, 187 II_RECIP_S>, 188 ROUND_W_FM_MM<0b0, 0b01001000>, ISA_MICROMIPS; 189 def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, 190 II_RECIP_D>, 191 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_32 { 192 let BaseOpcode = "RECIP_D32"; 193 } 194 let DecoderNamespace = "MicroMipsFP64" in 195 def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, 196 II_RECIP_D>, 197 ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_64; 198 def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, 199 II_RECIP_S>, 200 ROUND_W_FM_MM<0b0, 0b00001000>; 201 def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, 202 II_RECIP_D>, 203 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_32 { 204 let BaseOpcode = "RSQRT_D32"; 205 } 206 let DecoderNamespace = "MicroMipsFP64" in 207 def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, 208 II_RECIP_D>, 209 ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_64; 210} 211 212let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in { 213 def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>, 214 LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_32 { 215 let BaseOpcode = "LDC132"; 216 } 217 def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>, 218 LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_32; 219 def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>, 220 LW_FM_MM<0x27>, ISA_MICROMIPS; 221 def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>, 222 LW_FM_MM<0x26>, ISA_MICROMIPS; 223} 224 225multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt, 226 InstrItinClass itin> { 227 def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, 228 C_COND_FM_MM<fmt, 0> { 229 let BaseOpcode = "c.f."#NAME; 230 let isCommutable = 1; 231 } 232 def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, 233 C_COND_FM_MM<fmt, 1> { 234 let BaseOpcode = "c.un."#NAME; 235 let isCommutable = 1; 236 } 237 def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, 238 C_COND_FM_MM<fmt, 2> { 239 let BaseOpcode = "c.eq."#NAME; 240 let isCommutable = 1; 241 } 242 def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, 243 C_COND_FM_MM<fmt, 3> { 244 let BaseOpcode = "c.ueq."#NAME; 245 let isCommutable = 1; 246 } 247 def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, 248 C_COND_FM_MM<fmt, 4> { 249 let BaseOpcode = "c.olt."#NAME; 250 } 251 def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, 252 C_COND_FM_MM<fmt, 5> { 253 let BaseOpcode = "c.ult."#NAME; 254 } 255 def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, 256 C_COND_FM_MM<fmt, 6> { 257 let BaseOpcode = "c.ole."#NAME; 258 } 259 def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, 260 C_COND_FM_MM<fmt, 7> { 261 let BaseOpcode = "c.ule."#NAME; 262 } 263 def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, 264 C_COND_FM_MM<fmt, 8> { 265 let BaseOpcode = "c.sf."#NAME; 266 let isCommutable = 1; 267 } 268 def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, 269 C_COND_FM_MM<fmt, 9> { 270 let BaseOpcode = "c.ngle."#NAME; 271 } 272 def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, 273 C_COND_FM_MM<fmt, 10> { 274 let BaseOpcode = "c.seq."#NAME; 275 let isCommutable = 1; 276 } 277 def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, 278 C_COND_FM_MM<fmt, 11> { 279 let BaseOpcode = "c.ngl."#NAME; 280 } 281 def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, 282 C_COND_FM_MM<fmt, 12> { 283 let BaseOpcode = "c.lt."#NAME; 284 } 285 def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, 286 C_COND_FM_MM<fmt, 13> { 287 let BaseOpcode = "c.nge."#NAME; 288 } 289 def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, 290 C_COND_FM_MM<fmt, 14> { 291 let BaseOpcode = "c.le."#NAME; 292 } 293 def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, 294 C_COND_FM_MM<fmt, 15> { 295 let BaseOpcode = "c.ngt."#NAME; 296 } 297} 298 299defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>, 300 ISA_MICROMIPS32_NOT_MIPS32R6; 301defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, 302 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 303let DecoderNamespace = "Mips64" in 304 defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>, 305 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64; 306 307defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, 308 ISA_MICROMIPS32_NOT_MIPS32R6; 309defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, 310 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 311defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, 312 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64; 313 314defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">, 315 ISA_MICROMIPS32_NOT_MIPS32R6, HARDFLOAT; 316 317 318// To generate NMADD and NMSUB instructions when fneg node is present 319let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, 320 InMicroMips, NotMips32r6] in { 321 defm : NMADD_NMSUB<NMADD_S_MM, NMSUB_S_MM, FGR32Opnd>, 322 ISA_MICROMIPS32_NOT_MIPS32R6; 323 defm : NMADD_NMSUB<NMADD_D32_MM, NMSUB_D32_MM, AFGR64Opnd>, 324 ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; 325} 326 327//===----------------------------------------------------------------------===// 328// Floating Point Patterns 329//===----------------------------------------------------------------------===// 330 331// Patterns for loads/stores with a reg+imm operand. 332let AddedComplexity = 40 in { 333 def : LoadRegImmPat<LDC1_MM, f64, load>, ISA_MICROMIPS, FGR_32; 334 def : StoreRegImmPat<SDC1_MM, f64>, ISA_MICROMIPS, FGR_32; 335 def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS; 336 def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS; 337} 338