1let isCodeGenOnly = 1, Predicates = [InMicroMips] in {
2def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
3                ADDS_FM_MM<0, 0x30>;
4def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
5                ADDS_FM_MM<0, 0xf0>;
6def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
7                ADDS_FM_MM<0, 0xb0>;
8def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
9                ADDS_FM_MM<0, 0x70>;
10
11def FADD_MM  : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>,
12               ADDS_FM_MM<1, 0x30>;
13def FDIV_MM  : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>,
14               ADDS_FM_MM<1, 0xf0>;
15def FMUL_MM  : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>,
16               ADDS_FM_MM<1, 0xb0>;
17def FSUB_MM  : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>,
18               ADDS_FM_MM<1, 0x70>;
19
20def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
21               LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6;
22def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
23               SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6;
24def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
25               LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6;
26def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>,
27               SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6;
28
29def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
30                  CEQS_FM_MM<0>;
31def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
32                  CEQS_FM_MM<1>;
33
34def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
35              BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
36def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
37              BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
38def CVT_W_S_MM   : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
39                   ROUND_W_FM_MM<0, 0x24>;
40def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
41                   ROUND_W_FM_MM<0, 0xec>;
42
43def CEIL_W_MM  : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
44                 ROUND_W_FM_MM<1, 0x6c>;
45def CVT_W_MM   : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
46                 ROUND_W_FM_MM<1, 0x24>;
47def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
48                 ROUND_W_FM_MM<1, 0x2c>;
49def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
50                 ROUND_W_FM_MM<1, 0xec>;
51def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
52                 ROUND_W_FM_MM<1, 0xac>;
53
54def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
55                              fsqrt>, ROUND_W_FM_MM<1, 0x28>;
56
57def CVT_L_S_MM   : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
58                   ROUND_W_FM_MM<0, 0x4>, INSN_MIPS3_32R2;
59def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
60                   ROUND_W_FM_MM<1, 0x4>, INSN_MIPS3_32R2;
61
62def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
63                ABS_FM_MM<0, 0xd>;
64def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
65                ABS_FM_MM<0, 0x1>;
66def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
67                ABS_FM_MM<0, 0x2d>;
68def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
69                 ABS_FM_MM<0, 0x4d>;
70def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
71                   ABS_FM_MM<1, 0x4d>;
72def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
73                   ABS_FM_MM<0, 0x6d>;
74def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
75                 ABS_FM_MM<1, 0x6d>;
76
77def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
78              ABS_FM_MM<1, 0xd>;
79def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
80              ABS_FM_MM<1, 0x2d>;
81
82def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
83                  ABS_FM_MM<1, 0x1>, FGR_32;
84
85def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
86                                     II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>;
87def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
88                                     II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>;
89def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
90                                       II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>;
91def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
92                                       II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>;
93
94def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
95                                   MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>;
96def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
97                                   MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>;
98def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
99                                     MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>;
100def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
101                                     MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>;
102def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
103                             II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
104def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
105                             II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
106
107def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
108                MADDS_FM_MM<0x1>;
109def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
110                MADDS_FM_MM<0x21>;
111def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
112                 MADDS_FM_MM<0x2>;
113def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
114                 MADDS_FM_MM<0x22>;
115
116def MADD_D32_MM  : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
117                   MADDS_FM_MM<0x9>;
118def MSUB_D32_MM  : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
119                   MADDS_FM_MM<0x29>;
120def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
121                   MADDS_FM_MM<0xa>;
122def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
123                   MADDS_FM_MM<0x2a>;
124}
125
126let AdditionalPredicates = [InMicroMips] in {
127  def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
128    II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>;
129  def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
130    FGR32Opnd, II_TRUNC>, ROUND_W_FM_MM<0, 0xac>;
131  def CEIL_W_S_MM  : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
132    ROUND_W_FM_MM<0, 0x6c>;
133  def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
134    fsqrt>, ROUND_W_FM_MM<0, 0x28>;
135  def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
136             MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
137  def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
138                 MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
139  let DecoderNamespace = "MicroMips" in {
140    def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
141                  MFC1_FM_MM<0x40>;
142    def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
143                  MFC1_FM_MM<0x60>;
144    def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
145                                    II_RECIP_S>,
146                     ROUND_W_FM_MM<0b0, 0b01001000>;
147    def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
148                                 II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>;
149    def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
150                                    II_RECIP_S>,
151                     ROUND_W_FM_MM<0b0, 0b00001000>;
152    def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
153                                 II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>;
154  }
155  let DecoderNamespace = "MicroMips",  DecoderMethod = "DecodeFMemMMR2" in {
156    def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
157                  LW_FM_MM<0x2f>, FGR_32 {
158      let BaseOpcode = "LDC132";
159    }
160    def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,
161                  LW_FM_MM<0x2e>, FGR_32;
162    def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>,
163                  LW_FM_MM<0x27>;
164    def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>,
165                  LW_FM_MM<0x26>;
166  }
167}
168
169//===----------------------------------------------------------------------===//
170// Floating Point Patterns
171//===----------------------------------------------------------------------===//
172let AdditionalPredicates = [InMicroMips] in {
173  // Patterns for loads/stores with a reg+imm operand.
174  let AddedComplexity = 40 in {
175    def : LoadRegImmPat<LDC1_MM, f64, load>, FGR_32;
176    def : StoreRegImmPat<SDC1_MM, f64>, FGR_32;
177    def : LoadRegImmPat<LWC1_MM, f32, load>;
178    def : StoreRegImmPat<SWC1_MM, f32>;
179  }
180}
181