1//===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class MMDSPInst<string opstr = "">
11    : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
12  let InsnPredicates = [HasDSP];
13  let AdditionalPredicates = [InMicroMips];
14  string BaseOpcode = opstr;
15  string Arch = "mmdsp";
16  let DecoderNamespace = "MicroMips";
17}
18
19class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
20  bits<5> rd;
21  bits<5> rs;
22  bits<5> rt;
23
24  let Inst{31-26} = 0b000000;
25  let Inst{25-21} = rt;
26  let Inst{20-16} = rs;
27  let Inst{15-11} = rd;
28  let Inst{10-0}  = op;
29}
30
31class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
32  bits<5> rt;
33  bits<5> rs;
34
35  let Inst{31-26} = 0b000000;
36  let Inst{25-21} = rt;
37  let Inst{20-16} = rs;
38  let Inst{15-6}  = op;
39  let Inst{5-0}   = 0b111100;
40}
41
42class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
43  bits<5> rt;
44  bits<5> rs;
45  bits<2> ac;
46
47  let Inst{31-26} = 0b000000;
48  let Inst{25-21} = rt;
49  let Inst{20-16} = rs;
50  let Inst{15-14} = ac;
51  let Inst{13-6}  = op;
52  let Inst{5-0}   = 0b111100;
53}
54
55class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
56  bits<5> rd;
57  bits<5> rs;
58  bits<5> rt;
59
60  let Inst{31-26} = 0b000000;
61  let Inst{25-21} = rt;
62  let Inst{20-16} = rs;
63  let Inst{15-11} = rd;
64  let Inst{10}    = 0b0;
65  let Inst{9-0}   = op;
66}
67
68class POOL32A_2RSA4_FMT<string opstr, bits<12> op> : MMDSPInst<opstr> {
69  bits<5> rt;
70  bits<5> rs;
71  bits<4> sa;
72
73  let Inst{31-26} = 0b000000;
74  let Inst{25-21} = rt;
75  let Inst{20-16} = rs;
76  let Inst{15-12} = sa;
77  let Inst{11-0}  = op;
78}
79
80class POOL32A_2RSA3_FMT<string opstr, bits<7> op> : MMDSPInst<opstr> {
81  bits<5> rt;
82  bits<5> rs;
83  bits<3> sa;
84
85  let Inst{31-26} = 0b000000;
86  let Inst{25-21} = rt;
87  let Inst{20-16} = rs;
88  let Inst{15-13} = sa;
89  let Inst{12-6}  = op;
90  let Inst{5-0}   = 0b111100;
91}
92
93class POOL32A_2RSA5B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
94  bits<5> rt;
95  bits<5> rs;
96  bits<5> sa;
97
98  let Inst{31-26} = 0b000000;
99  let Inst{25-21} = rt;
100  let Inst{20-16} = rs;
101  let Inst{15-11} = sa;
102  let Inst{10}    = 0b0;
103  let Inst{9-0}   = op;
104}
105
106class POOL32A_2RSA4B0_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
107  bits<5> rt;
108  bits<5> rs;
109  bits<4> sa;
110
111  let Inst{31-26} = 0b000000;
112  let Inst{25-21} = rt;
113  let Inst{20-16} = rs;
114  let Inst{15-12} = sa;
115  let Inst{11}    = 0b0;
116  let Inst{10-0}  = op;
117}
118
119class POOL32A_2RSA4OP6_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
120  bits<5> rt;
121  bits<5> rs;
122  bits<4> sa;
123
124  let Inst{31-26} = 0b000000;
125  let Inst{25-21} = rt;
126  let Inst{20-16} = rs;
127  let Inst{15-12} = sa;
128  let Inst{11-6}  = op;
129  let Inst{5-0}   = 0b111100;
130}
131
132class POOL32A_1RIMM5AC_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
133  bits<5> rt;
134  bits<5> imm;
135  bits<2> ac;
136
137  let Inst{31-26} = 0b000000;
138  let Inst{25-21} = rt;
139  let Inst{20-16} = imm;
140  let Inst{15-14} = ac;
141  let Inst{13-6}  = funct;
142  let Inst{5-0}   = 0b111100;
143}
144