1//=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes microMIPSr6 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14def brtarget21_mm : Operand<OtherVT> {
15  let EncoderMethod = "getBranchTarget21OpValueMM";
16  let OperandType = "OPERAND_PCREL";
17  let DecoderMethod = "DecodeBranchTarget21MM";
18  let ParserMatchClass = MipsJumpTargetAsmOperand;
19}
20
21def brtarget26_mm : Operand<OtherVT> {
22  let EncoderMethod = "getBranchTarget26OpValueMM";
23  let OperandType = "OPERAND_PCREL";
24  let DecoderMethod = "DecodeBranchTarget26MM";
25  let ParserMatchClass = MipsJumpTargetAsmOperand;
26}
27
28def brtargetr6 : Operand<OtherVT> {
29  let EncoderMethod = "getBranchTargetOpValueMMR6";
30  let OperandType = "OPERAND_PCREL";
31  let DecoderMethod = "DecodeBranchTargetMM";
32  let ParserMatchClass = MipsJumpTargetAsmOperand;
33}
34
35def brtarget_lsl2_mm : Operand<OtherVT> {
36  let EncoderMethod = "getBranchTargetOpValueLsl2MMR6";
37  let OperandType = "OPERAND_PCREL";
38  // Instructions that use this operand have their decoder method
39  // set with DecodeDisambiguates
40  let DecoderMethod = "";
41  let ParserMatchClass = MipsJumpTargetAsmOperand;
42}
43
44//===----------------------------------------------------------------------===//
45//
46// Instruction Encodings
47//
48//===----------------------------------------------------------------------===//
49class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
50class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
51class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
52class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
53class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
54class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
55class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
56class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
57class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
58class AUI_MMR6_ENC : AUI_FM_MMR6;
59class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
60class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
61class BC16_MMR6_ENC : BC16_FM_MM16R6;
62class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
63class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
64class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
65class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
66class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;
67class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;
68class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,
69                      DecodeDisambiguates<"POP75GroupBranchMMR6">;
70class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
71                       DecodeDisambiguates<"BlezGroupBranchMMR6">;
72class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>,
73                      DecodeDisambiguates<"POP65GroupBranchMMR6">;
74class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>,
75                       DecodeDisambiguates<"BgtzGroupBranchMMR6">;
76class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
77class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>;
78class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>,
79                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
80class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>,
81                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
82class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>,
83                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
84class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>,
85                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
86class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>,
87                         DecodeDisambiguates<"POP35GroupBranchMMR6">;
88class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>,
89                         DecodeDisambiguates<"POP37GroupBranchMMR6">;
90class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>,
91                         MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
92class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>,
93                         MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
94class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
95                         MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
96class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
97                         MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
98class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
99class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
100class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
101class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
102class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
103class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
104class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
105class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
106class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
107class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
108class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
109class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
110class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
111class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
112class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
113class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
114class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
115class LWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x1>;
116class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
117class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
118class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
119class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
120class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
121class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
122class MFHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfhc1", 0b11000000>;
123class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
124class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
125class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
126class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
127class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
128class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
129class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
130class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
131class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
132class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
133class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
134class MTHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mthc1", 0b11100000>;
135class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
136class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
137class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
138class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
139class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
140class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
141class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
142class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
143class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
144class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
145class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
146class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
147class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
148class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
149class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
150class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
151class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
152class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
153class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
154class SWP_MMR6_ENC : POOL32B_LWP_SWP_FM_MMR6<0x9>;
155class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
156class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
157class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
158class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
159class LB_MMR6_ENC : LB32_FM_MMR6;
160class LBU_MMR6_ENC : LBU32_FM_MMR6;
161class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>;
162class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>;
163class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
164class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
165class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
166class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
167class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
168class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
169class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
170class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
171class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
172class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
173class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
174class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
175class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
176class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
177class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
178class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
179class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
180class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
181class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
182class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
183class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
184class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
185class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
186class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
187class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
188class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
189class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
190class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
191class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
192class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
193class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
194class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
195class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
196class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
197class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
198class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
199class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
200class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
201class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
202                                                       0b11001100>;
203class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
204                                                       0b11001100>;
205class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
206                                                       0b11101100>;
207class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
208                                                       0b11101100>;
209class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
210class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
211class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
212class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
213class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
214class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
215class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
216class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
217class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>;
218class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>;
219class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>;
220class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
221class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
222class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
223class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
224class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
225class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
226class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
227class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
228class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
229class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
230class LI16_MMR6_ENC : LI_FM_MM16;
231class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
232class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
233class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
234class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
235class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
236class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
237class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
238class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
239class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
240class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
241class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
242class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
243class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
244class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
245class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
246class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
247class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
248class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
249
250/// Floating Point Instructions
251class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
252class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
253class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
254class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
255class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
256class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
257class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
258class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
259class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
260class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
261class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
262class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
263class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
264class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
265class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
266class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
267class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
268class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
269class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
270class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
271class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
272class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
273class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
274class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
275
276class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
277class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
278class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
279class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
280class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
281class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
282class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
283class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
284class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
285class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
286
287//===----------------------------------------------------------------------===//
288//
289// Instruction Descriptions
290//
291//===----------------------------------------------------------------------===//
292
293class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
294                                  RegisterOperand GPROpnd>
295    : BRANCH_DESC_BASE {
296  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
297  dag OutOperandList = (outs);
298  string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
299  list<Register> Defs = [AT];
300  InstrItinClass Itinerary = II_BCCZC;
301}
302
303class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
304                                                      GPR32Opnd> {
305  list<Register> Defs = [RA];
306}
307
308class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
309                                                      GPR32Opnd> {
310  list<Register> Defs = [RA];
311}
312
313class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
314                                                      GPR32Opnd> {
315  list<Register> Defs = [RA];
316}
317
318class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
319                                                      GPR32Opnd> {
320  list<Register> Defs = [RA];
321}
322
323class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
324                                                      GPR32Opnd> {
325  list<Register> Defs = [RA];
326}
327
328class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
329                                                      GPR32Opnd> {
330  list<Register> Defs = [RA];
331}
332
333class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm,
334                                                    GPR32Opnd>;
335class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm,
336                                                    GPR32Opnd>;
337class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm,
338                                                    GPR32Opnd>;
339class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm,
340                                                    GPR32Opnd>;
341
342class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
343                                RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
344  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
345  dag OutOperandList = (outs);
346  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
347  list<Register> Defs = [AT];
348  InstrItinClass Itinerary = II_BCCC;
349}
350
351class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
352                                                 GPR32Opnd>;
353class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm,
354                                                 GPR32Opnd>;
355class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm,
356                                                 GPR32Opnd>;
357class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm,
358                                                 GPR32Opnd>;
359class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
360                                                 GPR32Opnd>;
361class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
362                                                 GPR32Opnd>;
363
364class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
365class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
366class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
367class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
368class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
369class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
370class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
371
372class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
373    : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
374  dag InOperandList = (ins opnd:$offset);
375  dag OutOperandList = (outs);
376  string AsmString = !strconcat(instr_asm, "\t$offset");
377  bit isBarrier = 1;
378  InstrItinClass Itinerary = Itin;
379}
380
381class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
382  bit isCall = 1;
383  list<Register> Defs = [RA];
384}
385class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC>;
386
387class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
388                                       !strconcat("bc16", "\t$offset"), [],
389                                       II_BC, FrmI>,
390                       MMR6Arch<"bc16">, MicroMipsR6Inst16 {
391  let isBranch = 1;
392  let isTerminator = 1;
393  let isBarrier = 1;
394  let hasDelaySlot = 0;
395  let AdditionalPredicates = [RelocPIC];
396  let Defs = [AT];
397}
398
399class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
400    : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
401  let isBranch = 1;
402  let isTerminator = 1;
403  let hasDelaySlot = 0;
404  let Defs = [AT];
405}
406class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
407class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
408
409class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
410class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
411
412class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
413    : MMR6Arch<instr_asm> {
414  dag OutOperandList = (outs GPROpnd:$rd);
415  dag InOperandList = (ins GPROpnd:$rt);
416  string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
417  list<dag> Pattern = [];
418  InstrItinClass Itinerary = II_BITSWAP;
419}
420
421class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
422
423class BRK_MMR6_DESC : BRK_FT<"break">;
424
425class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
426                           RegisterOperand GPROpnd, InstrItinClass Itin>
427      : MMR6Arch<instr_asm> {
428  dag OutOperandList = (outs);
429  dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
430  string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
431  list<dag> Pattern = [];
432  string DecoderMethod = "DecodeCacheOpMM";
433  InstrItinClass Itinerary = Itin;
434}
435
436class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd,
437                                             II_CACHE>;
438class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd,
439                                             II_PREF>;
440
441class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
442                                  RegisterOperand GPROpnd, InstrItinClass Itin>
443    : CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd, GPROpnd, Itin> {
444  string DecoderMethod = "DecodePrefeOpMM";
445}
446
447class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9,
448                                                    GPR32Opnd, II_PREFE>;
449class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9,
450                                                     GPR32Opnd, II_CACHEE>;
451
452class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
453                            RegisterOperand GPROpnd, InstrItinClass Itin>
454    : MMR6Arch<instr_asm> {
455  dag OutOperandList = (outs GPROpnd:$rt);
456  dag InOperandList = (ins MemOpnd:$addr);
457  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
458  string DecoderMethod = "DecodeLoadByte15";
459  bit mayLoad = 1;
460  InstrItinClass Itinerary = Itin;
461}
462class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
463class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
464                                            II_LBU>;
465
466class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
467                              RegisterOperand GPROpnd, InstrItinClass Itin>
468    : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd, Itin> {
469  let DecoderMethod = "DecodeLoadByte9";
470}
471class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd,
472                                              II_LBE>;
473class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd,
474                                               II_LBUE>;
475
476class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
477                             InstrItinClass Itin> : MMR6Arch<instr_asm> {
478  dag OutOperandList = (outs GPROpnd:$rt);
479  dag InOperandList = (ins GPROpnd:$rs);
480  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
481  InstrItinClass Itinerary = Itin;
482}
483
484class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
485class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
486
487class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
488class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
489class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
490
491class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
492class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
493class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
494
495class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
496    : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
497                      [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
498      MMR6Arch<opstr>, MicroMipsR6Inst16 {
499  let isCall = 1;
500  let hasDelaySlot = 0;
501  let Defs = [RA];
502}
503class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
504
505class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
506                                     RegisterOperand GPROpnd,
507                                     InstrItinClass Itin>
508    : MMR6Arch<opstr> {
509  dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
510  string AsmString = !strconcat(opstr, "\t$rt, $offset");
511  list<dag> Pattern = [];
512  bit isTerminator = 1;
513  bit hasDelaySlot = 0;
514  InstrItinClass Itinerary = Itin;
515}
516
517class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
518                                                       GPR32Opnd, II_JIALC> {
519  bit isCall = 1;
520  list<Register> Defs = [RA];
521}
522
523class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
524                                                     GPR32Opnd, II_JIC> {
525  bit isBarrier = 1;
526  list<Register> Defs = [AT];
527}
528
529class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
530    : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
531                      [], II_JR, FrmR>,
532      MMR6Arch<opstr>, MicroMipsR6Inst16 {
533  let hasDelaySlot = 0;
534  let isBranch = 1;
535  let isIndirectBranch = 1;
536}
537class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
538
539class JRCADDIUSP_MMR6_DESC
540    : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
541                      [], II_JRADDIUSP, FrmR>,
542      MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
543  let hasDelaySlot = 0;
544  let isTerminator = 1;
545  let isBarrier = 1;
546  let isBranch = 1;
547  let isIndirectBranch = 1;
548}
549
550class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
551                      Operand ImmOpnd, InstrItinClass Itin>
552    : MMR6Arch<instr_asm> {
553  dag OutOperandList = (outs GPROpnd:$rd);
554  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
555  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
556  list<dag> Pattern = [];
557  InstrItinClass Itinerary = Itin;
558}
559
560class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
561                                             II_ALIGN>;
562
563class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
564                         InstrItinClass Itin> : MMR6Arch<instr_asm> {
565  dag OutOperandList = (outs GPROpnd:$rt);
566  dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
567  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
568  list<dag> Pattern = [];
569  InstrItinClass Itinerary = Itin;
570}
571
572class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
573
574class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
575class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
576class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
577                            InstrItinClass Itin> : MMR6Arch<instr_asm> {
578  dag OutOperandList = (outs GPROpnd:$rt);
579  dag InOperandList = (ins simm16:$imm);
580  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
581  list<dag> Pattern = [];
582  InstrItinClass Itinerary = Itin;
583}
584
585class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
586class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
587
588class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
589                         Operand ImmOpnd, InstrItinClass Itin>
590    : MMR6Arch<instr_asm> {
591  dag OutOperandList = (outs GPROpnd:$rd);
592  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
593  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
594  list<dag> Pattern = [];
595  InstrItinClass Itinerary = Itin;
596}
597
598class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
599
600class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
601                           Operand ImmOpnd, InstrItinClass Itin>
602    : MMR6Arch<instr_asm> {
603  dag OutOperandList = (outs GPROpnd:$rt);
604  dag InOperandList = (ins ImmOpnd:$imm);
605  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
606  list<dag> Pattern = [];
607  InstrItinClass Itinerary = Itin;
608}
609
610class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
611                                               simm19_lsl2, II_ADDIUPC>;
612class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
613                                           II_LWPC>;
614
615class LWP_MMR6_DESC : MMR6Arch<"lwp"> {
616  dag OutOperandList = (outs regpair:$rd);
617  dag InOperandList = (ins mem_simm12:$addr);
618  string AsmString = !strconcat("lwp", "\t$rd, $addr");
619  list<dag> Pattern = [];
620  InstrItinClass Itinerary = II_LWP;
621  ComplexPattern Addr = addr;
622  Format f = FrmI;
623  string BaseOpcode = "lwp";
624  string DecoderMethod = "DecodeMemMMImm12";
625  bit mayLoad = 1;
626}
627
628class SWP_MMR6_DESC : MMR6Arch<"swp"> {
629  dag OutOperandList = (outs);
630  dag InOperandList = (ins regpair:$rd, mem_simm12:$addr);
631  string AsmString = !strconcat("swp", "\t$rd, $addr");
632  list<dag> Pattern = [];
633  InstrItinClass Itinerary = II_SWP;
634  ComplexPattern Addr = addr;
635  Format f = FrmI;
636  string BaseOpcode = "swp";
637  string DecoderMethod = "DecodeMemMMImm12";
638  bit mayStore = 1;
639}
640
641class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
642                               InstrItinClass Itin> : MMR6Arch<instr_asm> {
643  dag OutOperandList = (outs GPROpnd:$rd);
644  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
645  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
646  list<dag> Pattern = [];
647  InstrItinClass Itinerary = Itin;
648}
649
650class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
651                                                  II_SELCCZ>;
652class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
653                                                  II_SELCCZ>;
654class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
655class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
656  dag OutOperandList = (outs GPR32Opnd:$rt);
657  dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
658  string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
659  list<dag> Pattern = [];
660  InstrItinClass Itinerary = II_RDHWR;
661  Format Form = FrmR;
662}
663
664class WAIT_MMR6_DESC : WaitMM<"wait">;
665// FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
666//        Assemblers targeting specifically Release 6 should reject the SSNOP
667//        instruction with an error.
668class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
669class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
670
671class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
672                            InstrItinClass Itin,
673                            SDPatternOperator OpNode=null_frag>
674    : MipsR6Inst {
675  dag OutOperandList = (outs GPROpnd:$rd);
676  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
677  string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
678  list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
679  string BaseOpcode = opstr;
680  Format f = FrmR;
681  let isCommutable = 0;
682  let isReMaterializable = 1;
683  InstrItinClass Itinerary = Itin;
684
685  // This instruction doesn't trap division by zero itself. We must insert
686  // teq instructions as well.
687  bit usesCustomInserter = 1;
688}
689class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
690class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
691class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
692class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
693class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
694class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
695class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
696class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
697class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
698                                  or> {
699  int AddedComplexity = 1;
700}
701class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
702class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
703                                   immZExt16, xor>;
704
705class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
706                  InstrItinClass Itin = NoItinerary,
707                  SDPatternOperator OpNode = null_frag,
708                  ComplexPattern Addr = addr> :
709  InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
710         [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
711  let DecoderMethod = "DecodeMem";
712  let mayStore = 1;
713}
714class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
715  InstrItinClass Itinerary = II_SW;
716}
717class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9, II_SWE>;
718
719class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
720                                 InstrItinClass Itin> : MMR6Arch<instr_asm> {
721  dag InOperandList = (ins RO:$rs);
722  dag OutOperandList = (outs RO:$rt);
723  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
724  list<dag> Pattern = [];
725  Format f = FrmR;
726  string BaseOpcode = instr_asm;
727  bit hasSideEffects = 0;
728  InstrItinClass Itinerary = Itin;
729}
730class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
731                                                    II_WRPGPR>;
732class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
733
734class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
735                         RegisterOperand SrcRC, InstrItinClass Itin> {
736  dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
737  dag OutOperandList = (outs DstRC:$rs);
738  string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
739  list<dag> Pattern = [];
740  Format f = FrmFR;
741  string BaseOpcode = opstr;
742  InstrItinClass Itinerary = Itin;
743}
744class MTC1_MMR6_DESC_BASE<
745      string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
746      InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
747      : MipsR6Inst {
748  dag InOperandList = (ins SrcRC:$rt);
749  dag OutOperandList = (outs DstRC:$fs);
750  string AsmString = !strconcat(opstr, "\t$rt, $fs");
751  list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
752  Format f = FrmFR;
753  InstrItinClass Itinerary = Itin;
754  string BaseOpcode = opstr;
755}
756class MTC1_64_MMR6_DESC_BASE<
757      string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
758      InstrItinClass Itin = NoItinerary> : MipsR6Inst {
759  dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
760  dag OutOperandList = (outs DstRC:$fs);
761  string AsmString = !strconcat(opstr, "\t$rt, $fs");
762  list<dag> Pattern = [];
763  Format f = FrmFR;
764  InstrItinClass Itinerary = Itin;
765  string BaseOpcode = opstr;
766  // $fs_in is part of a white lie to work around a widespread bug in the FPU
767  // implementation. See expandBuildPairF64 for details.
768  let Constraints = "$fs = $fs_in";
769}
770class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
771                         RegisterOperand SrcRC, InstrItinClass Itin> {
772  dag InOperandList = (ins SrcRC:$rt);
773  dag OutOperandList = (outs DstRC:$impl);
774  string AsmString = !strconcat(opstr, "\t$rt, $impl");
775  list<dag> Pattern = [];
776  Format f = FrmFR;
777  string BaseOpcode = opstr;
778  InstrItinClass Itinerary = Itin;
779}
780
781class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
782                                           II_MTC0>;
783class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
784                                           II_MTC1, bitconvert>, HARDFLOAT;
785class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
786                                           II_MTC2>;
787class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
788                                            II_MTHC0>;
789class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd,
790                                                   GPR32Opnd, II_MTC1>,
791                            HARDFLOAT, FGR_32;
792class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd,
793                                                   GPR32Opnd, II_MTC1>,
794                            HARDFLOAT, FGR_64;
795class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
796                                            II_MTC2>;
797
798class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
799                          RegisterOperand SrcRC, InstrItinClass Itin> {
800  dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
801  dag OutOperandList = (outs DstRC:$rt);
802  string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
803  list<dag> Pattern = [];
804  Format f = FrmFR;
805  string BaseOpcode = opstr;
806  InstrItinClass Itinerary = Itin;
807}
808class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
809                          RegisterOperand SrcRC,
810                          InstrItinClass Itin = NoItinerary,
811                          SDPatternOperator OpNode = null_frag> : MipsR6Inst {
812  dag InOperandList = (ins SrcRC:$fs);
813  dag OutOperandList = (outs DstRC:$rt);
814  string AsmString = !strconcat(opstr, "\t$rt, $fs");
815  list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
816  Format f = FrmFR;
817  InstrItinClass Itinerary = Itin;
818  string BaseOpcode = opstr;
819}
820class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
821                          RegisterOperand SrcRC, InstrItinClass Itin> {
822  dag InOperandList = (ins SrcRC:$impl);
823  dag OutOperandList = (outs DstRC:$rt);
824  string AsmString = !strconcat(opstr, "\t$rt, $impl");
825  list<dag> Pattern = [];
826  Format f = FrmFR;
827  string BaseOpcode = opstr;
828  InstrItinClass Itinerary = Itin;
829}
830class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
831                                           II_MFC0>;
832class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
833                                           II_MFC1, bitconvert>, HARDFLOAT;
834class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
835                                           II_MFC2>;
836class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
837                                            II_MFHC0>;
838class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd,
839                                                II_MFHC1>, HARDFLOAT, FGR_32;
840class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd,
841                                                II_MFHC1>, HARDFLOAT, FGR_64;
842class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
843                                            II_MFC2>;
844
845class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
846  dag InOperandList = (ins mem_mm_16:$addr);
847  dag OutOperandList = (outs FGR64Opnd:$ft);
848  string AsmString = !strconcat("ldc1", "\t$ft, $addr");
849  list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
850  Format f = FrmFI;
851  InstrItinClass Itinerary = II_LDC1;
852  string BaseOpcode = "ldc1";
853  bit mayLoad = 1;
854  let DecoderMethod = "DecodeFMemMMR2";
855}
856
857class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
858  dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr);
859  dag OutOperandList = (outs);
860  string AsmString = !strconcat("sdc1", "\t$ft, $addr");
861  list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
862  Format f = FrmFI;
863  InstrItinClass Itinerary = II_SDC1;
864  string BaseOpcode = "sdc1";
865  bit mayStore = 1;
866  let DecoderMethod = "DecodeFMemMMR2";
867}
868
869class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
870  dag OutOperandList = (outs COP2Opnd:$rt);
871  dag InOperandList = (ins mem_mm_11:$addr);
872  string AsmString = !strconcat(opstr, "\t$rt, $addr");
873  list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
874  Format f = FrmFI;
875  InstrItinClass Itinerary = itin;
876  string BaseOpcode = opstr;
877  bit mayLoad = 1;
878  string DecoderMethod = "DecodeFMemCop2MMR6";
879}
880class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
881class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
882
883class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
884  dag OutOperandList = (outs);
885  dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
886  string AsmString = !strconcat(opstr, "\t$rt, $addr");
887  list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
888  Format f = FrmFI;
889  InstrItinClass Itinerary = itin;
890  string BaseOpcode = opstr;
891  bit mayStore = 1;
892  string DecoderMethod = "DecodeFMemCop2MMR6";
893}
894class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
895class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
896
897/// Floating Point Instructions
898class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
899                            InstrItinClass Itin, bit isComm,
900                            SDPatternOperator OpNode = null_frag> : HARDFLOAT {
901  dag OutOperandList = (outs RC:$fd);
902  dag InOperandList = (ins RC:$ft, RC:$fs);
903  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
904  list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
905  InstrItinClass Itinerary = Itin;
906  bit isCommutable = isComm;
907}
908class FADD_S_MMR6_DESC
909  : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
910class FADD_D_MMR6_DESC
911  : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
912class FSUB_S_MMR6_DESC
913  : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
914class FSUB_D_MMR6_DESC
915  : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
916class FMUL_S_MMR6_DESC
917  : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
918class FMUL_D_MMR6_DESC
919  : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
920class FDIV_S_MMR6_DESC
921  : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
922class FDIV_D_MMR6_DESC
923  : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
924class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
925                                            II_MADDF_S>, HARDFLOAT;
926class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
927                                            II_MADDF_D>, HARDFLOAT;
928class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
929                                            II_MSUBF_S>, HARDFLOAT;
930class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
931                                            II_MSUBF_D>, HARDFLOAT;
932
933class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
934                               RegisterOperand SrcRC, InstrItinClass Itin,
935                               SDPatternOperator OpNode = null_frag>
936                               : HARDFLOAT, NeverHasSideEffects {
937  dag OutOperandList = (outs DstRC:$ft);
938  dag InOperandList = (ins SrcRC:$fs);
939  string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
940  list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
941  InstrItinClass Itinerary = Itin;
942  Format Form = FrmFR;
943}
944class FMOV_S_MMR6_DESC
945  : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
946class FMOV_D_MMR6_DESC
947  : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
948class FNEG_S_MMR6_DESC
949  : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
950class FNEG_D_MMR6_DESC
951  : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
952
953class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
954                        HARDFLOAT;
955class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
956                        HARDFLOAT;
957class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
958                        HARDFLOAT;
959class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
960                        HARDFLOAT;
961
962class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
963                         HARDFLOAT;
964class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
965                         HARDFLOAT;
966class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
967                         HARDFLOAT;
968class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
969                         HARDFLOAT;
970
971class CVT_MMR6_DESC_BASE<
972    string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
973    InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
974    : HARDFLOAT, NeverHasSideEffects {
975  dag OutOperandList = (outs DstRC:$ft);
976  dag InOperandList = (ins SrcRC:$fs);
977  string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
978  list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
979  InstrItinClass Itinerary = Itin;
980  Format Form = FrmFR;
981}
982
983class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
984                                             II_CVT>;
985class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
986                                             II_CVT>;
987class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
988                                             II_CVT>;
989class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
990                                             II_CVT>;
991class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
992                                             II_CVT>;
993class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
994                                             II_CVT>;
995class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
996                                             II_CVT>, FGR_64;
997class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
998                                             II_CVT>;
999class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
1000                                             II_CVT>;
1001class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
1002                                             II_CVT>, FGR_64;
1003
1004multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
1005                       RegisterOperand FGROpnd, InstrItinClass Itin> {
1006  def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1007      !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
1008      CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT,
1009      ISA_MICROMIPS32R6;
1010  def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1011      !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
1012      CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT,
1013      ISA_MICROMIPS32R6;
1014  def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1015      !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
1016      CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT,
1017      ISA_MICROMIPS32R6;
1018  def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1019      !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
1020      CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT,
1021      ISA_MICROMIPS32R6;
1022  def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1023      !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
1024      CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT,
1025      ISA_MICROMIPS32R6;
1026  def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1027      !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
1028      CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT,
1029      ISA_MICROMIPS32R6;
1030  def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1031      !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
1032      CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT,
1033      ISA_MICROMIPS32R6;
1034  def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1035      !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
1036      CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT,
1037      ISA_MICROMIPS32R6;
1038  def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1039      !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
1040      CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT,
1041      ISA_MICROMIPS32R6;
1042  def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1043      !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
1044      CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT,
1045      ISA_MICROMIPS32R6;
1046  def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1047      !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
1048      CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT,
1049      ISA_MICROMIPS32R6;
1050  def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1051      !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
1052      CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT,
1053      ISA_MICROMIPS32R6;
1054  def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1055      !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
1056      CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT,
1057      ISA_MICROMIPS32R6;
1058  def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1059      !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
1060      CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT,
1061      ISA_MICROMIPS32R6;
1062  def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1063      !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
1064      CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT,
1065      ISA_MICROMIPS32R6;
1066  def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1067      !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
1068      CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT,
1069      ISA_MICROMIPS32R6;
1070}
1071
1072class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
1073                             RegisterOperand SrcRC, InstrItinClass Itin,
1074                             SDPatternOperator OpNode = null_frag>
1075    : HARDFLOAT, NeverHasSideEffects {
1076  dag OutOperandList = (outs DstRC:$ft);
1077  dag InOperandList  = (ins SrcRC:$fs);
1078  string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
1079  list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
1080  InstrItinClass Itinerary = Itin;
1081  Format Form = FrmFR;
1082  list<Predicate> EncodingPredicates = [HasStdEnc];
1083}
1084
1085class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
1086                                                II_ABS, fabs>;
1087class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
1088                                                II_ABS, fabs>;
1089class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
1090                                                    FGR32Opnd, II_FLOOR>;
1091class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
1092                                                    FGR64Opnd, II_FLOOR>;
1093class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
1094                                                    FGR32Opnd, II_FLOOR>;
1095class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
1096                                                    AFGR64Opnd, II_FLOOR>;
1097class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
1098                                                   FGR32Opnd, II_CEIL>;
1099class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
1100                                                   FGR64Opnd, II_CEIL>;
1101class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
1102                                                   FGR32Opnd, II_CEIL>;
1103class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
1104                                                   AFGR64Opnd, II_CEIL>;
1105class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
1106                                                    FGR32Opnd, II_TRUNC>;
1107class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
1108                                                    FGR64Opnd, II_TRUNC>;
1109class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
1110                                                    FGR32Opnd, II_TRUNC>;
1111class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
1112                                                    AFGR64Opnd, II_TRUNC>;
1113class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
1114                                                 II_SQRT_S, fsqrt>;
1115class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
1116                                                 II_SQRT_D, fsqrt>;
1117class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
1118                                                   FGR32Opnd, II_ROUND>;
1119class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
1120                                                   FGR64Opnd, II_ROUND>;
1121class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
1122                                                   FGR32Opnd, II_ROUND>;
1123class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
1124                                                   FGR64Opnd, II_ROUND>;
1125
1126class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
1127class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D> {
1128  // We must insert a SUBREG_TO_REG around $fd_in
1129  bit usesCustomInserter = 1;
1130}
1131
1132class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
1133                                              II_SELCCZ_S>;
1134class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
1135                                              II_SELCCZ_D>;
1136class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
1137                                              II_SELCCZ_S>;
1138class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
1139                                              II_SELCCZ_D>;
1140class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
1141                                              II_RINT_S>;
1142class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
1143                                              II_RINT_S>;
1144class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
1145                                              II_CLASS_S>;
1146class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
1147                                              II_CLASS_S>;
1148
1149class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
1150                           InstrItinClass Itin>
1151    : Store<opstr, RO>, MMR6Arch<opstr> {
1152  let DecoderMethod = "DecodeMemMMImm16";
1153  InstrItinClass Itinerary = Itin;
1154}
1155class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
1156
1157class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
1158                               InstrItinClass Itin>
1159    : MMR6Arch<instr_asm>, MipsR6Inst {
1160  dag OutOperandList = (outs);
1161  dag InOperandList = (ins RO:$rt, mem_simm9:$addr);
1162  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
1163  string DecoderMethod = "DecodeStoreEvaOpMM";
1164  bit mayStore = 1;
1165  InstrItinClass Itinerary = Itin;
1166}
1167class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd, II_SBE>;
1168class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd, II_SCE>;
1169class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
1170class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd, II_SHE>;
1171class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
1172                                   InstrItinClass Itin>
1173    : MMR6Arch<instr_asm>, MipsR6Inst {
1174  dag OutOperandList = (outs RO:$rt);
1175  dag InOperandList = (ins mem_simm9:$addr);
1176  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
1177  string DecoderMethod = "DecodeMemMMImm9";
1178  bit mayLoad = 1;
1179  InstrItinClass Itinerary = Itin;
1180}
1181class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd, II_LLE>;
1182class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd, II_LWE>;
1183class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
1184      MMR6Arch<"addu16"> {
1185  int AddedComplexity = 1;
1186}
1187class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
1188      MMR6Arch<"and16"> {
1189  int AddedComplexity = 1;
1190}
1191class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
1192      MMR6Arch<"andi16">;
1193class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
1194  int AddedComplexity = 1;
1195}
1196class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
1197      MMR6Arch<"or16"> {
1198  int AddedComplexity = 1;
1199}
1200class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
1201      MMR6Arch<"sll16">;
1202class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
1203      MMR6Arch<"srl16">;
1204class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">,
1205      MicroMipsR6Inst16;
1206class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
1207      MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
1208class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
1209      MicroMipsR6Inst16;
1210class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">,
1211      MicroMipsR6Inst16;
1212class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
1213      MMR6Arch<"subu16">, MicroMipsR6Inst16 {
1214  int AddedComplexity = 1;
1215}
1216class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
1217      MMR6Arch<"xor16"> {
1218  int AddedComplexity = 1;
1219}
1220
1221class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
1222  dag OutOperandList = (outs GPR32Opnd:$rt);
1223  dag InOperandList = (ins mem:$addr);
1224  string AsmString = "lw\t$rt, $addr";
1225  let DecoderMethod = "DecodeMemMMImm16";
1226  let canFoldAsLoad = 1;
1227  let mayLoad = 1;
1228  list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
1229  InstrItinClass Itinerary = II_LW;
1230}
1231
1232class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
1233  dag OutOperandList = (outs GPR32Opnd:$rt);
1234  dag InOperandList = (ins uimm16:$imm16);
1235  string AsmString = "lui\t$rt, $imm16";
1236  list<dag> Pattern = [];
1237  bit hasSideEffects = 0;
1238  bit isReMaterializable = 1;
1239  InstrItinClass Itinerary = II_LUI;
1240  Format Form = FrmI;
1241}
1242
1243class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
1244  dag OutOperandList = (outs);
1245  dag InOperandList = (ins uimm5:$stype);
1246  string AsmString = !strconcat("sync", "\t$stype");
1247  list<dag> Pattern = [(MipsSync immZExt5:$stype)];
1248  InstrItinClass Itinerary = II_SYNC;
1249  bit HasSideEffects = 1;
1250}
1251
1252class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
1253  let DecoderMethod = "DecodeSynciR6";
1254}
1255
1256class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
1257  dag OutOperandList = (outs GPR32Opnd:$rt);
1258  dag InOperandList = (ins GPR32Opnd:$rd);
1259  string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
1260  InstrItinClass Itinerary = II_RDPGPR;
1261}
1262
1263class SDBBP_MMR6_DESC : MipsR6Inst {
1264  dag OutOperandList = (outs);
1265  dag InOperandList = (ins uimm20:$code_);
1266  string AsmString = !strconcat("sdbbp", "\t$code_");
1267  list<dag> Pattern = [];
1268  InstrItinClass Itinerary = II_SDBBP;
1269}
1270
1271class LWM16_MMR6_DESC
1272    : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
1273                      !strconcat("lwm16", "\t$rt, $addr"), [],
1274                      II_LWM, FrmI>,
1275      MMR6Arch<"lwm16">, MicroMipsR6Inst16 {
1276  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1277  let mayLoad = 1;
1278  ComplexPattern Addr = addr;
1279}
1280
1281class SWM16_MMR6_DESC
1282    : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
1283                      !strconcat("swm16", "\t$rt, $addr"), [],
1284                      II_SWM, FrmI>,
1285      MMR6Arch<"swm16">, MicroMipsR6Inst16 {
1286  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1287  let mayStore = 1;
1288  ComplexPattern Addr = addr;
1289}
1290
1291class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
1292                          SDPatternOperator OpNode, InstrItinClass Itin,
1293                          Operand MemOpnd>
1294    : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
1295                      !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
1296      MMR6Arch<opstr>, MicroMipsR6Inst16 {
1297  let DecoderMethod = "DecodeMemMMImm4";
1298  let mayStore = 1;
1299}
1300class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
1301                                           truncstorei8, II_SB, mem_mm_4>;
1302class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
1303                                           truncstorei16, II_SH, mem_mm_4_lsl1>;
1304class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
1305                                           store, II_SW, mem_mm_4_lsl2>;
1306
1307class SWSP_MMR6_DESC
1308    : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
1309                      !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
1310      MMR6Arch<"sw">, MicroMipsR6Inst16 {
1311  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
1312  let mayStore = 1;
1313}
1314
1315class JALRC_HB_MMR6_DESC {
1316  dag OutOperandList = (outs GPR32Opnd:$rt);
1317  dag InOperandList = (ins GPR32Opnd:$rs);
1318  string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
1319  list<dag> Pattern = [];
1320  InstrItinClass Itinerary = II_JALR_HB;
1321  Format Form = FrmJ;
1322  bit isIndirectBranch = 1;
1323  bit hasDelaySlot = 0;
1324}
1325
1326class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1327  dag OutOperandList = (outs);
1328  dag InOperandList = (ins);
1329  string AsmString = opstr;
1330  list<dag> Pattern = [];
1331  InstrItinClass Itinerary = Itin;
1332}
1333
1334class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
1335class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
1336
1337class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1338  dag OutOperandList = (outs GPR32Opnd:$rs);
1339  dag InOperandList = (ins);
1340  string AsmString = !strconcat(opstr, "\t$rs");
1341  list<dag> Pattern = [];
1342  InstrItinClass Itinerary = Itin;
1343  bit hasUnModeledSideEffects = 1;
1344}
1345
1346class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
1347class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
1348
1349class BEQZC_MMR6_DESC
1350    : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
1351      MMR6Arch<"beqzc">;
1352class BNEZC_MMR6_DESC
1353    : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
1354      MMR6Arch<"bnezc">;
1355
1356class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
1357    InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
1358           !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
1359    HARDFLOAT, BRANCH_DESC_BASE {
1360  list<Register> Defs = [AT];
1361}
1362
1363class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
1364class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
1365
1366class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
1367    : BRANCH_DESC_BASE {
1368  dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
1369  dag OutOperandList = (outs);
1370  string AsmString = !strconcat(opstr, "\t$rt, $offset");
1371  list<Register> Defs = [AT];
1372  InstrItinClass Itinerary = Itin;
1373}
1374
1375class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
1376class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
1377
1378class EXT_MMR6_DESC {
1379  dag OutOperandList = (outs GPR32Opnd:$rt);
1380  dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
1381  string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
1382  list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
1383                       imm:$size))];
1384  InstrItinClass Itinerary = II_EXT;
1385  Format Form = FrmR;
1386  string BaseOpcode = "ext";
1387}
1388
1389class INS_MMR6_DESC {
1390  dag OutOperandList = (outs GPR32Opnd:$rt);
1391  dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
1392                       GPR32Opnd:$src);
1393  string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
1394  list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
1395                       imm:$size, GPR32Opnd:$src))];
1396  InstrItinClass Itinerary = II_INS;
1397  Format Form = FrmR;
1398  string BaseOpcode = "ins";
1399  string Constraints = "$src = $rt";
1400}
1401
1402class JALRC_MMR6_DESC {
1403  dag OutOperandList = (outs GPR32Opnd:$rt);
1404  dag InOperandList = (ins GPR32Opnd:$rs);
1405  string AsmString = !strconcat("jalrc", "\t$rt, $rs");
1406  list<dag> Pattern = [];
1407  InstrItinClass Itinerary = II_JALRC;
1408  bit isCall = 1;
1409  bit hasDelaySlot = 0;
1410  list<Register> Defs = [RA];
1411}
1412
1413class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
1414                               RegisterOperand GPROpnd>
1415    : BRANCH_DESC_BASE {
1416  dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
1417  dag OutOperandList = (outs);
1418  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
1419  list<Register> Defs = [AT];
1420  InstrItinClass Itinerary = II_BCCC;
1421}
1422
1423class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
1424class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>;
1425
1426//===----------------------------------------------------------------------===//
1427//
1428// Instruction Definitions
1429//
1430//===----------------------------------------------------------------------===//
1431
1432let DecoderNamespace = "MicroMipsR6" in {
1433def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
1434def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
1435def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
1436def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
1437                   ISA_MICROMIPS32R6;
1438def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
1439                  ISA_MICROMIPS32R6;
1440def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
1441def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
1442def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
1443def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
1444def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
1445def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
1446def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
1447def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
1448def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC,
1449                 ISA_MICROMIPS32R6;
1450def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
1451                   ISA_MICROMIPS32R6;
1452def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC,
1453                 ISA_MICROMIPS32R6;
1454def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
1455                   ISA_MICROMIPS32R6;
1456def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
1457                   ISA_MICROMIPS32R6;
1458def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
1459                   ISA_MICROMIPS32R6;
1460def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
1461                   ISA_MICROMIPS32R6;
1462def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
1463def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
1464def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
1465def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
1466def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
1467def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
1468def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
1469def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
1470def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
1471def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
1472def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
1473def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
1474                  ISA_MICROMIPS32R6;
1475def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
1476                   ISA_MICROMIPS32R6;
1477def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
1478def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
1479def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
1480def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
1481                      ISA_MICROMIPS32R6;
1482def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
1483def LWP_MMR6 : StdMMR6Rel, LWP_MMR6_ENC, LWP_MMR6_DESC, ISA_MICROMIPS32R6;
1484def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
1485def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1486def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
1487def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
1488def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
1489def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1490def MTHC1_D32_MMR6 : StdMMR6Rel, MTHC1_D32_MMR6_DESC, MTHC1_MMR6_ENC, ISA_MICROMIPS32R6;
1491let DecoderNamespace = "MicroMips32r6FP64" in {
1492  def MTHC1_D64_MMR6 : R6MMR6Rel, MTHC1_D64_MMR6_DESC, MTHC1_MMR6_ENC,
1493                       ISA_MICROMIPS32R6;
1494}
1495def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1496def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
1497def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
1498def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
1499def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1500def MFHC1_D32_MMR6 : StdMMR6Rel, MFHC1_D32_MMR6_DESC, MFHC1_MMR6_ENC,
1501                     ISA_MICROMIPS32R6;
1502let DecoderNamespace = "MicroMips32r6FP64" in {
1503  def MFHC1_D64_MMR6 : StdMMR6Rel, MFHC1_D64_MMR6_DESC, MFHC1_MMR6_ENC,
1504                       ISA_MICROMIPS32R6;
1505}
1506def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1507def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
1508def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
1509def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
1510def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
1511def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
1512def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
1513def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
1514def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
1515def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
1516def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
1517def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
1518def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
1519def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
1520def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
1521                  ISA_MICROMIPS32R6;
1522def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1523                  ISA_MICROMIPS32R6;
1524def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1525def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1526def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1527def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1528def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1529def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1530def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1531def SWP_MMR6 : StdMMR6Rel, SWP_MMR6_ENC, SWP_MMR6_DESC, ISA_MICROMIPS32R6;
1532def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
1533def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
1534                  ISA_MICROMIPS32R6;
1535def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1536                  ISA_MICROMIPS32R6;
1537def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1538def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1539def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1540def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6;
1541def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6;
1542def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1543def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1544def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1545def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1546def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1547def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1548def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1549                  ISA_MICROMIPS32R6;
1550def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1551def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1552def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1553let DecoderMethod = "DecodeMemMMImm16" in {
1554  def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1555}
1556let DecoderMethod = "DecodeMemMMImm9" in {
1557  def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
1558}
1559/// Floating Point Instructions
1560def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1561                  ISA_MICROMIPS32R6;
1562def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
1563                  ISA_MICROMIPS32R6;
1564def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1565                  ISA_MICROMIPS32R6;
1566def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
1567                  ISA_MICROMIPS32R6;
1568def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1569                  ISA_MICROMIPS32R6;
1570def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
1571                  ISA_MICROMIPS32R6;
1572def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1573                  ISA_MICROMIPS32R6;
1574def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
1575                  ISA_MICROMIPS32R6;
1576def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1577                   ISA_MICROMIPS32R6;
1578def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1579                   ISA_MICROMIPS32R6;
1580def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1581                   ISA_MICROMIPS32R6;
1582def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1583                   ISA_MICROMIPS32R6;
1584def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1585                  ISA_MICROMIPS32R6;
1586def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1587                  ISA_MICROMIPS32R6;
1588def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1589                  ISA_MICROMIPS32R6;
1590def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
1591                  ISA_MICROMIPS32R6;
1592def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1593def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1594def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1595def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1596def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1597                  ISA_MICROMIPS32R6;
1598def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1599                  ISA_MICROMIPS32R6;
1600def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1601                  ISA_MICROMIPS32R6;
1602def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1603                  ISA_MICROMIPS32R6;
1604def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1605                   ISA_MICROMIPS32R6;
1606def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1607                   ISA_MICROMIPS32R6;
1608def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1609                   ISA_MICROMIPS32R6;
1610def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
1611                   ISA_MICROMIPS32R6;
1612def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
1613                   ISA_MICROMIPS32R6;
1614def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
1615                   ISA_MICROMIPS32R6;
1616def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1617                   ISA_MICROMIPS32R6;
1618def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
1619                   ISA_MICROMIPS32R6;
1620def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1621                   ISA_MICROMIPS32R6;
1622def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1623                   ISA_MICROMIPS32R6;
1624defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
1625defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
1626def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
1627def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
1628def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1629                     ISA_MICROMIPS32R6;
1630def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1631                     ISA_MICROMIPS32R6;
1632def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1633                     ISA_MICROMIPS32R6;
1634def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1635                     ISA_MICROMIPS32R6;
1636def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1637                    ISA_MICROMIPS32R6;
1638def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1639                    ISA_MICROMIPS32R6;
1640def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1641                    ISA_MICROMIPS32R6;
1642def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1643                    ISA_MICROMIPS32R6;
1644def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1645                     ISA_MICROMIPS32R6;
1646def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1647                     ISA_MICROMIPS32R6;
1648def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1649                     ISA_MICROMIPS32R6;
1650def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1651                     ISA_MICROMIPS32R6;
1652def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
1653                  ISA_MICROMIPS32R6;
1654def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
1655                  ISA_MICROMIPS32R6;
1656def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1657def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
1658def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
1659def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1660def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
1661def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
1662def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
1663def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1664def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1665def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1666                  ISA_MICROMIPS32R6;
1667def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1668                  ISA_MICROMIPS32R6;
1669def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1670                  ISA_MICROMIPS32R6;
1671def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1672                  ISA_MICROMIPS32R6;
1673def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1674                  ISA_MICROMIPS32R6;
1675def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1676                  ISA_MICROMIPS32R6;
1677def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1678                  ISA_MICROMIPS32R6;
1679def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1680                   ISA_MICROMIPS32R6;
1681def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1682                ISA_MICROMIPS32R6;
1683def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1684                  ISA_MICROMIPS32R6;
1685def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1686                   ISA_MICROMIPS32R6;
1687def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1688                  ISA_MICROMIPS32R6;
1689def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1690                 ISA_MICROMIPS32R6;
1691def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
1692                    ISA_MICROMIPS32R6;
1693def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
1694def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
1695def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1696def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1697                  ISA_MICROMIPS32R6;
1698def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
1699def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1700                     ISA_MICROMIPS32R6;
1701def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1702                     ISA_MICROMIPS32R6;
1703def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1704                     ISA_MICROMIPS32R6;
1705def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1706                     ISA_MICROMIPS32R6;
1707def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1708def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1709def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1710                    ISA_MICROMIPS32R6;
1711def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1712                    ISA_MICROMIPS32R6;
1713def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC,
1714                    ISA_MICROMIPS32R6;
1715def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC,
1716                    ISA_MICROMIPS32R6;
1717def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1718                   ISA_MICROMIPS32R6;
1719def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1720                   ISA_MICROMIPS32R6;
1721def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
1722                  ISA_MICROMIPS32R6;
1723def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
1724                   ISA_MICROMIPS32R6;
1725def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
1726def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
1727def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
1728                   ISA_MICROMIPS32R6;
1729def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
1730                   ISA_MICROMIPS32R6;
1731def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
1732                   ISA_MICROMIPS32R6;
1733def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
1734                   ISA_MICROMIPS32R6;
1735let DecoderNamespace = "MicroMips32r6FP64" in {
1736  def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
1737                      ISA_MICROMIPS32R6 {
1738    let BaseOpcode = "LDC164";
1739  }
1740  def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
1741                      ISA_MICROMIPS32R6;
1742}
1743def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1744def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1745def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1746def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1747}
1748
1749def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
1750                MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">;
1751def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6,
1752                MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">;
1753def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
1754def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
1755def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
1756def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
1757def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6,
1758                DecodeDisambiguates<"POP35GroupBranchMMR6">;
1759def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6,
1760                DecodeDisambiguates<"POP37GroupBranchMMR6">;
1761def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1762def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1763def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1764def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1765def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
1766                   ISA_MICROMIPS32R6;
1767def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
1768                   ISA_MICROMIPS32R6;
1769def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
1770                   ISA_MICROMIPS32R6;
1771def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
1772                   ISA_MICROMIPS32R6;
1773
1774//===----------------------------------------------------------------------===//
1775//
1776// MicroMips instruction aliases
1777//
1778//===----------------------------------------------------------------------===//
1779
1780def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1781def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1782def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1783def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1784                                      !strconcat("b", "\t$offset")> {
1785  string DecoderNamespace = "MicroMipsR6";
1786}
1787def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1788def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1789def : MipsInstAlias<"rdhwr $rt, $rs",
1790                    (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1791                    ISA_MICROMIPS32R6;
1792def : MipsInstAlias<"mtc0 $rt, $rs",
1793                    (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1794                    ISA_MICROMIPS32R6;
1795def : MipsInstAlias<"mthc0 $rt, $rs",
1796                    (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1797                    ISA_MICROMIPS32R6;
1798def : MipsInstAlias<"mfc0 $rt, $rs",
1799                    (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1800                    ISA_MICROMIPS32R6;
1801def : MipsInstAlias<"mfhc0 $rt, $rs",
1802                    (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1803                    ISA_MICROMIPS32R6;
1804def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
1805                    ISA_MICROMIPS32R6;
1806def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1807def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1808def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
1809      ISA_MICROMIPS32R6;
1810def : MipsInstAlias<"and $rs, $rt, $imm",
1811                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1812                    ISA_MICROMIPS32R6;
1813def : MipsInstAlias<"and $rs, $imm",
1814                    (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1815                    ISA_MICROMIPS32R6;
1816def : MipsInstAlias<"or $rs, $rt, $imm",
1817                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1818                    ISA_MICROMIPS32R6;
1819def : MipsInstAlias<"or $rs, $imm",
1820                    (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1821                    ISA_MICROMIPS32R6;
1822def : MipsInstAlias<"xor $rs, $rt, $imm",
1823                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1824                    ISA_MICROMIPS32R6;
1825def : MipsInstAlias<"xor $rs, $imm",
1826                    (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1827                    ISA_MICROMIPS32R6;
1828def : MipsInstAlias<"not $rt, $rs",
1829                    (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1830                    ISA_MICROMIPS32R6;
1831def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1832                    ISA_MICROMIPS32R6;
1833def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1834                    ISA_MICROMIPS32R6;
1835
1836//===----------------------------------------------------------------------===//
1837//
1838// MicroMips arbitrary patterns that map to one or more instructions
1839//
1840//===----------------------------------------------------------------------===//
1841
1842def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1843              (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
1844def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1845              (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
1846
1847def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1848              (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond),
1849                     (SELEQZ_MMR6 i32:$f, i32:$cond))>,
1850              ISA_MICROMIPS32R6;
1851def : MipsPat<(select i32:$cond, i32:$t, immz),
1852              (SELNEZ_MMR6 i32:$t, i32:$cond)>,
1853              ISA_MICROMIPS32R6;
1854def : MipsPat<(select i32:$cond, immz, i32:$f),
1855              (SELEQZ_MMR6 i32:$f, i32:$cond)>,
1856              ISA_MICROMIPS32R6;
1857
1858defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
1859                      SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
1860
1861defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1862defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1863
1864def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1865              (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
1866              ISA_MICROMIPS32R6;
1867def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1868              (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1869def : MipsPat<(i32 immZExt16:$imm),
1870              (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1871def : MipsPat<(not GPRMM16:$in),
1872              (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
1873def : MipsPat<(not GPR32:$in),
1874              (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
1875// Patterns for load with a reg+imm operand.
1876let AddedComplexity = 41 in {
1877  def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
1878  def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
1879}
1880
1881def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1882