1 //===- MipsOptionRecord.cpp - Abstraction for storing information ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MipsOptionRecord.h" 11 #include "MipsABIInfo.h" 12 #include "MipsELFStreamer.h" 13 #include "MipsTargetStreamer.h" 14 #include "llvm/BinaryFormat/ELF.h" 15 #include "llvm/MC/MCAssembler.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCRegisterInfo.h" 18 #include "llvm/MC/MCSectionELF.h" 19 #include <cassert> 20 21 using namespace llvm; 22 23 void MipsRegInfoRecord::EmitMipsOptionRecord() { 24 MCAssembler &MCA = Streamer->getAssembler(); 25 MipsTargetStreamer *MTS = 26 static_cast<MipsTargetStreamer *>(Streamer->getTargetStreamer()); 27 28 Streamer->PushSection(); 29 30 // We need to distinguish between N64 and the rest because at the moment 31 // we don't emit .Mips.options for other ELFs other than N64. 32 // Since .reginfo has the same information as .Mips.options (ODK_REGINFO), 33 // we can use the same abstraction (MipsRegInfoRecord class) to handle both. 34 if (MTS->getABI().IsN64()) { 35 // The EntrySize value of 1 seems strange since the records are neither 36 // 1-byte long nor fixed length but it matches the value GAS emits. 37 MCSectionELF *Sec = 38 Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS, 39 ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP, 1, ""); 40 MCA.registerSection(*Sec); 41 Sec->setAlignment(8); 42 Streamer->SwitchSection(Sec); 43 44 Streamer->EmitIntValue(ELF::ODK_REGINFO, 1); // kind 45 Streamer->EmitIntValue(40, 1); // size 46 Streamer->EmitIntValue(0, 2); // section 47 Streamer->EmitIntValue(0, 4); // info 48 Streamer->EmitIntValue(ri_gprmask, 4); 49 Streamer->EmitIntValue(0, 4); // pad 50 Streamer->EmitIntValue(ri_cprmask[0], 4); 51 Streamer->EmitIntValue(ri_cprmask[1], 4); 52 Streamer->EmitIntValue(ri_cprmask[2], 4); 53 Streamer->EmitIntValue(ri_cprmask[3], 4); 54 Streamer->EmitIntValue(ri_gp_value, 8); 55 } else { 56 MCSectionELF *Sec = Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, 57 ELF::SHF_ALLOC, 24, ""); 58 MCA.registerSection(*Sec); 59 Sec->setAlignment(MTS->getABI().IsN32() ? 8 : 4); 60 Streamer->SwitchSection(Sec); 61 62 Streamer->EmitIntValue(ri_gprmask, 4); 63 Streamer->EmitIntValue(ri_cprmask[0], 4); 64 Streamer->EmitIntValue(ri_cprmask[1], 4); 65 Streamer->EmitIntValue(ri_cprmask[2], 4); 66 Streamer->EmitIntValue(ri_cprmask[3], 4); 67 assert((ri_gp_value & 0xffffffff) == ri_gp_value); 68 Streamer->EmitIntValue(ri_gp_value, 4); 69 } 70 71 Streamer->PopSection(); 72 } 73 74 void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg, 75 const MCRegisterInfo *MCRegInfo) { 76 unsigned Value = 0; 77 78 for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid(); 79 ++SubRegIt) { 80 unsigned CurrentSubReg = *SubRegIt; 81 82 unsigned EncVal = MCRegInfo->getEncodingValue(CurrentSubReg); 83 Value |= 1 << EncVal; 84 85 if (GPR32RegClass->contains(CurrentSubReg) || 86 GPR64RegClass->contains(CurrentSubReg)) 87 ri_gprmask |= Value; 88 else if (COP0RegClass->contains(CurrentSubReg)) 89 ri_cprmask[0] |= Value; 90 // MIPS COP1 is the FPU. 91 else if (FGR32RegClass->contains(CurrentSubReg) || 92 FGR64RegClass->contains(CurrentSubReg) || 93 AFGR64RegClass->contains(CurrentSubReg) || 94 MSA128BRegClass->contains(CurrentSubReg)) 95 ri_cprmask[1] |= Value; 96 else if (COP2RegClass->contains(CurrentSubReg)) 97 ri_cprmask[2] |= Value; 98 else if (COP3RegClass->contains(CurrentSubReg)) 99 ri_cprmask[3] |= Value; 100 } 101 } 102