1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsMCTargetDesc.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCAsmInfo.h"
18 #include "MipsMCNaCl.h"
19 #include "MipsTargetStreamer.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCCodeGenInfo.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrAnalysis.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/MC/MachineLocation.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/FormattedStream.h"
31 #include "llvm/Support/TargetRegistry.h"
32 
33 using namespace llvm;
34 
35 #define GET_INSTRINFO_MC_DESC
36 #include "MipsGenInstrInfo.inc"
37 
38 #define GET_SUBTARGETINFO_MC_DESC
39 #include "MipsGenSubtargetInfo.inc"
40 
41 #define GET_REGINFO_MC_DESC
42 #include "MipsGenRegisterInfo.inc"
43 
44 /// Select the Mips CPU for the given triple and cpu name.
45 /// FIXME: Merge with the copy in MipsSubtarget.cpp
46 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
47   if (CPU.empty() || CPU == "generic") {
48     if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
49       CPU = "mips32";
50     else
51       CPU = "mips64";
52   }
53   return CPU;
54 }
55 
56 static MCInstrInfo *createMipsMCInstrInfo() {
57   MCInstrInfo *X = new MCInstrInfo();
58   InitMipsMCInstrInfo(X);
59   return X;
60 }
61 
62 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
63   MCRegisterInfo *X = new MCRegisterInfo();
64   InitMipsMCRegisterInfo(X, Mips::RA);
65   return X;
66 }
67 
68 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
69                                                   StringRef CPU, StringRef FS) {
70   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
71   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
72 }
73 
74 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
75                                       const Triple &TT) {
76   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
77 
78   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
79   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
80   MAI->addInitialFrameState(Inst);
81 
82   return MAI;
83 }
84 
85 static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
86                                               CodeModel::Model CM,
87                                               CodeGenOpt::Level OL) {
88   MCCodeGenInfo *X = new MCCodeGenInfo();
89   X->initMCCodeGenInfo(RM, CM, OL);
90   return X;
91 }
92 
93 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
94                                               unsigned SyntaxVariant,
95                                               const MCAsmInfo &MAI,
96                                               const MCInstrInfo &MII,
97                                               const MCRegisterInfo &MRI) {
98   return new MipsInstPrinter(MAI, MII, MRI);
99 }
100 
101 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
102                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
103                                     MCCodeEmitter *Emitter, bool RelaxAll) {
104   MCStreamer *S;
105   if (!T.isOSNaCl())
106     S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
107   else
108     S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
109   return S;
110 }
111 
112 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
113                                                      formatted_raw_ostream &OS,
114                                                      MCInstPrinter *InstPrint,
115                                                      bool isVerboseAsm) {
116   return new MipsTargetAsmStreamer(S, OS);
117 }
118 
119 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
120   return new MipsTargetStreamer(S);
121 }
122 
123 static MCTargetStreamer *
124 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
125   return new MipsTargetELFStreamer(S, STI);
126 }
127 
128 namespace {
129 
130 class MipsMCInstrAnalysis : public MCInstrAnalysis {
131 public:
132   MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
133 
134   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
135                       uint64_t &Target) const override {
136     unsigned NumOps = Inst.getNumOperands();
137     if (NumOps == 0)
138       return false;
139     switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
140     case MCOI::OPERAND_UNKNOWN:
141     case MCOI::OPERAND_IMMEDIATE:
142       // jal, bal ...
143       Target = Inst.getOperand(NumOps - 1).getImm();
144       return true;
145     case MCOI::OPERAND_PCREL:
146       // b, j, beq ...
147       Target = Addr + Inst.getOperand(NumOps - 1).getImm();
148       return true;
149     default:
150       return false;
151     }
152   }
153 };
154 }
155 
156 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
157   return new MipsMCInstrAnalysis(Info);
158 }
159 
160 extern "C" void LLVMInitializeMipsTargetMC() {
161   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
162                     &TheMips64elTarget}) {
163     // Register the MC asm info.
164     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
165 
166     // Register the MC codegen info.
167     TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
168 
169     // Register the MC instruction info.
170     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
171 
172     // Register the MC register info.
173     TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
174 
175     // Register the elf streamer.
176     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
177 
178     // Register the asm target streamer.
179     TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
180 
181     TargetRegistry::RegisterNullTargetStreamer(*T,
182                                                createMipsNullTargetStreamer);
183 
184     // Register the MC subtarget info.
185     TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
186 
187     // Register the MC instruction analyzer.
188     TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis);
189 
190     // Register the MCInstPrinter.
191     TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
192 
193     TargetRegistry::RegisterObjectTargetStreamer(
194         *T, createMipsObjectTargetStreamer);
195   }
196 
197   // Register the MC Code Emitter
198   for (Target *T : {&TheMipsTarget, &TheMips64Target})
199     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
200 
201   for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
202     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
203 
204   // Register the asm backend.
205   TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
206                                        createMipsAsmBackendEB32);
207   TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
208                                        createMipsAsmBackendEL32);
209   TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
210                                        createMipsAsmBackendEB64);
211   TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
212                                        createMipsAsmBackendEL64);
213 
214 }
215