1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "InstPrinter/MipsInstPrinter.h"
15 #include "MipsELFStreamer.h"
16 #include "MipsMCAsmInfo.h"
17 #include "MipsMCNaCl.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetStreamer.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCCodeGenInfo.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrAnalysis.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/MC/MachineLocation.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/FormattedStream.h"
32 #include "llvm/Support/TargetRegistry.h"
33 
34 using namespace llvm;
35 
36 #define GET_INSTRINFO_MC_DESC
37 #include "MipsGenInstrInfo.inc"
38 
39 #define GET_SUBTARGETINFO_MC_DESC
40 #include "MipsGenSubtargetInfo.inc"
41 
42 #define GET_REGINFO_MC_DESC
43 #include "MipsGenRegisterInfo.inc"
44 
45 /// Select the Mips CPU for the given triple and cpu name.
46 /// FIXME: Merge with the copy in MipsSubtarget.cpp
47 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
48   if (CPU.empty() || CPU == "generic") {
49     if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
50       CPU = "mips32";
51     else
52       CPU = "mips64";
53   }
54   return CPU;
55 }
56 
57 static MCInstrInfo *createMipsMCInstrInfo() {
58   MCInstrInfo *X = new MCInstrInfo();
59   InitMipsMCInstrInfo(X);
60   return X;
61 }
62 
63 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
64   MCRegisterInfo *X = new MCRegisterInfo();
65   InitMipsMCRegisterInfo(X, Mips::RA);
66   return X;
67 }
68 
69 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
70                                                   StringRef CPU, StringRef FS) {
71   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
72   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
73 }
74 
75 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
76                                       const Triple &TT) {
77   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
78 
79   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
80   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
81   MAI->addInitialFrameState(Inst);
82 
83   return MAI;
84 }
85 
86 static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
87                                               CodeModel::Model CM,
88                                               CodeGenOpt::Level OL) {
89   MCCodeGenInfo *X = new MCCodeGenInfo();
90   if (CM == CodeModel::JITDefault)
91     RM = Reloc::Static;
92   else if (RM == Reloc::Default)
93     RM = Reloc::PIC_;
94   X->initMCCodeGenInfo(RM, CM, OL);
95   return X;
96 }
97 
98 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
99                                               unsigned SyntaxVariant,
100                                               const MCAsmInfo &MAI,
101                                               const MCInstrInfo &MII,
102                                               const MCRegisterInfo &MRI) {
103   return new MipsInstPrinter(MAI, MII, MRI);
104 }
105 
106 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
107                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
108                                     MCCodeEmitter *Emitter, bool RelaxAll) {
109   MCStreamer *S;
110   if (!T.isOSNaCl())
111     S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
112   else
113     S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
114   return S;
115 }
116 
117 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
118                                                      formatted_raw_ostream &OS,
119                                                      MCInstPrinter *InstPrint,
120                                                      bool isVerboseAsm) {
121   return new MipsTargetAsmStreamer(S, OS);
122 }
123 
124 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
125   return new MipsTargetStreamer(S);
126 }
127 
128 static MCTargetStreamer *
129 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
130   return new MipsTargetELFStreamer(S, STI);
131 }
132 
133 namespace {
134 
135 class MipsMCInstrAnalysis : public MCInstrAnalysis {
136 public:
137   MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
138 
139   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
140                       uint64_t &Target) const override {
141     unsigned NumOps = Inst.getNumOperands();
142     if (NumOps == 0)
143       return false;
144     switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
145     case MCOI::OPERAND_UNKNOWN:
146     case MCOI::OPERAND_IMMEDIATE:
147       // jal, bal ...
148       Target = Inst.getOperand(NumOps - 1).getImm();
149       return true;
150     case MCOI::OPERAND_PCREL:
151       // b, j, beq ...
152       Target = Addr + Inst.getOperand(NumOps - 1).getImm();
153       return true;
154     default:
155       return false;
156     }
157   }
158 };
159 }
160 
161 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
162   return new MipsMCInstrAnalysis(Info);
163 }
164 
165 extern "C" void LLVMInitializeMipsTargetMC() {
166   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
167                     &TheMips64elTarget}) {
168     // Register the MC asm info.
169     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
170 
171     // Register the MC codegen info.
172     TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
173 
174     // Register the MC instruction info.
175     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
176 
177     // Register the MC register info.
178     TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
179 
180     // Register the elf streamer.
181     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
182 
183     // Register the asm target streamer.
184     TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
185 
186     TargetRegistry::RegisterNullTargetStreamer(*T,
187                                                createMipsNullTargetStreamer);
188 
189     // Register the MC subtarget info.
190     TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
191 
192     // Register the MC instruction analyzer.
193     TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis);
194 
195     // Register the MCInstPrinter.
196     TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
197 
198     TargetRegistry::RegisterObjectTargetStreamer(
199         *T, createMipsObjectTargetStreamer);
200   }
201 
202   // Register the MC Code Emitter
203   for (Target *T : {&TheMipsTarget, &TheMips64Target})
204     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
205 
206   for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
207     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
208 
209   // Register the asm backend.
210   TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
211                                        createMipsAsmBackendEB32);
212   TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
213                                        createMipsAsmBackendEL32);
214   TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
215                                        createMipsAsmBackendEB64);
216   TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
217                                        createMipsAsmBackendEL64);
218 
219 }
220