1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides Mips specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "InstPrinter/MipsInstPrinter.h" 15 #include "MipsELFStreamer.h" 16 #include "MipsMCAsmInfo.h" 17 #include "MipsMCNaCl.h" 18 #include "MipsMCTargetDesc.h" 19 #include "MipsTargetStreamer.h" 20 #include "llvm/ADT/Triple.h" 21 #include "llvm/MC/MCCodeGenInfo.h" 22 #include "llvm/MC/MCELFStreamer.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCSymbol.h" 27 #include "llvm/MC/MachineLocation.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/FormattedStream.h" 31 #include "llvm/Support/TargetRegistry.h" 32 33 #define GET_INSTRINFO_MC_DESC 34 #include "MipsGenInstrInfo.inc" 35 36 #define GET_SUBTARGETINFO_MC_DESC 37 #include "MipsGenSubtargetInfo.inc" 38 39 #define GET_REGINFO_MC_DESC 40 #include "MipsGenRegisterInfo.inc" 41 42 using namespace llvm; 43 44 /// Select the Mips CPU for the given triple and cpu name. 45 /// FIXME: Merge with the copy in MipsSubtarget.cpp 46 static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) { 47 if (CPU.empty() || CPU == "generic") { 48 Triple TheTriple(TT); 49 if (TheTriple.getArch() == Triple::mips || 50 TheTriple.getArch() == Triple::mipsel) 51 CPU = "mips32"; 52 else 53 CPU = "mips64"; 54 } 55 return CPU; 56 } 57 58 static MCInstrInfo *createMipsMCInstrInfo() { 59 MCInstrInfo *X = new MCInstrInfo(); 60 InitMipsMCInstrInfo(X); 61 return X; 62 } 63 64 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) { 65 MCRegisterInfo *X = new MCRegisterInfo(); 66 InitMipsMCRegisterInfo(X, Mips::RA); 67 return X; 68 } 69 70 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, 71 StringRef FS) { 72 CPU = selectMipsCPU(TT, CPU); 73 MCSubtargetInfo *X = new MCSubtargetInfo(); 74 InitMipsMCSubtargetInfo(X, TT, CPU, FS); 75 return X; 76 } 77 78 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { 79 MCAsmInfo *MAI = new MipsMCAsmInfo(TT); 80 81 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); 82 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, SP, 0); 83 MAI->addInitialFrameState(Inst); 84 85 return MAI; 86 } 87 88 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM, 89 CodeModel::Model CM, 90 CodeGenOpt::Level OL) { 91 MCCodeGenInfo *X = new MCCodeGenInfo(); 92 if (CM == CodeModel::JITDefault) 93 RM = Reloc::Static; 94 else if (RM == Reloc::Default) 95 RM = Reloc::PIC_; 96 X->InitMCCodeGenInfo(RM, CM, OL); 97 return X; 98 } 99 100 static MCInstPrinter *createMipsMCInstPrinter(const Target &T, 101 unsigned SyntaxVariant, 102 const MCAsmInfo &MAI, 103 const MCInstrInfo &MII, 104 const MCRegisterInfo &MRI, 105 const MCSubtargetInfo &STI) { 106 return new MipsInstPrinter(MAI, MII, MRI); 107 } 108 109 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, 110 MCContext &Context, MCAsmBackend &MAB, 111 raw_ostream &OS, MCCodeEmitter *Emitter, 112 const MCSubtargetInfo &STI, 113 bool RelaxAll, bool NoExecStack) { 114 MCStreamer *S; 115 if (!Triple(TT).isOSNaCl()) 116 S = createMipsELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll, 117 NoExecStack); 118 else 119 S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll, 120 NoExecStack); 121 new MipsTargetELFStreamer(*S, STI); 122 return S; 123 } 124 125 static MCStreamer * 126 createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, 127 bool isVerboseAsm, bool useCFI, bool useDwarfDirectory, 128 MCInstPrinter *InstPrint, MCCodeEmitter *CE, 129 MCAsmBackend *TAB, bool ShowInst) { 130 MCStreamer *S = 131 llvm::createAsmStreamer(Ctx, OS, isVerboseAsm, useCFI, useDwarfDirectory, 132 InstPrint, CE, TAB, ShowInst); 133 new MipsTargetAsmStreamer(*S, OS); 134 return S; 135 } 136 137 extern "C" void LLVMInitializeMipsTargetMC() { 138 // Register the MC asm info. 139 RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo); 140 RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo); 141 RegisterMCAsmInfoFn A(TheMips64Target, createMipsMCAsmInfo); 142 RegisterMCAsmInfoFn B(TheMips64elTarget, createMipsMCAsmInfo); 143 144 // Register the MC codegen info. 145 TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget, 146 createMipsMCCodeGenInfo); 147 TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget, 148 createMipsMCCodeGenInfo); 149 TargetRegistry::RegisterMCCodeGenInfo(TheMips64Target, 150 createMipsMCCodeGenInfo); 151 TargetRegistry::RegisterMCCodeGenInfo(TheMips64elTarget, 152 createMipsMCCodeGenInfo); 153 154 // Register the MC instruction info. 155 TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo); 156 TargetRegistry::RegisterMCInstrInfo(TheMipselTarget, createMipsMCInstrInfo); 157 TargetRegistry::RegisterMCInstrInfo(TheMips64Target, createMipsMCInstrInfo); 158 TargetRegistry::RegisterMCInstrInfo(TheMips64elTarget, 159 createMipsMCInstrInfo); 160 161 // Register the MC register info. 162 TargetRegistry::RegisterMCRegInfo(TheMipsTarget, createMipsMCRegisterInfo); 163 TargetRegistry::RegisterMCRegInfo(TheMipselTarget, createMipsMCRegisterInfo); 164 TargetRegistry::RegisterMCRegInfo(TheMips64Target, createMipsMCRegisterInfo); 165 TargetRegistry::RegisterMCRegInfo(TheMips64elTarget, 166 createMipsMCRegisterInfo); 167 168 // Register the MC Code Emitter 169 TargetRegistry::RegisterMCCodeEmitter(TheMipsTarget, 170 createMipsMCCodeEmitterEB); 171 TargetRegistry::RegisterMCCodeEmitter(TheMipselTarget, 172 createMipsMCCodeEmitterEL); 173 TargetRegistry::RegisterMCCodeEmitter(TheMips64Target, 174 createMipsMCCodeEmitterEB); 175 TargetRegistry::RegisterMCCodeEmitter(TheMips64elTarget, 176 createMipsMCCodeEmitterEL); 177 178 // Register the object streamer. 179 TargetRegistry::RegisterMCObjectStreamer(TheMipsTarget, createMCStreamer); 180 TargetRegistry::RegisterMCObjectStreamer(TheMipselTarget, createMCStreamer); 181 TargetRegistry::RegisterMCObjectStreamer(TheMips64Target, createMCStreamer); 182 TargetRegistry::RegisterMCObjectStreamer(TheMips64elTarget, 183 createMCStreamer); 184 185 // Register the asm streamer. 186 TargetRegistry::RegisterAsmStreamer(TheMipsTarget, createMCAsmStreamer); 187 TargetRegistry::RegisterAsmStreamer(TheMipselTarget, createMCAsmStreamer); 188 TargetRegistry::RegisterAsmStreamer(TheMips64Target, createMCAsmStreamer); 189 TargetRegistry::RegisterAsmStreamer(TheMips64elTarget, createMCAsmStreamer); 190 191 // Register the asm backend. 192 TargetRegistry::RegisterMCAsmBackend(TheMipsTarget, 193 createMipsAsmBackendEB32); 194 TargetRegistry::RegisterMCAsmBackend(TheMipselTarget, 195 createMipsAsmBackendEL32); 196 TargetRegistry::RegisterMCAsmBackend(TheMips64Target, 197 createMipsAsmBackendEB64); 198 TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget, 199 createMipsAsmBackendEL64); 200 201 // Register the MC subtarget info. 202 TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget, 203 createMipsMCSubtargetInfo); 204 TargetRegistry::RegisterMCSubtargetInfo(TheMipselTarget, 205 createMipsMCSubtargetInfo); 206 TargetRegistry::RegisterMCSubtargetInfo(TheMips64Target, 207 createMipsMCSubtargetInfo); 208 TargetRegistry::RegisterMCSubtargetInfo(TheMips64elTarget, 209 createMipsMCSubtargetInfo); 210 211 // Register the MCInstPrinter. 212 TargetRegistry::RegisterMCInstPrinter(TheMipsTarget, 213 createMipsMCInstPrinter); 214 TargetRegistry::RegisterMCInstPrinter(TheMipselTarget, 215 createMipsMCInstPrinter); 216 TargetRegistry::RegisterMCInstPrinter(TheMips64Target, 217 createMipsMCInstPrinter); 218 TargetRegistry::RegisterMCInstPrinter(TheMips64elTarget, 219 createMipsMCInstPrinter); 220 } 221