1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsMCTargetDesc.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsAsmBackend.h"
17 #include "MipsELFStreamer.h"
18 #include "MipsMCAsmInfo.h"
19 #include "MipsMCNaCl.h"
20 #include "MipsTargetStreamer.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrAnalysis.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/MC/MachineLocation.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/FormattedStream.h"
31 #include "llvm/Support/TargetRegistry.h"
32 
33 using namespace llvm;
34 
35 #define GET_INSTRINFO_MC_DESC
36 #include "MipsGenInstrInfo.inc"
37 
38 #define GET_SUBTARGETINFO_MC_DESC
39 #include "MipsGenSubtargetInfo.inc"
40 
41 #define GET_REGINFO_MC_DESC
42 #include "MipsGenRegisterInfo.inc"
43 
44 /// Select the Mips CPU for the given triple and cpu name.
45 /// FIXME: Merge with the copy in MipsSubtarget.cpp
46 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
47   if (CPU.empty() || CPU == "generic") {
48     if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
49       CPU = "mips32";
50     else
51       CPU = "mips64";
52   }
53   return CPU;
54 }
55 
56 static MCInstrInfo *createMipsMCInstrInfo() {
57   MCInstrInfo *X = new MCInstrInfo();
58   InitMipsMCInstrInfo(X);
59   return X;
60 }
61 
62 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
63   MCRegisterInfo *X = new MCRegisterInfo();
64   InitMipsMCRegisterInfo(X, Mips::RA);
65   return X;
66 }
67 
68 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
69                                                   StringRef CPU, StringRef FS) {
70   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
71   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
72 }
73 
74 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
75                                       const Triple &TT) {
76   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
77 
78   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
79   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
80   MAI->addInitialFrameState(Inst);
81 
82   return MAI;
83 }
84 
85 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
86                                               unsigned SyntaxVariant,
87                                               const MCAsmInfo &MAI,
88                                               const MCInstrInfo &MII,
89                                               const MCRegisterInfo &MRI) {
90   return new MipsInstPrinter(MAI, MII, MRI);
91 }
92 
93 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
94                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
95                                     MCCodeEmitter *Emitter, bool RelaxAll) {
96   MCStreamer *S;
97   if (!T.isOSNaCl())
98     S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
99   else
100     S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
101   return S;
102 }
103 
104 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
105                                                      formatted_raw_ostream &OS,
106                                                      MCInstPrinter *InstPrint,
107                                                      bool isVerboseAsm) {
108   return new MipsTargetAsmStreamer(S, OS);
109 }
110 
111 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
112   return new MipsTargetStreamer(S);
113 }
114 
115 static MCTargetStreamer *
116 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
117   return new MipsTargetELFStreamer(S, STI);
118 }
119 
120 namespace {
121 
122 class MipsMCInstrAnalysis : public MCInstrAnalysis {
123 public:
124   MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
125 
126   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
127                       uint64_t &Target) const override {
128     unsigned NumOps = Inst.getNumOperands();
129     if (NumOps == 0)
130       return false;
131     switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
132     case MCOI::OPERAND_UNKNOWN:
133     case MCOI::OPERAND_IMMEDIATE:
134       // jal, bal ...
135       Target = Inst.getOperand(NumOps - 1).getImm();
136       return true;
137     case MCOI::OPERAND_PCREL:
138       // b, j, beq ...
139       Target = Addr + Inst.getOperand(NumOps - 1).getImm();
140       return true;
141     default:
142       return false;
143     }
144   }
145 };
146 }
147 
148 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
149   return new MipsMCInstrAnalysis(Info);
150 }
151 
152 extern "C" void LLVMInitializeMipsTargetMC() {
153   for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
154                     &getTheMips64Target(), &getTheMips64elTarget()}) {
155     // Register the MC asm info.
156     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
157 
158     // Register the MC instruction info.
159     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
160 
161     // Register the MC register info.
162     TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
163 
164     // Register the elf streamer.
165     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
166 
167     // Register the asm target streamer.
168     TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
169 
170     TargetRegistry::RegisterNullTargetStreamer(*T,
171                                                createMipsNullTargetStreamer);
172 
173     // Register the MC subtarget info.
174     TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
175 
176     // Register the MC instruction analyzer.
177     TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis);
178 
179     // Register the MCInstPrinter.
180     TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
181 
182     TargetRegistry::RegisterObjectTargetStreamer(
183         *T, createMipsObjectTargetStreamer);
184 
185     // Register the asm backend.
186     TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend);
187   }
188 
189   // Register the MC Code Emitter
190   for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
191     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
192 
193   for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
194     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
195 }
196