1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsMCTargetDesc.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCAsmInfo.h"
18 #include "MipsMCNaCl.h"
19 #include "MipsTargetStreamer.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCCodeGenInfo.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrAnalysis.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/MC/MachineLocation.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/FormattedStream.h"
31 #include "llvm/Support/TargetRegistry.h"
32 
33 using namespace llvm;
34 
35 #define GET_INSTRINFO_MC_DESC
36 #include "MipsGenInstrInfo.inc"
37 
38 #define GET_SUBTARGETINFO_MC_DESC
39 #include "MipsGenSubtargetInfo.inc"
40 
41 #define GET_REGINFO_MC_DESC
42 #include "MipsGenRegisterInfo.inc"
43 
44 /// Select the Mips CPU for the given triple and cpu name.
45 /// FIXME: Merge with the copy in MipsSubtarget.cpp
46 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
47   if (CPU.empty() || CPU == "generic") {
48     if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
49       CPU = "mips32";
50     else
51       CPU = "mips64";
52   }
53   return CPU;
54 }
55 
56 static MCInstrInfo *createMipsMCInstrInfo() {
57   MCInstrInfo *X = new MCInstrInfo();
58   InitMipsMCInstrInfo(X);
59   return X;
60 }
61 
62 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
63   MCRegisterInfo *X = new MCRegisterInfo();
64   InitMipsMCRegisterInfo(X, Mips::RA);
65   return X;
66 }
67 
68 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
69                                                   StringRef CPU, StringRef FS) {
70   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
71   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
72 }
73 
74 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
75                                       const Triple &TT) {
76   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
77 
78   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
79   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
80   MAI->addInitialFrameState(Inst);
81 
82   return MAI;
83 }
84 
85 static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
86                                               CodeModel::Model CM,
87                                               CodeGenOpt::Level OL) {
88   MCCodeGenInfo *X = new MCCodeGenInfo();
89   if (RM == Reloc::Default || CM == CodeModel::JITDefault)
90     RM = Reloc::Static;
91   X->initMCCodeGenInfo(RM, CM, OL);
92   return X;
93 }
94 
95 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
96                                               unsigned SyntaxVariant,
97                                               const MCAsmInfo &MAI,
98                                               const MCInstrInfo &MII,
99                                               const MCRegisterInfo &MRI) {
100   return new MipsInstPrinter(MAI, MII, MRI);
101 }
102 
103 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
104                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
105                                     MCCodeEmitter *Emitter, bool RelaxAll) {
106   MCStreamer *S;
107   if (!T.isOSNaCl())
108     S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
109   else
110     S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
111   return S;
112 }
113 
114 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
115                                                      formatted_raw_ostream &OS,
116                                                      MCInstPrinter *InstPrint,
117                                                      bool isVerboseAsm) {
118   return new MipsTargetAsmStreamer(S, OS);
119 }
120 
121 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
122   return new MipsTargetStreamer(S);
123 }
124 
125 static MCTargetStreamer *
126 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
127   return new MipsTargetELFStreamer(S, STI);
128 }
129 
130 namespace {
131 
132 class MipsMCInstrAnalysis : public MCInstrAnalysis {
133 public:
134   MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
135 
136   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
137                       uint64_t &Target) const override {
138     unsigned NumOps = Inst.getNumOperands();
139     if (NumOps == 0)
140       return false;
141     switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
142     case MCOI::OPERAND_UNKNOWN:
143     case MCOI::OPERAND_IMMEDIATE:
144       // jal, bal ...
145       Target = Inst.getOperand(NumOps - 1).getImm();
146       return true;
147     case MCOI::OPERAND_PCREL:
148       // b, j, beq ...
149       Target = Addr + Inst.getOperand(NumOps - 1).getImm();
150       return true;
151     default:
152       return false;
153     }
154   }
155 };
156 }
157 
158 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
159   return new MipsMCInstrAnalysis(Info);
160 }
161 
162 extern "C" void LLVMInitializeMipsTargetMC() {
163   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
164                     &TheMips64elTarget}) {
165     // Register the MC asm info.
166     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
167 
168     // Register the MC codegen info.
169     TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
170 
171     // Register the MC instruction info.
172     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
173 
174     // Register the MC register info.
175     TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
176 
177     // Register the elf streamer.
178     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
179 
180     // Register the asm target streamer.
181     TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
182 
183     TargetRegistry::RegisterNullTargetStreamer(*T,
184                                                createMipsNullTargetStreamer);
185 
186     // Register the MC subtarget info.
187     TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
188 
189     // Register the MC instruction analyzer.
190     TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis);
191 
192     // Register the MCInstPrinter.
193     TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
194 
195     TargetRegistry::RegisterObjectTargetStreamer(
196         *T, createMipsObjectTargetStreamer);
197   }
198 
199   // Register the MC Code Emitter
200   for (Target *T : {&TheMipsTarget, &TheMips64Target})
201     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
202 
203   for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
204     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
205 
206   // Register the asm backend.
207   TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
208                                        createMipsAsmBackendEB32);
209   TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
210                                        createMipsAsmBackendEL32);
211   TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
212                                        createMipsAsmBackendEB64);
213   TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
214                                        createMipsAsmBackendEL64);
215 
216 }
217