1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "InstPrinter/MipsInstPrinter.h"
15 #include "MipsELFStreamer.h"
16 #include "MipsMCAsmInfo.h"
17 #include "MipsMCNaCl.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetStreamer.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCCodeGenInfo.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MachineLocation.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/FormattedStream.h"
31 #include "llvm/Support/TargetRegistry.h"
32 
33 using namespace llvm;
34 
35 #define GET_INSTRINFO_MC_DESC
36 #include "MipsGenInstrInfo.inc"
37 
38 #define GET_SUBTARGETINFO_MC_DESC
39 #include "MipsGenSubtargetInfo.inc"
40 
41 #define GET_REGINFO_MC_DESC
42 #include "MipsGenRegisterInfo.inc"
43 
44 /// Select the Mips CPU for the given triple and cpu name.
45 /// FIXME: Merge with the copy in MipsSubtarget.cpp
46 StringRef MIPS_MC::selectMipsCPU(StringRef TT, StringRef CPU) {
47   if (CPU.empty() || CPU == "generic") {
48     Triple TheTriple(TT);
49     if (TheTriple.getArch() == Triple::mips ||
50         TheTriple.getArch() == Triple::mipsel)
51       CPU = "mips32";
52     else
53       CPU = "mips64";
54   }
55   return CPU;
56 }
57 
58 static MCInstrInfo *createMipsMCInstrInfo() {
59   MCInstrInfo *X = new MCInstrInfo();
60   InitMipsMCInstrInfo(X);
61   return X;
62 }
63 
64 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
65   MCRegisterInfo *X = new MCRegisterInfo();
66   InitMipsMCRegisterInfo(X, Mips::RA);
67   return X;
68 }
69 
70 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
71                                                   StringRef FS) {
72   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
73   MCSubtargetInfo *X = new MCSubtargetInfo();
74   InitMipsMCSubtargetInfo(X, TT, CPU, FS);
75   return X;
76 }
77 
78 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
79   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
80 
81   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
82   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
83   MAI->addInitialFrameState(Inst);
84 
85   return MAI;
86 }
87 
88 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
89                                               CodeModel::Model CM,
90                                               CodeGenOpt::Level OL) {
91   MCCodeGenInfo *X = new MCCodeGenInfo();
92   if (CM == CodeModel::JITDefault)
93     RM = Reloc::Static;
94   else if (RM == Reloc::Default)
95     RM = Reloc::PIC_;
96   X->InitMCCodeGenInfo(RM, CM, OL);
97   return X;
98 }
99 
100 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
101                                               unsigned SyntaxVariant,
102                                               const MCAsmInfo &MAI,
103                                               const MCInstrInfo &MII,
104                                               const MCRegisterInfo &MRI) {
105   return new MipsInstPrinter(MAI, MII, MRI);
106 }
107 
108 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
109                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
110                                     MCCodeEmitter *Emitter, bool RelaxAll) {
111   MCStreamer *S;
112   if (!T.isOSNaCl())
113     S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
114   else
115     S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
116   return S;
117 }
118 
119 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
120                                                      formatted_raw_ostream &OS,
121                                                      MCInstPrinter *InstPrint,
122                                                      bool isVerboseAsm) {
123   return new MipsTargetAsmStreamer(S, OS);
124 }
125 
126 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
127   return new MipsTargetStreamer(S);
128 }
129 
130 static MCTargetStreamer *
131 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
132   return new MipsTargetELFStreamer(S, STI);
133 }
134 
135 extern "C" void LLVMInitializeMipsTargetMC() {
136   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
137                     &TheMips64elTarget}) {
138     // Register the MC asm info.
139     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
140 
141     // Register the MC codegen info.
142     TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
143 
144     // Register the MC instruction info.
145     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
146 
147     // Register the MC register info.
148     TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
149 
150     // Register the elf streamer.
151     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
152 
153     // Register the asm target streamer.
154     TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
155 
156     TargetRegistry::RegisterNullTargetStreamer(*T,
157                                                createMipsNullTargetStreamer);
158 
159     // Register the MC subtarget info.
160     TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
161 
162     // Register the MCInstPrinter.
163     TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
164 
165     TargetRegistry::RegisterObjectTargetStreamer(
166         *T, createMipsObjectTargetStreamer);
167   }
168 
169   // Register the MC Code Emitter
170   for (Target *T : {&TheMipsTarget, &TheMips64Target})
171     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
172 
173   for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
174     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
175 
176   // Register the asm backend.
177   TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
178                                        createMipsAsmBackendEB32);
179   TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
180                                        createMipsAsmBackendEL32);
181   TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
182                                        createMipsAsmBackendEB64);
183   TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
184                                        createMipsAsmBackendEL64);
185 
186 }
187