1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MipsMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsMCCodeEmitter.h"
15 #include "MCTargetDesc/MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsMCExpr.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <cassert>
33 #include <cstdint>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mccodeemitter"
38 
39 #define GET_INSTRMAP_INFO
40 #include "MipsGenInstrInfo.inc"
41 #undef GET_INSTRMAP_INFO
42 
43 namespace llvm {
44 
45 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
46                                          const MCRegisterInfo &MRI,
47                                          MCContext &Ctx) {
48   return new MipsMCCodeEmitter(MCII, Ctx, false);
49 }
50 
51 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
52                                          const MCRegisterInfo &MRI,
53                                          MCContext &Ctx) {
54   return new MipsMCCodeEmitter(MCII, Ctx, true);
55 }
56 
57 } // end namespace llvm
58 
59 // If the D<shift> instruction has a shift amount that is greater
60 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
61 static void LowerLargeShift(MCInst& Inst) {
62   assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
63   assert(Inst.getOperand(2).isImm());
64 
65   int64_t Shift = Inst.getOperand(2).getImm();
66   if (Shift <= 31)
67     return; // Do nothing
68   Shift -= 32;
69 
70   // saminus32
71   Inst.getOperand(2).setImm(Shift);
72 
73   switch (Inst.getOpcode()) {
74   default:
75     // Calling function is not synchronized
76     llvm_unreachable("Unexpected shift instruction");
77   case Mips::DSLL:
78     Inst.setOpcode(Mips::DSLL32);
79     return;
80   case Mips::DSRL:
81     Inst.setOpcode(Mips::DSRL32);
82     return;
83   case Mips::DSRA:
84     Inst.setOpcode(Mips::DSRA32);
85     return;
86   case Mips::DROTR:
87     Inst.setOpcode(Mips::DROTR32);
88     return;
89   }
90 }
91 
92 // Fix a bad compact branch encoding for beqc/bnec.
93 void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
94   // Encoding may be illegal !(rs < rt), but this situation is
95   // easily fixed.
96   unsigned RegOp0 = Inst.getOperand(0).getReg();
97   unsigned RegOp1 = Inst.getOperand(1).getReg();
98 
99   unsigned Reg0 =  Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
100   unsigned Reg1 =  Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
101 
102   if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||
103       Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {
104     assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
105     if (Reg0 < Reg1)
106       return;
107   } else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {
108     if (Reg0 >= Reg1)
109       return;
110   } else if (Inst.getOpcode() == Mips::BNVC_MMR6 ||
111              Inst.getOpcode() == Mips::BOVC_MMR6) {
112     if (Reg1 >= Reg0)
113       return;
114   } else
115     llvm_unreachable("Cannot rewrite unknown branch!");
116 
117   Inst.getOperand(0).setReg(RegOp1);
118   Inst.getOperand(1).setReg(RegOp0);
119 }
120 
121 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
122   return STI.getFeatureBits()[Mips::FeatureMicroMips];
123 }
124 
125 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
126   return STI.getFeatureBits()[Mips::FeatureMips32r6];
127 }
128 
129 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
130   OS << (char)C;
131 }
132 
133 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
134                                         const MCSubtargetInfo &STI,
135                                         raw_ostream &OS) const {
136   // Output the instruction encoding in little endian byte order.
137   // Little-endian byte ordering:
138   //   mips32r2:   4 | 3 | 2 | 1
139   //   microMIPS:  2 | 1 | 4 | 3
140   if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
141     EmitInstruction(Val >> 16, 2, STI, OS);
142     EmitInstruction(Val, 2, STI, OS);
143   } else {
144     for (unsigned i = 0; i < Size; ++i) {
145       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
146       EmitByte((Val >> Shift) & 0xff, OS);
147     }
148   }
149 }
150 
151 /// encodeInstruction - Emit the instruction.
152 /// Size the instruction with Desc.getSize().
153 void MipsMCCodeEmitter::
154 encodeInstruction(const MCInst &MI, raw_ostream &OS,
155                   SmallVectorImpl<MCFixup> &Fixups,
156                   const MCSubtargetInfo &STI) const
157 {
158   // Non-pseudo instructions that get changed for direct object
159   // only based on operand values.
160   // If this list of instructions get much longer we will move
161   // the check to a function call. Until then, this is more efficient.
162   MCInst TmpInst = MI;
163   switch (MI.getOpcode()) {
164   // If shift amount is >= 32 it the inst needs to be lowered further
165   case Mips::DSLL:
166   case Mips::DSRL:
167   case Mips::DSRA:
168   case Mips::DROTR:
169     LowerLargeShift(TmpInst);
170     break;
171   // Compact branches, enforce encoding restrictions.
172   case Mips::BEQC:
173   case Mips::BNEC:
174   case Mips::BEQC64:
175   case Mips::BNEC64:
176   case Mips::BOVC:
177   case Mips::BOVC_MMR6:
178   case Mips::BNVC:
179   case Mips::BNVC_MMR6:
180     LowerCompactBranch(TmpInst);
181   }
182 
183   unsigned long N = Fixups.size();
184   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
185 
186   // Check for unimplemented opcodes.
187   // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
188   // so we have to special check for them.
189   unsigned Opcode = TmpInst.getOpcode();
190   if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
191       (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary)
192     llvm_unreachable("unimplemented opcode in encodeInstruction()");
193 
194   int NewOpcode = -1;
195   if (isMicroMips(STI)) {
196     if (isMips32r6(STI)) {
197       NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
198       if (NewOpcode == -1)
199         NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
200     }
201     else
202       NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
203 
204     // Check whether it is Dsp instruction.
205     if (NewOpcode == -1)
206       NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
207 
208     if (NewOpcode != -1) {
209       if (Fixups.size() > N)
210         Fixups.pop_back();
211 
212       Opcode = NewOpcode;
213       TmpInst.setOpcode (NewOpcode);
214       Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
215     }
216 
217     if (((MI.getOpcode() == Mips::MOVEP_MM) ||
218          (MI.getOpcode() == Mips::MOVEP_MMR6))) {
219       unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI);
220       Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7);
221     }
222   }
223 
224   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
225 
226   // Get byte count of instruction
227   unsigned Size = Desc.getSize();
228   if (!Size)
229     llvm_unreachable("Desc.getSize() returns 0");
230 
231   EmitInstruction(Binary, Size, STI, OS);
232 }
233 
234 /// getBranchTargetOpValue - Return binary encoding of the branch
235 /// target operand. If the machine operand requires relocation,
236 /// record the relocation and return zero.
237 unsigned MipsMCCodeEmitter::
238 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
239                        SmallVectorImpl<MCFixup> &Fixups,
240                        const MCSubtargetInfo &STI) const {
241   const MCOperand &MO = MI.getOperand(OpNo);
242 
243   // If the destination is an immediate, divide by 4.
244   if (MO.isImm()) return MO.getImm() >> 2;
245 
246   assert(MO.isExpr() &&
247          "getBranchTargetOpValue expects only expressions or immediates");
248 
249   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
250       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
251   Fixups.push_back(MCFixup::create(0, FixupExpression,
252                                    MCFixupKind(Mips::fixup_Mips_PC16)));
253   return 0;
254 }
255 
256 /// getBranchTargetOpValue1SImm16 - Return binary encoding of the branch
257 /// target operand. If the machine operand requires relocation,
258 /// record the relocation and return zero.
259 unsigned MipsMCCodeEmitter::
260 getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
261                               SmallVectorImpl<MCFixup> &Fixups,
262                               const MCSubtargetInfo &STI) const {
263   const MCOperand &MO = MI.getOperand(OpNo);
264 
265   // If the destination is an immediate, divide by 2.
266   if (MO.isImm()) return MO.getImm() >> 1;
267 
268   assert(MO.isExpr() &&
269          "getBranchTargetOpValue expects only expressions or immediates");
270 
271   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
272       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
273   Fixups.push_back(MCFixup::create(0, FixupExpression,
274                                    MCFixupKind(Mips::fixup_Mips_PC16)));
275   return 0;
276 }
277 
278 /// getBranchTargetOpValueMMR6 - Return binary encoding of the branch
279 /// target operand. If the machine operand requires relocation,
280 /// record the relocation and return zero.
281 unsigned MipsMCCodeEmitter::
282 getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
283                            SmallVectorImpl<MCFixup> &Fixups,
284                            const MCSubtargetInfo &STI) const {
285   const MCOperand &MO = MI.getOperand(OpNo);
286 
287   // If the destination is an immediate, divide by 2.
288   if (MO.isImm())
289     return MO.getImm() >> 1;
290 
291   assert(MO.isExpr() &&
292          "getBranchTargetOpValueMMR6 expects only expressions or immediates");
293 
294   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
295       MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
296   Fixups.push_back(MCFixup::create(0, FixupExpression,
297                                    MCFixupKind(Mips::fixup_Mips_PC16)));
298   return 0;
299 }
300 
301 /// getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch
302 /// target operand. If the machine operand requires relocation,
303 /// record the relocation and return zero.
304 unsigned MipsMCCodeEmitter::
305 getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
306                                SmallVectorImpl<MCFixup> &Fixups,
307                                const MCSubtargetInfo &STI) const {
308   const MCOperand &MO = MI.getOperand(OpNo);
309 
310   // If the destination is an immediate, divide by 4.
311   if (MO.isImm())
312     return MO.getImm() >> 2;
313 
314   assert(MO.isExpr() &&
315          "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates");
316 
317   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
318       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
319   Fixups.push_back(MCFixup::create(0, FixupExpression,
320                                    MCFixupKind(Mips::fixup_Mips_PC16)));
321   return 0;
322 }
323 
324 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
325 /// target operand. If the machine operand requires relocation,
326 /// record the relocation and return zero.
327 unsigned MipsMCCodeEmitter::
328 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
329                           SmallVectorImpl<MCFixup> &Fixups,
330                           const MCSubtargetInfo &STI) const {
331   const MCOperand &MO = MI.getOperand(OpNo);
332 
333   // If the destination is an immediate, divide by 2.
334   if (MO.isImm()) return MO.getImm() >> 1;
335 
336   assert(MO.isExpr() &&
337          "getBranchTargetOpValueMM expects only expressions or immediates");
338 
339   const MCExpr *Expr = MO.getExpr();
340   Fixups.push_back(MCFixup::create(0, Expr,
341                                    MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
342   return 0;
343 }
344 
345 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
346 /// 10-bit branch target operand. If the machine operand requires relocation,
347 /// record the relocation and return zero.
348 unsigned MipsMCCodeEmitter::
349 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
350                              SmallVectorImpl<MCFixup> &Fixups,
351                              const MCSubtargetInfo &STI) const {
352   const MCOperand &MO = MI.getOperand(OpNo);
353 
354   // If the destination is an immediate, divide by 2.
355   if (MO.isImm()) return MO.getImm() >> 1;
356 
357   assert(MO.isExpr() &&
358          "getBranchTargetOpValuePC10 expects only expressions or immediates");
359 
360   const MCExpr *Expr = MO.getExpr();
361   Fixups.push_back(MCFixup::create(0, Expr,
362                    MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
363   return 0;
364 }
365 
366 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
367 /// target operand. If the machine operand requires relocation,
368 /// record the relocation and return zero.
369 unsigned MipsMCCodeEmitter::
370 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
371                          SmallVectorImpl<MCFixup> &Fixups,
372                          const MCSubtargetInfo &STI) const {
373   const MCOperand &MO = MI.getOperand(OpNo);
374 
375   // If the destination is an immediate, divide by 2.
376   if (MO.isImm()) return MO.getImm() >> 1;
377 
378   assert(MO.isExpr() &&
379          "getBranchTargetOpValueMM expects only expressions or immediates");
380 
381   const MCExpr *Expr = MO.getExpr();
382   Fixups.push_back(MCFixup::create(0, Expr,
383                    MCFixupKind(Mips::
384                                fixup_MICROMIPS_PC16_S1)));
385   return 0;
386 }
387 
388 /// getBranchTarget21OpValue - Return binary encoding of the branch
389 /// target operand. If the machine operand requires relocation,
390 /// record the relocation and return zero.
391 unsigned MipsMCCodeEmitter::
392 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
393                          SmallVectorImpl<MCFixup> &Fixups,
394                          const MCSubtargetInfo &STI) const {
395   const MCOperand &MO = MI.getOperand(OpNo);
396 
397   // If the destination is an immediate, divide by 4.
398   if (MO.isImm()) return MO.getImm() >> 2;
399 
400   assert(MO.isExpr() &&
401          "getBranchTarget21OpValue expects only expressions or immediates");
402 
403   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
404       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
405   Fixups.push_back(MCFixup::create(0, FixupExpression,
406                                    MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
407   return 0;
408 }
409 
410 /// getBranchTarget21OpValueMM - Return binary encoding of the branch
411 /// target operand for microMIPS. If the machine operand requires
412 /// relocation, record the relocation and return zero.
413 unsigned MipsMCCodeEmitter::
414 getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
415                            SmallVectorImpl<MCFixup> &Fixups,
416                            const MCSubtargetInfo &STI) const {
417   const MCOperand &MO = MI.getOperand(OpNo);
418 
419   // If the destination is an immediate, divide by 4.
420   if (MO.isImm()) return MO.getImm() >> 2;
421 
422   assert(MO.isExpr() &&
423     "getBranchTarget21OpValueMM expects only expressions or immediates");
424 
425   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
426       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
427   Fixups.push_back(MCFixup::create(0, FixupExpression,
428                                    MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
429   return 0;
430 }
431 
432 /// getBranchTarget26OpValue - Return binary encoding of the branch
433 /// target operand. If the machine operand requires relocation,
434 /// record the relocation and return zero.
435 unsigned MipsMCCodeEmitter::
436 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
437                          SmallVectorImpl<MCFixup> &Fixups,
438                          const MCSubtargetInfo &STI) const {
439   const MCOperand &MO = MI.getOperand(OpNo);
440 
441   // If the destination is an immediate, divide by 4.
442   if (MO.isImm()) return MO.getImm() >> 2;
443 
444   assert(MO.isExpr() &&
445          "getBranchTarget26OpValue expects only expressions or immediates");
446 
447   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
448       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
449   Fixups.push_back(MCFixup::create(0, FixupExpression,
450                                    MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
451   return 0;
452 }
453 
454 /// getBranchTarget26OpValueMM - Return binary encoding of the branch
455 /// target operand. If the machine operand requires relocation,
456 /// record the relocation and return zero.
457 unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
458     const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
459     const MCSubtargetInfo &STI) const {
460   const MCOperand &MO = MI.getOperand(OpNo);
461 
462   // If the destination is an immediate, divide by 2.
463   if (MO.isImm())
464     return MO.getImm() >> 1;
465 
466   assert(MO.isExpr() &&
467          "getBranchTarget26OpValueMM expects only expressions or immediates");
468 
469   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
470       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
471   Fixups.push_back(MCFixup::create(0, FixupExpression,
472                                    MCFixupKind(Mips::fixup_MICROMIPS_PC26_S1)));
473   return 0;
474 }
475 
476 /// getJumpOffset16OpValue - Return binary encoding of the jump
477 /// target operand. If the machine operand requires relocation,
478 /// record the relocation and return zero.
479 unsigned MipsMCCodeEmitter::
480 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
481                        SmallVectorImpl<MCFixup> &Fixups,
482                        const MCSubtargetInfo &STI) const {
483   const MCOperand &MO = MI.getOperand(OpNo);
484 
485   if (MO.isImm()) return MO.getImm();
486 
487   assert(MO.isExpr() &&
488          "getJumpOffset16OpValue expects only expressions or an immediate");
489 
490    // TODO: Push fixup.
491    return 0;
492 }
493 
494 /// getJumpTargetOpValue - Return binary encoding of the jump
495 /// target operand. If the machine operand requires relocation,
496 /// record the relocation and return zero.
497 unsigned MipsMCCodeEmitter::
498 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
499                      SmallVectorImpl<MCFixup> &Fixups,
500                      const MCSubtargetInfo &STI) const {
501   const MCOperand &MO = MI.getOperand(OpNo);
502   // If the destination is an immediate, divide by 4.
503   if (MO.isImm()) return MO.getImm()>>2;
504 
505   assert(MO.isExpr() &&
506          "getJumpTargetOpValue expects only expressions or an immediate");
507 
508   const MCExpr *Expr = MO.getExpr();
509   Fixups.push_back(MCFixup::create(0, Expr,
510                                    MCFixupKind(Mips::fixup_Mips_26)));
511   return 0;
512 }
513 
514 unsigned MipsMCCodeEmitter::
515 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
516                        SmallVectorImpl<MCFixup> &Fixups,
517                        const MCSubtargetInfo &STI) const {
518   const MCOperand &MO = MI.getOperand(OpNo);
519   // If the destination is an immediate, divide by 2.
520   if (MO.isImm()) return MO.getImm() >> 1;
521 
522   assert(MO.isExpr() &&
523          "getJumpTargetOpValueMM expects only expressions or an immediate");
524 
525   const MCExpr *Expr = MO.getExpr();
526   Fixups.push_back(MCFixup::create(0, Expr,
527                                    MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
528   return 0;
529 }
530 
531 unsigned MipsMCCodeEmitter::
532 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
533                      SmallVectorImpl<MCFixup> &Fixups,
534                      const MCSubtargetInfo &STI) const {
535   const MCOperand &MO = MI.getOperand(OpNo);
536   if (MO.isImm()) {
537     // The immediate is encoded as 'immediate << 2'.
538     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
539     assert((Res & 3) == 0);
540     return Res >> 2;
541   }
542 
543   assert(MO.isExpr() &&
544          "getUImm5Lsl2Encoding expects only expressions or an immediate");
545 
546   return 0;
547 }
548 
549 unsigned MipsMCCodeEmitter::
550 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
551                   SmallVectorImpl<MCFixup> &Fixups,
552                   const MCSubtargetInfo &STI) const {
553   const MCOperand &MO = MI.getOperand(OpNo);
554   if (MO.isImm()) {
555     int Value = MO.getImm();
556     return Value >> 2;
557   }
558 
559   return 0;
560 }
561 
562 unsigned MipsMCCodeEmitter::
563 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
564                      SmallVectorImpl<MCFixup> &Fixups,
565                      const MCSubtargetInfo &STI) const {
566   const MCOperand &MO = MI.getOperand(OpNo);
567   if (MO.isImm()) {
568     unsigned Value = MO.getImm();
569     return Value >> 2;
570   }
571 
572   return 0;
573 }
574 
575 unsigned MipsMCCodeEmitter::
576 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
577                      SmallVectorImpl<MCFixup> &Fixups,
578                      const MCSubtargetInfo &STI) const {
579   const MCOperand &MO = MI.getOperand(OpNo);
580   if (MO.isImm()) {
581     unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
582     return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
583   }
584 
585   return 0;
586 }
587 
588 unsigned MipsMCCodeEmitter::
589 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
590                const MCSubtargetInfo &STI) const {
591   int64_t Res;
592 
593   if (Expr->evaluateAsAbsolute(Res))
594     return Res;
595 
596   MCExpr::ExprKind Kind = Expr->getKind();
597   if (Kind == MCExpr::Constant) {
598     return cast<MCConstantExpr>(Expr)->getValue();
599   }
600 
601   if (Kind == MCExpr::Binary) {
602     unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
603     Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
604     return Res;
605   }
606 
607   if (Kind == MCExpr::Target) {
608     const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
609 
610     Mips::Fixups FixupKind = Mips::Fixups(0);
611     switch (MipsExpr->getKind()) {
612     case MipsMCExpr::MEK_None:
613     case MipsMCExpr::MEK_Special:
614       llvm_unreachable("Unhandled fixup kind!");
615       break;
616     case MipsMCExpr::MEK_DTPREL:
617       llvm_unreachable("MEK_DTPREL is used for TLS DIEExpr only");
618       break;
619     case MipsMCExpr::MEK_CALL_HI16:
620       FixupKind = Mips::fixup_Mips_CALL_HI16;
621       break;
622     case MipsMCExpr::MEK_CALL_LO16:
623       FixupKind = Mips::fixup_Mips_CALL_LO16;
624       break;
625     case MipsMCExpr::MEK_DTPREL_HI:
626       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
627                                    : Mips::fixup_Mips_DTPREL_HI;
628       break;
629     case MipsMCExpr::MEK_DTPREL_LO:
630       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
631                                    : Mips::fixup_Mips_DTPREL_LO;
632       break;
633     case MipsMCExpr::MEK_GOTTPREL:
634       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOTTPREL
635                                    : Mips::fixup_Mips_GOTTPREL;
636       break;
637     case MipsMCExpr::MEK_GOT:
638       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
639                                    : Mips::fixup_Mips_GOT;
640       break;
641     case MipsMCExpr::MEK_GOT_CALL:
642       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
643                                    : Mips::fixup_Mips_CALL16;
644       break;
645     case MipsMCExpr::MEK_GOT_DISP:
646       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
647                                    : Mips::fixup_Mips_GOT_DISP;
648       break;
649     case MipsMCExpr::MEK_GOT_HI16:
650       FixupKind = Mips::fixup_Mips_GOT_HI16;
651       break;
652     case MipsMCExpr::MEK_GOT_LO16:
653       FixupKind = Mips::fixup_Mips_GOT_LO16;
654       break;
655     case MipsMCExpr::MEK_GOT_PAGE:
656       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
657                                    : Mips::fixup_Mips_GOT_PAGE;
658       break;
659     case MipsMCExpr::MEK_GOT_OFST:
660       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
661                                    : Mips::fixup_Mips_GOT_OFST;
662       break;
663     case MipsMCExpr::MEK_GPREL:
664       FixupKind = Mips::fixup_Mips_GPREL16;
665       break;
666     case MipsMCExpr::MEK_LO:
667       // Check for %lo(%neg(%gp_rel(X)))
668       if (MipsExpr->isGpOff())
669         FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GPOFF_LO
670                                      : Mips::fixup_Mips_GPOFF_LO;
671       else
672         FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
673                                      : Mips::fixup_Mips_LO16;
674       break;
675     case MipsMCExpr::MEK_HIGHEST:
676       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HIGHEST
677                                    : Mips::fixup_Mips_HIGHEST;
678       break;
679     case MipsMCExpr::MEK_HIGHER:
680       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HIGHER
681                                    : Mips::fixup_Mips_HIGHER;
682       break;
683     case MipsMCExpr::MEK_HI:
684       // Check for %hi(%neg(%gp_rel(X)))
685       if (MipsExpr->isGpOff())
686         FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GPOFF_HI
687                                      : Mips::fixup_Mips_GPOFF_HI;
688       else
689         FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
690                                      : Mips::fixup_Mips_HI16;
691       break;
692     case MipsMCExpr::MEK_PCREL_HI16:
693       FixupKind = Mips::fixup_MIPS_PCHI16;
694       break;
695     case MipsMCExpr::MEK_PCREL_LO16:
696       FixupKind = Mips::fixup_MIPS_PCLO16;
697       break;
698     case MipsMCExpr::MEK_TLSGD:
699       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
700                                    : Mips::fixup_Mips_TLSGD;
701       break;
702     case MipsMCExpr::MEK_TLSLDM:
703       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
704                                    : Mips::fixup_Mips_TLSLDM;
705       break;
706     case MipsMCExpr::MEK_TPREL_HI:
707       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
708                                    : Mips::fixup_Mips_TPREL_HI;
709       break;
710     case MipsMCExpr::MEK_TPREL_LO:
711       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
712                                    : Mips::fixup_Mips_TPREL_LO;
713       break;
714     case MipsMCExpr::MEK_NEG:
715       FixupKind =
716           isMicroMips(STI) ? Mips::fixup_MICROMIPS_SUB : Mips::fixup_Mips_SUB;
717       break;
718     }
719     Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
720     return 0;
721   }
722 
723   if (Kind == MCExpr::SymbolRef) {
724     Mips::Fixups FixupKind = Mips::Fixups(0);
725 
726     switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
727     default: llvm_unreachable("Unknown fixup kind!");
728       break;
729     case MCSymbolRefExpr::VK_None:
730       FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
731       break;
732     } // switch
733 
734     Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
735     return 0;
736   }
737   return 0;
738 }
739 
740 /// getMachineOpValue - Return binary encoding of operand. If the machine
741 /// operand requires relocation, record the relocation and return zero.
742 unsigned MipsMCCodeEmitter::
743 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
744                   SmallVectorImpl<MCFixup> &Fixups,
745                   const MCSubtargetInfo &STI) const {
746   if (MO.isReg()) {
747     unsigned Reg = MO.getReg();
748     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
749     return RegNo;
750   } else if (MO.isImm()) {
751     return static_cast<unsigned>(MO.getImm());
752   } else if (MO.isFPImm()) {
753     return static_cast<unsigned>(APFloat(MO.getFPImm())
754         .bitcastToAPInt().getHiBits(32).getLimitedValue());
755   }
756   // MO must be an Expr.
757   assert(MO.isExpr());
758   return getExprOpValue(MO.getExpr(),Fixups, STI);
759 }
760 
761 /// Return binary encoding of memory related operand.
762 /// If the offset operand requires relocation, record the relocation.
763 template <unsigned ShiftAmount>
764 unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
765                                            SmallVectorImpl<MCFixup> &Fixups,
766                                            const MCSubtargetInfo &STI) const {
767   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
768   assert(MI.getOperand(OpNo).isReg());
769   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
770   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
771 
772   // Apply the scale factor if there is one.
773   OffBits >>= ShiftAmount;
774 
775   return (OffBits & 0xFFFF) | RegBits;
776 }
777 
778 unsigned MipsMCCodeEmitter::
779 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
780                      SmallVectorImpl<MCFixup> &Fixups,
781                      const MCSubtargetInfo &STI) const {
782   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
783   assert(MI.getOperand(OpNo).isReg());
784   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
785                                        Fixups, STI) << 4;
786   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
787                                        Fixups, STI);
788 
789   return (OffBits & 0xF) | RegBits;
790 }
791 
792 unsigned MipsMCCodeEmitter::
793 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
794                          SmallVectorImpl<MCFixup> &Fixups,
795                          const MCSubtargetInfo &STI) const {
796   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
797   assert(MI.getOperand(OpNo).isReg());
798   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
799                                        Fixups, STI) << 4;
800   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
801                                        Fixups, STI) >> 1;
802 
803   return (OffBits & 0xF) | RegBits;
804 }
805 
806 unsigned MipsMCCodeEmitter::
807 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
808                          SmallVectorImpl<MCFixup> &Fixups,
809                          const MCSubtargetInfo &STI) const {
810   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
811   assert(MI.getOperand(OpNo).isReg());
812   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
813                                        Fixups, STI) << 4;
814   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
815                                        Fixups, STI) >> 2;
816 
817   return (OffBits & 0xF) | RegBits;
818 }
819 
820 unsigned MipsMCCodeEmitter::
821 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
822                            SmallVectorImpl<MCFixup> &Fixups,
823                            const MCSubtargetInfo &STI) const {
824   // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
825   assert(MI.getOperand(OpNo).isReg() &&
826          (MI.getOperand(OpNo).getReg() == Mips::SP ||
827          MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
828          "Unexpected base register!");
829   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
830                                        Fixups, STI) >> 2;
831 
832   return OffBits & 0x1F;
833 }
834 
835 unsigned MipsMCCodeEmitter::
836 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
837                            SmallVectorImpl<MCFixup> &Fixups,
838                            const MCSubtargetInfo &STI) const {
839   // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
840   assert(MI.getOperand(OpNo).isReg() &&
841          MI.getOperand(OpNo).getReg() == Mips::GP &&
842          "Unexpected base register!");
843 
844   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
845                                        Fixups, STI) >> 2;
846 
847   return OffBits & 0x7F;
848 }
849 
850 unsigned MipsMCCodeEmitter::
851 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
852                      SmallVectorImpl<MCFixup> &Fixups,
853                      const MCSubtargetInfo &STI) const {
854   // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
855   assert(MI.getOperand(OpNo).isReg());
856   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
857                                        STI) << 16;
858   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
859 
860   return (OffBits & 0x1FF) | RegBits;
861 }
862 
863 unsigned MipsMCCodeEmitter::
864 getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
865                       SmallVectorImpl<MCFixup> &Fixups,
866                       const MCSubtargetInfo &STI) const {
867   // Base register is encoded in bits 20-16, offset is encoded in bits 10-0.
868   assert(MI.getOperand(OpNo).isReg());
869   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
870                                        STI) << 16;
871   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
872 
873   return (OffBits & 0x07FF) | RegBits;
874 }
875 
876 unsigned MipsMCCodeEmitter::
877 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
878                       SmallVectorImpl<MCFixup> &Fixups,
879                       const MCSubtargetInfo &STI) const {
880   // opNum can be invalid if instruction had reglist as operand.
881   // MemOperand is always last operand of instruction (base + offset).
882   switch (MI.getOpcode()) {
883   default:
884     break;
885   case Mips::SWM32_MM:
886   case Mips::LWM32_MM:
887     OpNo = MI.getNumOperands() - 2;
888     break;
889   }
890 
891   // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
892   assert(MI.getOperand(OpNo).isReg());
893   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
894   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
895 
896   return (OffBits & 0x0FFF) | RegBits;
897 }
898 
899 unsigned MipsMCCodeEmitter::
900 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
901                       SmallVectorImpl<MCFixup> &Fixups,
902                       const MCSubtargetInfo &STI) const {
903   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
904   assert(MI.getOperand(OpNo).isReg());
905   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
906                                        STI) << 16;
907   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
908 
909   return (OffBits & 0xFFFF) | RegBits;
910 }
911 
912 unsigned MipsMCCodeEmitter::
913 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
914                        SmallVectorImpl<MCFixup> &Fixups,
915                        const MCSubtargetInfo &STI) const {
916   // opNum can be invalid if instruction had reglist as operand
917   // MemOperand is always last operand of instruction (base + offset)
918   switch (MI.getOpcode()) {
919   default:
920     break;
921   case Mips::SWM16_MM:
922   case Mips::SWM16_MMR6:
923   case Mips::LWM16_MM:
924   case Mips::LWM16_MMR6:
925     OpNo = MI.getNumOperands() - 2;
926     break;
927   }
928 
929   // Offset is encoded in bits 4-0.
930   assert(MI.getOperand(OpNo).isReg());
931   // Base register is always SP - thus it is not encoded.
932   assert(MI.getOperand(OpNo+1).isImm());
933   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
934 
935   return ((OffBits >> 2) & 0x0F);
936 }
937 
938 // FIXME: should be called getMSBEncoding
939 //
940 unsigned
941 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
942                                       SmallVectorImpl<MCFixup> &Fixups,
943                                       const MCSubtargetInfo &STI) const {
944   assert(MI.getOperand(OpNo-1).isImm());
945   assert(MI.getOperand(OpNo).isImm());
946   unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
947   unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
948 
949   return Position + Size - 1;
950 }
951 
952 template <unsigned Bits, int Offset>
953 unsigned
954 MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
955                                              SmallVectorImpl<MCFixup> &Fixups,
956                                              const MCSubtargetInfo &STI) const {
957   assert(MI.getOperand(OpNo).isImm());
958   unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
959   Value -= Offset;
960   return Value;
961 }
962 
963 unsigned
964 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
965                                          SmallVectorImpl<MCFixup> &Fixups,
966                                          const MCSubtargetInfo &STI) const {
967   const MCOperand &MO = MI.getOperand(OpNo);
968   if (MO.isImm()) {
969     // The immediate is encoded as 'immediate << 2'.
970     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
971     assert((Res & 3) == 0);
972     return Res >> 2;
973   }
974 
975   assert(MO.isExpr() &&
976          "getSimm19Lsl2Encoding expects only expressions or an immediate");
977 
978   const MCExpr *Expr = MO.getExpr();
979   Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2
980                                             : Mips::fixup_MIPS_PC19_S2;
981   Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
982   return 0;
983 }
984 
985 unsigned
986 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
987                                          SmallVectorImpl<MCFixup> &Fixups,
988                                          const MCSubtargetInfo &STI) const {
989   const MCOperand &MO = MI.getOperand(OpNo);
990   if (MO.isImm()) {
991     // The immediate is encoded as 'immediate << 3'.
992     unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
993     assert((Res & 7) == 0);
994     return Res >> 3;
995   }
996 
997   assert(MO.isExpr() &&
998          "getSimm18Lsl2Encoding expects only expressions or an immediate");
999 
1000   const MCExpr *Expr = MO.getExpr();
1001   Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
1002                                             : Mips::fixup_MIPS_PC18_S3;
1003   Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
1004   return 0;
1005 }
1006 
1007 unsigned
1008 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
1009                                         SmallVectorImpl<MCFixup> &Fixups,
1010                                         const MCSubtargetInfo &STI) const {
1011   assert(MI.getOperand(OpNo).isImm());
1012   const MCOperand &MO = MI.getOperand(OpNo);
1013   return MO.getImm() % 8;
1014 }
1015 
1016 unsigned
1017 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
1018                                     SmallVectorImpl<MCFixup> &Fixups,
1019                                     const MCSubtargetInfo &STI) const {
1020   assert(MI.getOperand(OpNo).isImm());
1021   const MCOperand &MO = MI.getOperand(OpNo);
1022   unsigned Value = MO.getImm();
1023   switch (Value) {
1024     case 128:   return 0x0;
1025     case 1:     return 0x1;
1026     case 2:     return 0x2;
1027     case 3:     return 0x3;
1028     case 4:     return 0x4;
1029     case 7:     return 0x5;
1030     case 8:     return 0x6;
1031     case 15:    return 0x7;
1032     case 16:    return 0x8;
1033     case 31:    return 0x9;
1034     case 32:    return 0xa;
1035     case 63:    return 0xb;
1036     case 64:    return 0xc;
1037     case 255:   return 0xd;
1038     case 32768: return 0xe;
1039     case 65535: return 0xf;
1040   }
1041   llvm_unreachable("Unexpected value");
1042 }
1043 
1044 unsigned
1045 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
1046                                           SmallVectorImpl<MCFixup> &Fixups,
1047                                           const MCSubtargetInfo &STI) const {
1048   unsigned res = 0;
1049 
1050   // Register list operand is always first operand of instruction and it is
1051   // placed before memory operand (register + imm).
1052 
1053   for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
1054     unsigned Reg = MI.getOperand(I).getReg();
1055     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
1056     if (RegNo != 31)
1057       res++;
1058     else
1059       res |= 0x10;
1060   }
1061   return res;
1062 }
1063 
1064 unsigned
1065 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
1066                                             SmallVectorImpl<MCFixup> &Fixups,
1067                                             const MCSubtargetInfo &STI) const {
1068   return (MI.getNumOperands() - 4);
1069 }
1070 
1071 unsigned
1072 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
1073                                           SmallVectorImpl<MCFixup> &Fixups,
1074                                           const MCSubtargetInfo &STI) const {
1075   unsigned res = 0;
1076 
1077   if (MI.getOperand(0).getReg() == Mips::A1 &&
1078       MI.getOperand(1).getReg() == Mips::A2)
1079     res = 0;
1080   else if (MI.getOperand(0).getReg() == Mips::A1 &&
1081            MI.getOperand(1).getReg() == Mips::A3)
1082     res = 1;
1083   else if (MI.getOperand(0).getReg() == Mips::A2 &&
1084            MI.getOperand(1).getReg() == Mips::A3)
1085     res = 2;
1086   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1087            MI.getOperand(1).getReg() == Mips::S5)
1088     res = 3;
1089   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1090            MI.getOperand(1).getReg() == Mips::S6)
1091     res = 4;
1092   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1093            MI.getOperand(1).getReg() == Mips::A1)
1094     res = 5;
1095   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1096            MI.getOperand(1).getReg() == Mips::A2)
1097     res = 6;
1098   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1099            MI.getOperand(1).getReg() == Mips::A3)
1100     res = 7;
1101 
1102   return res;
1103 }
1104 
1105 unsigned
1106 MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
1107                                             SmallVectorImpl<MCFixup> &Fixups,
1108                                             const MCSubtargetInfo &STI) const {
1109   assert(((OpNo == 2) || (OpNo == 3)) &&
1110          "Unexpected OpNo for movep operand encoding!");
1111 
1112   MCOperand Op = MI.getOperand(OpNo);
1113   assert(Op.isReg() && "Operand of movep is not a register!");
1114   switch (Op.getReg()) {
1115   default:
1116     llvm_unreachable("Unknown register for movep!");
1117   case Mips::ZERO:  return 0;
1118   case Mips::S1:    return 1;
1119   case Mips::V0:    return 2;
1120   case Mips::V1:    return 3;
1121   case Mips::S0:    return 4;
1122   case Mips::S2:    return 5;
1123   case Mips::S3:    return 6;
1124   case Mips::S4:    return 7;
1125   }
1126 }
1127 
1128 unsigned
1129 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1130                                          SmallVectorImpl<MCFixup> &Fixups,
1131                                          const MCSubtargetInfo &STI) const {
1132   const MCOperand &MO = MI.getOperand(OpNo);
1133   assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
1134   // The immediate is encoded as 'immediate >> 2'.
1135   unsigned Res = static_cast<unsigned>(MO.getImm());
1136   assert((Res & 3) == 0);
1137   return Res >> 2;
1138 }
1139 
1140 #include "MipsGenMCCodeEmitter.inc"
1141