1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MCTargetDesc/MipsAsmBackend.h" 16 #include "MCTargetDesc/MipsFixupKinds.h" 17 #include "MCTargetDesc/MipsMCExpr.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/MC/MCAsmBackend.h" 21 #include "llvm/MC/MCAssembler.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCDirectives.h" 24 #include "llvm/MC/MCELFObjectWriter.h" 25 #include "llvm/MC/MCFixupKindInfo.h" 26 #include "llvm/MC/MCObjectWriter.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/MC/MCTargetOptions.h" 29 #include "llvm/MC/MCValue.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/Format.h" 32 #include "llvm/Support/MathExtras.h" 33 #include "llvm/Support/raw_ostream.h" 34 35 using namespace llvm; 36 37 // Prepare value for the target space for it 38 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 39 MCContext &Ctx) { 40 41 unsigned Kind = Fixup.getKind(); 42 43 // Add/subtract and shift 44 switch (Kind) { 45 default: 46 return 0; 47 case FK_Data_2: 48 case Mips::fixup_Mips_LO16: 49 case Mips::fixup_Mips_GPREL16: 50 case Mips::fixup_Mips_GPOFF_HI: 51 case Mips::fixup_Mips_GPOFF_LO: 52 case Mips::fixup_Mips_GOT_PAGE: 53 case Mips::fixup_Mips_GOT_OFST: 54 case Mips::fixup_Mips_GOT_DISP: 55 case Mips::fixup_Mips_GOT_LO16: 56 case Mips::fixup_Mips_CALL_LO16: 57 case Mips::fixup_MICROMIPS_LO16: 58 case Mips::fixup_MICROMIPS_GOT_PAGE: 59 case Mips::fixup_MICROMIPS_GOT_OFST: 60 case Mips::fixup_MICROMIPS_GOT_DISP: 61 case Mips::fixup_MIPS_PCLO16: 62 Value &= 0xffff; 63 break; 64 case FK_DTPRel_4: 65 case FK_DTPRel_8: 66 case FK_TPRel_4: 67 case FK_TPRel_8: 68 case FK_GPRel_4: 69 case FK_Data_4: 70 case FK_Data_8: 71 case Mips::fixup_Mips_SUB: 72 case Mips::fixup_MICROMIPS_SUB: 73 break; 74 case Mips::fixup_Mips_PC16: 75 // The displacement is then divided by 4 to give us an 18 bit 76 // address range. Forcing a signed division because Value can be negative. 77 Value = (int64_t)Value / 4; 78 // We now check if Value can be encoded as a 16-bit signed immediate. 79 if (!isInt<16>(Value)) { 80 Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); 81 return 0; 82 } 83 break; 84 case Mips::fixup_MIPS_PC19_S2: 85 case Mips::fixup_MICROMIPS_PC19_S2: 86 // Forcing a signed division because Value can be negative. 87 Value = (int64_t)Value / 4; 88 // We now check if Value can be encoded as a 19-bit signed immediate. 89 if (!isInt<19>(Value)) { 90 Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup"); 91 return 0; 92 } 93 break; 94 case Mips::fixup_Mips_26: 95 // So far we are only using this type for jumps. 96 // The displacement is then divided by 4 to give us an 28 bit 97 // address range. 98 Value >>= 2; 99 break; 100 case Mips::fixup_Mips_HI16: 101 case Mips::fixup_Mips_GOT: 102 case Mips::fixup_MICROMIPS_GOT16: 103 case Mips::fixup_Mips_GOT_HI16: 104 case Mips::fixup_Mips_CALL_HI16: 105 case Mips::fixup_MICROMIPS_HI16: 106 case Mips::fixup_MIPS_PCHI16: 107 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 108 Value = ((Value + 0x8000) >> 16) & 0xffff; 109 break; 110 case Mips::fixup_Mips_HIGHER: 111 // Get the 3rd 16-bits. 112 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 113 break; 114 case Mips::fixup_Mips_HIGHEST: 115 // Get the 4th 16-bits. 116 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 117 break; 118 case Mips::fixup_MICROMIPS_26_S1: 119 Value >>= 1; 120 break; 121 case Mips::fixup_MICROMIPS_PC7_S1: 122 Value -= 4; 123 // Forcing a signed division because Value can be negative. 124 Value = (int64_t) Value / 2; 125 // We now check if Value can be encoded as a 7-bit signed immediate. 126 if (!isInt<7>(Value)) { 127 Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup"); 128 return 0; 129 } 130 break; 131 case Mips::fixup_MICROMIPS_PC10_S1: 132 Value -= 2; 133 // Forcing a signed division because Value can be negative. 134 Value = (int64_t) Value / 2; 135 // We now check if Value can be encoded as a 10-bit signed immediate. 136 if (!isInt<10>(Value)) { 137 Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup"); 138 return 0; 139 } 140 break; 141 case Mips::fixup_MICROMIPS_PC16_S1: 142 Value -= 4; 143 // Forcing a signed division because Value can be negative. 144 Value = (int64_t)Value / 2; 145 // We now check if Value can be encoded as a 16-bit signed immediate. 146 if (!isInt<16>(Value)) { 147 Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); 148 return 0; 149 } 150 break; 151 case Mips::fixup_MIPS_PC18_S3: 152 // Forcing a signed division because Value can be negative. 153 Value = (int64_t)Value / 8; 154 // We now check if Value can be encoded as a 18-bit signed immediate. 155 if (!isInt<18>(Value)) { 156 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); 157 return 0; 158 } 159 break; 160 case Mips::fixup_MICROMIPS_PC18_S3: 161 // Check alignment. 162 if ((Value & 7)) { 163 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); 164 } 165 // Forcing a signed division because Value can be negative. 166 Value = (int64_t)Value / 8; 167 // We now check if Value can be encoded as a 18-bit signed immediate. 168 if (!isInt<18>(Value)) { 169 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); 170 return 0; 171 } 172 break; 173 case Mips::fixup_MIPS_PC21_S2: 174 // Forcing a signed division because Value can be negative. 175 Value = (int64_t) Value / 4; 176 // We now check if Value can be encoded as a 21-bit signed immediate. 177 if (!isInt<21>(Value)) { 178 Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); 179 return 0; 180 } 181 break; 182 case Mips::fixup_MIPS_PC26_S2: 183 // Forcing a signed division because Value can be negative. 184 Value = (int64_t) Value / 4; 185 // We now check if Value can be encoded as a 26-bit signed immediate. 186 if (!isInt<26>(Value)) { 187 Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup"); 188 return 0; 189 } 190 break; 191 case Mips::fixup_MICROMIPS_PC26_S1: 192 // Forcing a signed division because Value can be negative. 193 Value = (int64_t)Value / 2; 194 // We now check if Value can be encoded as a 26-bit signed immediate. 195 if (!isInt<26>(Value)) { 196 Ctx.reportFatalError(Fixup.getLoc(), "out of range PC26 fixup"); 197 return 0; 198 } 199 break; 200 case Mips::fixup_MICROMIPS_PC21_S1: 201 // Forcing a signed division because Value can be negative. 202 Value = (int64_t)Value / 2; 203 // We now check if Value can be encoded as a 21-bit signed immediate. 204 if (!isInt<21>(Value)) { 205 Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); 206 return 0; 207 } 208 break; 209 } 210 211 return Value; 212 } 213 214 std::unique_ptr<MCObjectWriter> 215 MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { 216 return createMipsELFObjectWriter(OS, TheTriple, IsN32); 217 } 218 219 // Little-endian fixup data byte ordering: 220 // mips32r2: a | b | x | x 221 // microMIPS: x | x | a | b 222 223 static bool needsMMLEByteOrder(unsigned Kind) { 224 return Kind != Mips::fixup_MICROMIPS_PC10_S1 && 225 Kind >= Mips::fixup_MICROMIPS_26_S1 && 226 Kind < Mips::LastTargetFixupKind; 227 } 228 229 // Calculate index for microMIPS specific little endian byte order 230 static unsigned calculateMMLEIndex(unsigned i) { 231 assert(i <= 3 && "Index out of range!"); 232 233 return (1 - i / 2) * 2 + i % 2; 234 } 235 236 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 237 /// data fragment, at the offset specified by the fixup and following the 238 /// fixup kind as appropriate. 239 void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 240 const MCValue &Target, 241 MutableArrayRef<char> Data, uint64_t Value, 242 bool IsResolved) const { 243 MCFixupKind Kind = Fixup.getKind(); 244 MCContext &Ctx = Asm.getContext(); 245 Value = adjustFixupValue(Fixup, Value, Ctx); 246 247 if (!Value) 248 return; // Doesn't change encoding. 249 250 // Where do we start in the object 251 unsigned Offset = Fixup.getOffset(); 252 // Number of bytes we need to fixup 253 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 254 // Used to point to big endian bytes 255 unsigned FullSize; 256 257 switch ((unsigned)Kind) { 258 case FK_Data_2: 259 case Mips::fixup_Mips_16: 260 case Mips::fixup_MICROMIPS_PC10_S1: 261 FullSize = 2; 262 break; 263 case FK_Data_8: 264 case Mips::fixup_Mips_64: 265 FullSize = 8; 266 break; 267 case FK_Data_4: 268 default: 269 FullSize = 4; 270 break; 271 } 272 273 // Grab current value, if any, from bits. 274 uint64_t CurVal = 0; 275 276 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); 277 278 for (unsigned i = 0; i != NumBytes; ++i) { 279 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 280 : i) 281 : (FullSize - 1 - i); 282 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 283 } 284 285 uint64_t Mask = ((uint64_t)(-1) >> 286 (64 - getFixupKindInfo(Kind).TargetSize)); 287 CurVal |= Value & Mask; 288 289 // Write out the fixed up bytes back to the code/data bits. 290 for (unsigned i = 0; i != NumBytes; ++i) { 291 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 292 : i) 293 : (FullSize - 1 - i); 294 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 295 } 296 } 297 298 Optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const { 299 return StringSwitch<Optional<MCFixupKind>>(Name) 300 .Case("R_MIPS_NONE", (MCFixupKind)Mips::fixup_Mips_NONE) 301 .Case("R_MIPS_32", FK_Data_4) 302 .Default(MCAsmBackend::getFixupKind(Name)); 303 } 304 305 const MCFixupKindInfo &MipsAsmBackend:: 306 getFixupKindInfo(MCFixupKind Kind) const { 307 const static MCFixupKindInfo LittleEndianInfos[] = { 308 // This table *must* be in same the order of fixup_* kinds in 309 // MipsFixupKinds.h. 310 // 311 // name offset bits flags 312 { "fixup_Mips_NONE", 0, 0, 0 }, 313 { "fixup_Mips_16", 0, 16, 0 }, 314 { "fixup_Mips_32", 0, 32, 0 }, 315 { "fixup_Mips_REL32", 0, 32, 0 }, 316 { "fixup_Mips_26", 0, 26, 0 }, 317 { "fixup_Mips_HI16", 0, 16, 0 }, 318 { "fixup_Mips_LO16", 0, 16, 0 }, 319 { "fixup_Mips_GPREL16", 0, 16, 0 }, 320 { "fixup_Mips_LITERAL", 0, 16, 0 }, 321 { "fixup_Mips_GOT", 0, 16, 0 }, 322 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 323 { "fixup_Mips_CALL16", 0, 16, 0 }, 324 { "fixup_Mips_GPREL32", 0, 32, 0 }, 325 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 326 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 327 { "fixup_Mips_64", 0, 64, 0 }, 328 { "fixup_Mips_TLSGD", 0, 16, 0 }, 329 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 330 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 331 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 332 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 333 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 334 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 335 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 336 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 337 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 338 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 339 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 340 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 341 { "fixup_Mips_HIGHER", 0, 16, 0 }, 342 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 343 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 344 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 345 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 346 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 347 { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 348 { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 349 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 350 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 351 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 352 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 353 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 354 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 355 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 356 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 357 { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, 358 { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 359 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 360 { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 361 { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 362 { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 363 { "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 364 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 365 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 366 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 367 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 368 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, 369 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, 370 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 371 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 372 { "fixup_MICROMIPS_GOTTPREL", 0, 16, 0 }, 373 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 374 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }, 375 { "fixup_Mips_SUB", 0, 64, 0 }, 376 { "fixup_MICROMIPS_SUB", 0, 64, 0 } 377 }; 378 static_assert(array_lengthof(LittleEndianInfos) == Mips::NumTargetFixupKinds, 379 "Not all MIPS little endian fixup kinds added!"); 380 381 const static MCFixupKindInfo BigEndianInfos[] = { 382 // This table *must* be in same the order of fixup_* kinds in 383 // MipsFixupKinds.h. 384 // 385 // name offset bits flags 386 { "fixup_Mips_NONE", 0, 0, 0 }, 387 { "fixup_Mips_16", 16, 16, 0 }, 388 { "fixup_Mips_32", 0, 32, 0 }, 389 { "fixup_Mips_REL32", 0, 32, 0 }, 390 { "fixup_Mips_26", 6, 26, 0 }, 391 { "fixup_Mips_HI16", 16, 16, 0 }, 392 { "fixup_Mips_LO16", 16, 16, 0 }, 393 { "fixup_Mips_GPREL16", 16, 16, 0 }, 394 { "fixup_Mips_LITERAL", 16, 16, 0 }, 395 { "fixup_Mips_GOT", 16, 16, 0 }, 396 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 397 { "fixup_Mips_CALL16", 16, 16, 0 }, 398 { "fixup_Mips_GPREL32", 0, 32, 0 }, 399 { "fixup_Mips_SHIFT5", 21, 5, 0 }, 400 { "fixup_Mips_SHIFT6", 21, 5, 0 }, 401 { "fixup_Mips_64", 0, 64, 0 }, 402 { "fixup_Mips_TLSGD", 16, 16, 0 }, 403 { "fixup_Mips_GOTTPREL", 16, 16, 0 }, 404 { "fixup_Mips_TPREL_HI", 16, 16, 0 }, 405 { "fixup_Mips_TPREL_LO", 16, 16, 0 }, 406 { "fixup_Mips_TLSLDM", 16, 16, 0 }, 407 { "fixup_Mips_DTPREL_HI", 16, 16, 0 }, 408 { "fixup_Mips_DTPREL_LO", 16, 16, 0 }, 409 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 410 { "fixup_Mips_GPOFF_HI", 16, 16, 0 }, 411 { "fixup_Mips_GPOFF_LO", 16, 16, 0 }, 412 { "fixup_Mips_GOT_PAGE", 16, 16, 0 }, 413 { "fixup_Mips_GOT_OFST", 16, 16, 0 }, 414 { "fixup_Mips_GOT_DISP", 16, 16, 0 }, 415 { "fixup_Mips_HIGHER", 16, 16, 0 }, 416 { "fixup_Mips_HIGHEST", 16, 16, 0 }, 417 { "fixup_Mips_GOT_HI16", 16, 16, 0 }, 418 { "fixup_Mips_GOT_LO16", 16, 16, 0 }, 419 { "fixup_Mips_CALL_HI16", 16, 16, 0 }, 420 { "fixup_Mips_CALL_LO16", 16, 16, 0 }, 421 { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel }, 422 { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 423 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, 424 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 425 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 426 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 427 { "fixup_MICROMIPS_26_S1", 6, 26, 0 }, 428 { "fixup_MICROMIPS_HI16", 16, 16, 0 }, 429 { "fixup_MICROMIPS_LO16", 16, 16, 0 }, 430 { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, 431 { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, 432 { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, 433 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 434 { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 435 { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel }, 436 { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel }, 437 { "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel }, 438 { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, 439 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, 440 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, 441 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 }, 442 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 }, 443 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 }, 444 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, 445 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, 446 { "fixup_MICROMIPS_GOTTPREL", 16, 16, 0 }, 447 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, 448 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }, 449 { "fixup_Mips_SUB", 0, 64, 0 }, 450 { "fixup_MICROMIPS_SUB", 0, 64, 0 } 451 }; 452 static_assert(array_lengthof(BigEndianInfos) == Mips::NumTargetFixupKinds, 453 "Not all MIPS big endian fixup kinds added!"); 454 455 if (Kind < FirstTargetFixupKind) 456 return MCAsmBackend::getFixupKindInfo(Kind); 457 458 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 459 "Invalid kind!"); 460 461 if (IsLittle) 462 return LittleEndianInfos[Kind - FirstTargetFixupKind]; 463 return BigEndianInfos[Kind - FirstTargetFixupKind]; 464 } 465 466 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 467 /// to the given output. If the target cannot generate such a sequence, 468 /// it should return an error. 469 /// 470 /// \return - True on success. 471 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 472 // Check for a less than instruction size number of bytes 473 // FIXME: 16 bit instructions are not handled yet here. 474 // We shouldn't be using a hard coded number for instruction size. 475 476 // If the count is not 4-byte aligned, we must be writing data into the text 477 // section (otherwise we have unaligned instructions, and thus have far 478 // bigger problems), so just write zeros instead. 479 OW->WriteZeros(Count); 480 return true; 481 } 482 483 MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, 484 const MCSubtargetInfo &STI, 485 const MCRegisterInfo &MRI, 486 const MCTargetOptions &Options) { 487 return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), 488 Options.ABIName == "n32"); 489 } 490