1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MCTargetDesc/MipsFixupKinds.h" 16 #include "MCTargetDesc/MipsAsmBackend.h" 17 #include "MCTargetDesc/MipsMCTargetDesc.h" 18 #include "llvm/MC/MCAsmBackend.h" 19 #include "llvm/MC/MCAssembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDirectives.h" 22 #include "llvm/MC/MCELFObjectWriter.h" 23 #include "llvm/MC/MCFixupKindInfo.h" 24 #include "llvm/MC/MCObjectWriter.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/raw_ostream.h" 29 30 using namespace llvm; 31 32 // Prepare value for the target space for it 33 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 34 MCContext *Ctx = NULL) { 35 36 unsigned Kind = Fixup.getKind(); 37 38 // Add/subtract and shift 39 switch (Kind) { 40 default: 41 return 0; 42 case FK_Data_2: 43 case FK_GPRel_4: 44 case FK_Data_4: 45 case FK_Data_8: 46 case Mips::fixup_Mips_LO16: 47 case Mips::fixup_Mips_GPREL16: 48 case Mips::fixup_Mips_GPOFF_HI: 49 case Mips::fixup_Mips_GPOFF_LO: 50 case Mips::fixup_Mips_GOT_PAGE: 51 case Mips::fixup_Mips_GOT_OFST: 52 case Mips::fixup_Mips_GOT_DISP: 53 case Mips::fixup_Mips_GOT_LO16: 54 case Mips::fixup_Mips_CALL_LO16: 55 case Mips::fixup_MICROMIPS_LO16: 56 case Mips::fixup_MICROMIPS_GOT_PAGE: 57 case Mips::fixup_MICROMIPS_GOT_OFST: 58 case Mips::fixup_MICROMIPS_GOT_DISP: 59 break; 60 case Mips::fixup_Mips_PC16: 61 // So far we are only using this type for branches. 62 // For branches we start 1 instruction after the branch 63 // so the displacement will be one instruction size less. 64 Value -= 4; 65 // The displacement is then divided by 4 to give us an 18 bit 66 // address range. Forcing a signed division because Value can be negative. 67 Value = (int64_t)Value / 4; 68 // We now check if Value can be encoded as a 16-bit signed immediate. 69 if (!isIntN(16, Value) && Ctx) 70 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup"); 71 break; 72 case Mips::fixup_Mips_26: 73 // So far we are only using this type for jumps. 74 // The displacement is then divided by 4 to give us an 28 bit 75 // address range. 76 Value >>= 2; 77 break; 78 case Mips::fixup_Mips_HI16: 79 case Mips::fixup_Mips_GOT_Local: 80 case Mips::fixup_Mips_GOT_HI16: 81 case Mips::fixup_Mips_CALL_HI16: 82 case Mips::fixup_MICROMIPS_HI16: 83 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 84 Value = ((Value + 0x8000) >> 16) & 0xffff; 85 break; 86 case Mips::fixup_Mips_HIGHER: 87 // Get the 3rd 16-bits. 88 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 89 break; 90 case Mips::fixup_Mips_HIGHEST: 91 // Get the 4th 16-bits. 92 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 93 break; 94 case Mips::fixup_MICROMIPS_26_S1: 95 Value >>= 1; 96 break; 97 case Mips::fixup_MICROMIPS_PC16_S1: 98 Value -= 4; 99 // Forcing a signed division because Value can be negative. 100 Value = (int64_t)Value / 2; 101 // We now check if Value can be encoded as a 16-bit signed immediate. 102 if (!isIntN(16, Value) && Ctx) 103 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup"); 104 break; 105 } 106 107 return Value; 108 } 109 110 MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const { 111 return createMipsELFObjectWriter(OS, 112 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 113 } 114 115 // Little-endian fixup data byte ordering: 116 // mips32r2: a | b | x | x 117 // microMIPS: x | x | a | b 118 119 static bool needsMMLEByteOrder(unsigned Kind) { 120 return Kind >= Mips::fixup_MICROMIPS_26_S1 && 121 Kind < Mips::LastTargetFixupKind; 122 } 123 124 // Calculate index for microMIPS specific little endian byte order 125 static unsigned calculateMMLEIndex(unsigned i) { 126 assert(i <= 3 && "Index out of range!"); 127 128 return (1 - i / 2) * 2 + i % 2; 129 } 130 131 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 132 /// data fragment, at the offset specified by the fixup and following the 133 /// fixup kind as appropriate. 134 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 135 unsigned DataSize, uint64_t Value, 136 bool IsPCRel) const { 137 MCFixupKind Kind = Fixup.getKind(); 138 Value = adjustFixupValue(Fixup, Value); 139 140 if (!Value) 141 return; // Doesn't change encoding. 142 143 // Where do we start in the object 144 unsigned Offset = Fixup.getOffset(); 145 // Number of bytes we need to fixup 146 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 147 // Used to point to big endian bytes 148 unsigned FullSize; 149 150 switch ((unsigned)Kind) { 151 case FK_Data_2: 152 case Mips::fixup_Mips_16: 153 FullSize = 2; 154 break; 155 case FK_Data_8: 156 case Mips::fixup_Mips_64: 157 FullSize = 8; 158 break; 159 case FK_Data_4: 160 default: 161 FullSize = 4; 162 break; 163 } 164 165 // Grab current value, if any, from bits. 166 uint64_t CurVal = 0; 167 168 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); 169 170 for (unsigned i = 0; i != NumBytes; ++i) { 171 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 172 : i) 173 : (FullSize - 1 - i); 174 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 175 } 176 177 uint64_t Mask = ((uint64_t)(-1) >> 178 (64 - getFixupKindInfo(Kind).TargetSize)); 179 CurVal |= Value & Mask; 180 181 // Write out the fixed up bytes back to the code/data bits. 182 for (unsigned i = 0; i != NumBytes; ++i) { 183 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 184 : i) 185 : (FullSize - 1 - i); 186 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 187 } 188 } 189 190 const MCFixupKindInfo &MipsAsmBackend:: 191 getFixupKindInfo(MCFixupKind Kind) const { 192 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { 193 // This table *must* be in same the order of fixup_* kinds in 194 // MipsFixupKinds.h. 195 // 196 // name offset bits flags 197 { "fixup_Mips_16", 0, 16, 0 }, 198 { "fixup_Mips_32", 0, 32, 0 }, 199 { "fixup_Mips_REL32", 0, 32, 0 }, 200 { "fixup_Mips_26", 0, 26, 0 }, 201 { "fixup_Mips_HI16", 0, 16, 0 }, 202 { "fixup_Mips_LO16", 0, 16, 0 }, 203 { "fixup_Mips_GPREL16", 0, 16, 0 }, 204 { "fixup_Mips_LITERAL", 0, 16, 0 }, 205 { "fixup_Mips_GOT_Global", 0, 16, 0 }, 206 { "fixup_Mips_GOT_Local", 0, 16, 0 }, 207 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 208 { "fixup_Mips_CALL16", 0, 16, 0 }, 209 { "fixup_Mips_GPREL32", 0, 32, 0 }, 210 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 211 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 212 { "fixup_Mips_64", 0, 64, 0 }, 213 { "fixup_Mips_TLSGD", 0, 16, 0 }, 214 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 215 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 216 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 217 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 218 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 219 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 220 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 221 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 222 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 223 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 224 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 225 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 226 { "fixup_Mips_HIGHER", 0, 16, 0 }, 227 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 228 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 229 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 230 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 231 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 232 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 233 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 234 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 235 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 236 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 237 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 238 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 239 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 240 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 241 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, 242 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, 243 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 244 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 245 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 246 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } 247 }; 248 249 if (Kind < FirstTargetFixupKind) 250 return MCAsmBackend::getFixupKindInfo(Kind); 251 252 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 253 "Invalid kind!"); 254 return Infos[Kind - FirstTargetFixupKind]; 255 } 256 257 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 258 /// to the given output. If the target cannot generate such a sequence, 259 /// it should return an error. 260 /// 261 /// \return - True on success. 262 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 263 // Check for a less than instruction size number of bytes 264 // FIXME: 16 bit instructions are not handled yet here. 265 // We shouldn't be using a hard coded number for instruction size. 266 if (Count % 4) return false; 267 268 uint64_t NumNops = Count / 4; 269 for (uint64_t i = 0; i != NumNops; ++i) 270 OW->Write32(0); 271 return true; 272 } 273 274 /// processFixupValue - Target hook to process the literal value of a fixup 275 /// if necessary. 276 void MipsAsmBackend::processFixupValue(const MCAssembler &Asm, 277 const MCAsmLayout &Layout, 278 const MCFixup &Fixup, 279 const MCFragment *DF, 280 const MCValue &Target, 281 uint64_t &Value, 282 bool &IsResolved) { 283 // At this point we'll ignore the value returned by adjustFixupValue as 284 // we are only checking if the fixup can be applied correctly. We have 285 // access to MCContext from here which allows us to report a fatal error 286 // with *possibly* a source code location. 287 (void)adjustFixupValue(Fixup, Value, &Asm.getContext()); 288 } 289 290 // MCAsmBackend 291 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 292 const MCRegisterInfo &MRI, 293 StringRef TT, 294 StringRef CPU) { 295 return new MipsAsmBackend(T, Triple(TT).getOS(), 296 /*IsLittle*/true, /*Is64Bit*/false); 297 } 298 299 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 300 const MCRegisterInfo &MRI, 301 StringRef TT, 302 StringRef CPU) { 303 return new MipsAsmBackend(T, Triple(TT).getOS(), 304 /*IsLittle*/false, /*Is64Bit*/false); 305 } 306 307 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 308 const MCRegisterInfo &MRI, 309 StringRef TT, 310 StringRef CPU) { 311 return new MipsAsmBackend(T, Triple(TT).getOS(), 312 /*IsLittle*/true, /*Is64Bit*/true); 313 } 314 315 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 316 const MCRegisterInfo &MRI, 317 StringRef TT, 318 StringRef CPU) { 319 return new MipsAsmBackend(T, Triple(TT).getOS(), 320 /*IsLittle*/false, /*Is64Bit*/true); 321 } 322