1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MCTargetDesc/MipsFixupKinds.h" 16 #include "MCTargetDesc/MipsAsmBackend.h" 17 #include "MCTargetDesc/MipsMCExpr.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "llvm/MC/MCAsmBackend.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDirectives.h" 23 #include "llvm/MC/MCELFObjectWriter.h" 24 #include "llvm/MC/MCFixupKindInfo.h" 25 #include "llvm/MC/MCObjectWriter.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCValue.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/Format.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Support/raw_ostream.h" 32 33 using namespace llvm; 34 35 // Prepare value for the target space for it 36 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 37 MCContext *Ctx = nullptr) { 38 39 unsigned Kind = Fixup.getKind(); 40 41 // Add/subtract and shift 42 switch (Kind) { 43 default: 44 return 0; 45 case FK_Data_2: 46 case Mips::fixup_Mips_LO16: 47 case Mips::fixup_Mips_GPREL16: 48 case Mips::fixup_Mips_GPOFF_HI: 49 case Mips::fixup_Mips_GPOFF_LO: 50 case Mips::fixup_Mips_GOT_PAGE: 51 case Mips::fixup_Mips_GOT_OFST: 52 case Mips::fixup_Mips_GOT_DISP: 53 case Mips::fixup_Mips_GOT_LO16: 54 case Mips::fixup_Mips_CALL_LO16: 55 case Mips::fixup_MICROMIPS_LO16: 56 case Mips::fixup_MICROMIPS_GOT_PAGE: 57 case Mips::fixup_MICROMIPS_GOT_OFST: 58 case Mips::fixup_MICROMIPS_GOT_DISP: 59 case Mips::fixup_MIPS_PCLO16: 60 Value &= 0xffff; 61 break; 62 case FK_GPRel_4: 63 case FK_Data_4: 64 case FK_Data_8: 65 case Mips::fixup_Mips_SUB: 66 case Mips::fixup_MICROMIPS_SUB: 67 break; 68 case Mips::fixup_Mips_PC16: 69 // The displacement is then divided by 4 to give us an 18 bit 70 // address range. Forcing a signed division because Value can be negative. 71 Value = (int64_t)Value / 4; 72 // We now check if Value can be encoded as a 16-bit signed immediate. 73 if (!isInt<16>(Value) && Ctx) { 74 Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup"); 75 return 0; 76 } 77 break; 78 case Mips::fixup_MIPS_PC19_S2: 79 case Mips::fixup_MICROMIPS_PC19_S2: 80 // Forcing a signed division because Value can be negative. 81 Value = (int64_t)Value / 4; 82 // We now check if Value can be encoded as a 19-bit signed immediate. 83 if (!isInt<19>(Value) && Ctx) { 84 Ctx->reportError(Fixup.getLoc(), "out of range PC19 fixup"); 85 return 0; 86 } 87 break; 88 case Mips::fixup_Mips_26: 89 // So far we are only using this type for jumps. 90 // The displacement is then divided by 4 to give us an 28 bit 91 // address range. 92 Value >>= 2; 93 break; 94 case Mips::fixup_Mips_HI16: 95 case Mips::fixup_Mips_GOT: 96 case Mips::fixup_MICROMIPS_GOT16: 97 case Mips::fixup_Mips_GOT_HI16: 98 case Mips::fixup_Mips_CALL_HI16: 99 case Mips::fixup_MICROMIPS_HI16: 100 case Mips::fixup_MIPS_PCHI16: 101 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 102 Value = ((Value + 0x8000) >> 16) & 0xffff; 103 break; 104 case Mips::fixup_Mips_HIGHER: 105 // Get the 3rd 16-bits. 106 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 107 break; 108 case Mips::fixup_Mips_HIGHEST: 109 // Get the 4th 16-bits. 110 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 111 break; 112 case Mips::fixup_MICROMIPS_26_S1: 113 Value >>= 1; 114 break; 115 case Mips::fixup_MICROMIPS_PC7_S1: 116 Value -= 4; 117 // Forcing a signed division because Value can be negative. 118 Value = (int64_t) Value / 2; 119 // We now check if Value can be encoded as a 7-bit signed immediate. 120 if (!isInt<7>(Value) && Ctx) { 121 Ctx->reportError(Fixup.getLoc(), "out of range PC7 fixup"); 122 return 0; 123 } 124 break; 125 case Mips::fixup_MICROMIPS_PC10_S1: 126 Value -= 2; 127 // Forcing a signed division because Value can be negative. 128 Value = (int64_t) Value / 2; 129 // We now check if Value can be encoded as a 10-bit signed immediate. 130 if (!isInt<10>(Value) && Ctx) { 131 Ctx->reportError(Fixup.getLoc(), "out of range PC10 fixup"); 132 return 0; 133 } 134 break; 135 case Mips::fixup_MICROMIPS_PC16_S1: 136 Value -= 4; 137 // Forcing a signed division because Value can be negative. 138 Value = (int64_t)Value / 2; 139 // We now check if Value can be encoded as a 16-bit signed immediate. 140 if (!isInt<16>(Value) && Ctx) { 141 Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup"); 142 return 0; 143 } 144 break; 145 case Mips::fixup_MIPS_PC18_S3: 146 // Forcing a signed division because Value can be negative. 147 Value = (int64_t)Value / 8; 148 // We now check if Value can be encoded as a 18-bit signed immediate. 149 if (!isInt<18>(Value) && Ctx) { 150 Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup"); 151 return 0; 152 } 153 break; 154 case Mips::fixup_MICROMIPS_PC18_S3: 155 // Check alignment. 156 if ((Value & 7) && Ctx) { 157 Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup"); 158 } 159 // Forcing a signed division because Value can be negative. 160 Value = (int64_t)Value / 8; 161 // We now check if Value can be encoded as a 18-bit signed immediate. 162 if (!isInt<18>(Value) && Ctx) { 163 Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup"); 164 return 0; 165 } 166 break; 167 case Mips::fixup_MIPS_PC21_S2: 168 // Forcing a signed division because Value can be negative. 169 Value = (int64_t) Value / 4; 170 // We now check if Value can be encoded as a 21-bit signed immediate. 171 if (!isInt<21>(Value) && Ctx) { 172 Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup"); 173 return 0; 174 } 175 break; 176 case Mips::fixup_MIPS_PC26_S2: 177 // Forcing a signed division because Value can be negative. 178 Value = (int64_t) Value / 4; 179 // We now check if Value can be encoded as a 26-bit signed immediate. 180 if (!isInt<26>(Value) && Ctx) { 181 Ctx->reportError(Fixup.getLoc(), "out of range PC26 fixup"); 182 return 0; 183 } 184 break; 185 case Mips::fixup_MICROMIPS_PC26_S1: 186 // Forcing a signed division because Value can be negative. 187 Value = (int64_t)Value / 2; 188 // We now check if Value can be encoded as a 26-bit signed immediate. 189 if (!isInt<26>(Value) && Ctx) { 190 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC26 fixup"); 191 return 0; 192 } 193 break; 194 case Mips::fixup_MICROMIPS_PC21_S1: 195 // Forcing a signed division because Value can be negative. 196 Value = (int64_t)Value / 2; 197 // We now check if Value can be encoded as a 21-bit signed immediate. 198 if (!isInt<21>(Value) && Ctx) { 199 Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup"); 200 return 0; 201 } 202 break; 203 } 204 205 return Value; 206 } 207 208 MCObjectWriter * 209 MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { 210 return createMipsELFObjectWriter(OS, 211 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 212 } 213 214 // Little-endian fixup data byte ordering: 215 // mips32r2: a | b | x | x 216 // microMIPS: x | x | a | b 217 218 static bool needsMMLEByteOrder(unsigned Kind) { 219 return Kind != Mips::fixup_MICROMIPS_PC10_S1 && 220 Kind >= Mips::fixup_MICROMIPS_26_S1 && 221 Kind < Mips::LastTargetFixupKind; 222 } 223 224 // Calculate index for microMIPS specific little endian byte order 225 static unsigned calculateMMLEIndex(unsigned i) { 226 assert(i <= 3 && "Index out of range!"); 227 228 return (1 - i / 2) * 2 + i % 2; 229 } 230 231 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 232 /// data fragment, at the offset specified by the fixup and following the 233 /// fixup kind as appropriate. 234 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 235 unsigned DataSize, uint64_t Value, 236 bool IsPCRel) const { 237 MCFixupKind Kind = Fixup.getKind(); 238 Value = adjustFixupValue(Fixup, Value); 239 240 if (!Value) 241 return; // Doesn't change encoding. 242 243 // Where do we start in the object 244 unsigned Offset = Fixup.getOffset(); 245 // Number of bytes we need to fixup 246 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 247 // Used to point to big endian bytes 248 unsigned FullSize; 249 250 switch ((unsigned)Kind) { 251 case FK_Data_2: 252 case Mips::fixup_Mips_16: 253 case Mips::fixup_MICROMIPS_PC10_S1: 254 FullSize = 2; 255 break; 256 case FK_Data_8: 257 case Mips::fixup_Mips_64: 258 FullSize = 8; 259 break; 260 case FK_Data_4: 261 default: 262 FullSize = 4; 263 break; 264 } 265 266 // Grab current value, if any, from bits. 267 uint64_t CurVal = 0; 268 269 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); 270 271 for (unsigned i = 0; i != NumBytes; ++i) { 272 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 273 : i) 274 : (FullSize - 1 - i); 275 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 276 } 277 278 uint64_t Mask = ((uint64_t)(-1) >> 279 (64 - getFixupKindInfo(Kind).TargetSize)); 280 CurVal |= Value & Mask; 281 282 // Write out the fixed up bytes back to the code/data bits. 283 for (unsigned i = 0; i != NumBytes; ++i) { 284 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 285 : i) 286 : (FullSize - 1 - i); 287 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 288 } 289 } 290 291 Optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const { 292 return StringSwitch<Optional<MCFixupKind>>(Name) 293 .Case("R_MIPS_NONE", (MCFixupKind)Mips::fixup_Mips_NONE) 294 .Case("R_MIPS_32", FK_Data_4) 295 .Default(MCAsmBackend::getFixupKind(Name)); 296 } 297 298 const MCFixupKindInfo &MipsAsmBackend:: 299 getFixupKindInfo(MCFixupKind Kind) const { 300 const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = { 301 // This table *must* be in same the order of fixup_* kinds in 302 // MipsFixupKinds.h. 303 // 304 // name offset bits flags 305 { "fixup_Mips_NONE", 0, 0, 0 }, 306 { "fixup_Mips_16", 0, 16, 0 }, 307 { "fixup_Mips_32", 0, 32, 0 }, 308 { "fixup_Mips_REL32", 0, 32, 0 }, 309 { "fixup_Mips_26", 0, 26, 0 }, 310 { "fixup_Mips_HI16", 0, 16, 0 }, 311 { "fixup_Mips_LO16", 0, 16, 0 }, 312 { "fixup_Mips_GPREL16", 0, 16, 0 }, 313 { "fixup_Mips_LITERAL", 0, 16, 0 }, 314 { "fixup_Mips_GOT", 0, 16, 0 }, 315 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 316 { "fixup_Mips_CALL16", 0, 16, 0 }, 317 { "fixup_Mips_GPREL32", 0, 32, 0 }, 318 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 319 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 320 { "fixup_Mips_64", 0, 64, 0 }, 321 { "fixup_Mips_TLSGD", 0, 16, 0 }, 322 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 323 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 324 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 325 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 326 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 327 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 328 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 329 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 330 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 331 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 332 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 333 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 334 { "fixup_Mips_HIGHER", 0, 16, 0 }, 335 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 336 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 337 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 338 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 339 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 340 { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 341 { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 342 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 343 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 344 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 345 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 346 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 347 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 348 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 349 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 350 { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, 351 { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 352 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 353 { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 354 { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 355 { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 356 { "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 357 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 358 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 359 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 360 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 361 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, 362 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, 363 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 364 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 365 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 366 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }, 367 { "fixup_Mips_SUB", 0, 64, 0 }, 368 { "fixup_MICROMIPS_SUB", 0, 64, 0 } 369 }; 370 371 const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = { 372 // This table *must* be in same the order of fixup_* kinds in 373 // MipsFixupKinds.h. 374 // 375 // name offset bits flags 376 { "fixup_Mips_NONE", 0, 0, 0 }, 377 { "fixup_Mips_16", 16, 16, 0 }, 378 { "fixup_Mips_32", 0, 32, 0 }, 379 { "fixup_Mips_REL32", 0, 32, 0 }, 380 { "fixup_Mips_26", 6, 26, 0 }, 381 { "fixup_Mips_HI16", 16, 16, 0 }, 382 { "fixup_Mips_LO16", 16, 16, 0 }, 383 { "fixup_Mips_GPREL16", 16, 16, 0 }, 384 { "fixup_Mips_LITERAL", 16, 16, 0 }, 385 { "fixup_Mips_GOT", 16, 16, 0 }, 386 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 387 { "fixup_Mips_CALL16", 16, 16, 0 }, 388 { "fixup_Mips_GPREL32", 0, 32, 0 }, 389 { "fixup_Mips_SHIFT5", 21, 5, 0 }, 390 { "fixup_Mips_SHIFT6", 21, 5, 0 }, 391 { "fixup_Mips_64", 0, 64, 0 }, 392 { "fixup_Mips_TLSGD", 16, 16, 0 }, 393 { "fixup_Mips_GOTTPREL", 16, 16, 0 }, 394 { "fixup_Mips_TPREL_HI", 16, 16, 0 }, 395 { "fixup_Mips_TPREL_LO", 16, 16, 0 }, 396 { "fixup_Mips_TLSLDM", 16, 16, 0 }, 397 { "fixup_Mips_DTPREL_HI", 16, 16, 0 }, 398 { "fixup_Mips_DTPREL_LO", 16, 16, 0 }, 399 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 400 { "fixup_Mips_GPOFF_HI", 16, 16, 0 }, 401 { "fixup_Mips_GPOFF_LO", 16, 16, 0 }, 402 { "fixup_Mips_GOT_PAGE", 16, 16, 0 }, 403 { "fixup_Mips_GOT_OFST", 16, 16, 0 }, 404 { "fixup_Mips_GOT_DISP", 16, 16, 0 }, 405 { "fixup_Mips_HIGHER", 16, 16, 0 }, 406 { "fixup_Mips_HIGHEST", 16, 16, 0 }, 407 { "fixup_Mips_GOT_HI16", 16, 16, 0 }, 408 { "fixup_Mips_GOT_LO16", 16, 16, 0 }, 409 { "fixup_Mips_CALL_HI16", 16, 16, 0 }, 410 { "fixup_Mips_CALL_LO16", 16, 16, 0 }, 411 { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel }, 412 { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 413 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, 414 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 415 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 416 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 417 { "fixup_MICROMIPS_26_S1", 6, 26, 0 }, 418 { "fixup_MICROMIPS_HI16", 16, 16, 0 }, 419 { "fixup_MICROMIPS_LO16", 16, 16, 0 }, 420 { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, 421 { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, 422 { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, 423 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 424 { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 425 { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel }, 426 { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel }, 427 { "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel }, 428 { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, 429 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, 430 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, 431 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 }, 432 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 }, 433 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 }, 434 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, 435 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, 436 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, 437 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }, 438 { "fixup_Mips_SUB", 0, 64, 0 }, 439 { "fixup_MICROMIPS_SUB", 0, 64, 0 } 440 }; 441 442 if (Kind < FirstTargetFixupKind) 443 return MCAsmBackend::getFixupKindInfo(Kind); 444 445 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 446 "Invalid kind!"); 447 448 if (IsLittle) 449 return LittleEndianInfos[Kind - FirstTargetFixupKind]; 450 return BigEndianInfos[Kind - FirstTargetFixupKind]; 451 } 452 453 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 454 /// to the given output. If the target cannot generate such a sequence, 455 /// it should return an error. 456 /// 457 /// \return - True on success. 458 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 459 // Check for a less than instruction size number of bytes 460 // FIXME: 16 bit instructions are not handled yet here. 461 // We shouldn't be using a hard coded number for instruction size. 462 463 // If the count is not 4-byte aligned, we must be writing data into the text 464 // section (otherwise we have unaligned instructions, and thus have far 465 // bigger problems), so just write zeros instead. 466 OW->WriteZeros(Count); 467 return true; 468 } 469 470 /// processFixupValue - Target hook to process the literal value of a fixup 471 /// if necessary. 472 void MipsAsmBackend::processFixupValue(const MCAssembler &Asm, 473 const MCAsmLayout &Layout, 474 const MCFixup &Fixup, 475 const MCFragment *DF, 476 const MCValue &Target, 477 uint64_t &Value, 478 bool &IsResolved) { 479 // At this point we'll ignore the value returned by adjustFixupValue as 480 // we are only checking if the fixup can be applied correctly. We have 481 // access to MCContext from here which allows us to report a fatal error 482 // with *possibly* a source code location. 483 // The caller will also ignore any changes we make to Value 484 // (recordRelocation() overwrites it with it's own calculation). 485 (void)adjustFixupValue(Fixup, Value, &Asm.getContext()); 486 } 487 488 // MCAsmBackend 489 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 490 const MCRegisterInfo &MRI, 491 const Triple &TT, StringRef CPU, 492 const MCTargetOptions &Options) { 493 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, 494 /*Is64Bit*/ false); 495 } 496 497 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 498 const MCRegisterInfo &MRI, 499 const Triple &TT, StringRef CPU, 500 const MCTargetOptions &Options) { 501 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, 502 /*Is64Bit*/ false); 503 } 504 505 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 506 const MCRegisterInfo &MRI, 507 const Triple &TT, StringRef CPU, 508 const MCTargetOptions &Options) { 509 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); 510 } 511 512 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 513 const MCRegisterInfo &MRI, 514 const Triple &TT, StringRef CPU, 515 const MCTargetOptions &Options) { 516 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, 517 /*Is64Bit*/ true); 518 } 519