1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MCTargetDesc/MipsFixupKinds.h" 16 #include "MCTargetDesc/MipsAsmBackend.h" 17 #include "MCTargetDesc/MipsMCTargetDesc.h" 18 #include "llvm/MC/MCAsmBackend.h" 19 #include "llvm/MC/MCAssembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCDirectives.h" 22 #include "llvm/MC/MCELFObjectWriter.h" 23 #include "llvm/MC/MCFixupKindInfo.h" 24 #include "llvm/MC/MCObjectWriter.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/raw_ostream.h" 29 30 using namespace llvm; 31 32 // Prepare value for the target space for it 33 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 34 MCContext *Ctx = nullptr) { 35 36 unsigned Kind = Fixup.getKind(); 37 38 // Add/subtract and shift 39 switch (Kind) { 40 default: 41 return 0; 42 case FK_Data_2: 43 case FK_GPRel_4: 44 case FK_Data_4: 45 case FK_Data_8: 46 case Mips::fixup_Mips_LO16: 47 case Mips::fixup_Mips_GPREL16: 48 case Mips::fixup_Mips_GPOFF_HI: 49 case Mips::fixup_Mips_GPOFF_LO: 50 case Mips::fixup_Mips_GOT_PAGE: 51 case Mips::fixup_Mips_GOT_OFST: 52 case Mips::fixup_Mips_GOT_DISP: 53 case Mips::fixup_Mips_GOT_LO16: 54 case Mips::fixup_Mips_CALL_LO16: 55 case Mips::fixup_MICROMIPS_LO16: 56 case Mips::fixup_MICROMIPS_GOT_PAGE: 57 case Mips::fixup_MICROMIPS_GOT_OFST: 58 case Mips::fixup_MICROMIPS_GOT_DISP: 59 case Mips::fixup_MIPS_PCLO16: 60 break; 61 case Mips::fixup_Mips_PC16: 62 // The displacement is then divided by 4 to give us an 18 bit 63 // address range. Forcing a signed division because Value can be negative. 64 Value = (int64_t)Value / 4; 65 // We now check if Value can be encoded as a 16-bit signed immediate. 66 if (!isInt<16>(Value) && Ctx) { 67 Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup"); 68 return 0; 69 } 70 break; 71 case Mips::fixup_MIPS_PC19_S2: 72 case Mips::fixup_MICROMIPS_PC19_S2: 73 // Forcing a signed division because Value can be negative. 74 Value = (int64_t)Value / 4; 75 // We now check if Value can be encoded as a 19-bit signed immediate. 76 if (!isInt<19>(Value) && Ctx) { 77 Ctx->reportError(Fixup.getLoc(), "out of range PC19 fixup"); 78 return 0; 79 } 80 break; 81 case Mips::fixup_Mips_26: 82 // So far we are only using this type for jumps. 83 // The displacement is then divided by 4 to give us an 28 bit 84 // address range. 85 Value >>= 2; 86 break; 87 case Mips::fixup_Mips_HI16: 88 case Mips::fixup_Mips_GOT_Local: 89 case Mips::fixup_Mips_GOT_HI16: 90 case Mips::fixup_Mips_CALL_HI16: 91 case Mips::fixup_MICROMIPS_HI16: 92 case Mips::fixup_MIPS_PCHI16: 93 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 94 Value = ((Value + 0x8000) >> 16) & 0xffff; 95 break; 96 case Mips::fixup_Mips_HIGHER: 97 // Get the 3rd 16-bits. 98 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 99 break; 100 case Mips::fixup_Mips_HIGHEST: 101 // Get the 4th 16-bits. 102 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 103 break; 104 case Mips::fixup_MICROMIPS_26_S1: 105 Value >>= 1; 106 break; 107 case Mips::fixup_MICROMIPS_PC7_S1: 108 Value -= 4; 109 // Forcing a signed division because Value can be negative. 110 Value = (int64_t) Value / 2; 111 // We now check if Value can be encoded as a 7-bit signed immediate. 112 if (!isInt<7>(Value) && Ctx) { 113 Ctx->reportError(Fixup.getLoc(), "out of range PC7 fixup"); 114 return 0; 115 } 116 break; 117 case Mips::fixup_MICROMIPS_PC10_S1: 118 Value -= 2; 119 // Forcing a signed division because Value can be negative. 120 Value = (int64_t) Value / 2; 121 // We now check if Value can be encoded as a 10-bit signed immediate. 122 if (!isInt<10>(Value) && Ctx) { 123 Ctx->reportError(Fixup.getLoc(), "out of range PC10 fixup"); 124 return 0; 125 } 126 break; 127 case Mips::fixup_MICROMIPS_PC16_S1: 128 Value -= 4; 129 // Forcing a signed division because Value can be negative. 130 Value = (int64_t)Value / 2; 131 // We now check if Value can be encoded as a 16-bit signed immediate. 132 if (!isInt<16>(Value) && Ctx) { 133 Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup"); 134 return 0; 135 } 136 break; 137 case Mips::fixup_MIPS_PC18_S3: 138 // Forcing a signed division because Value can be negative. 139 Value = (int64_t)Value / 8; 140 // We now check if Value can be encoded as a 18-bit signed immediate. 141 if (!isInt<18>(Value) && Ctx) { 142 Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup"); 143 return 0; 144 } 145 break; 146 case Mips::fixup_MICROMIPS_PC18_S3: 147 // Check alignment. 148 if ((Value & 7) && Ctx) { 149 Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup"); 150 } 151 // Forcing a signed division because Value can be negative. 152 Value = (int64_t)Value / 8; 153 // We now check if Value can be encoded as a 18-bit signed immediate. 154 if (!isInt<18>(Value) && Ctx) { 155 Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup"); 156 return 0; 157 } 158 break; 159 case Mips::fixup_MIPS_PC21_S2: 160 // Forcing a signed division because Value can be negative. 161 Value = (int64_t) Value / 4; 162 // We now check if Value can be encoded as a 21-bit signed immediate. 163 if (!isInt<21>(Value) && Ctx) { 164 Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup"); 165 return 0; 166 } 167 break; 168 case Mips::fixup_MIPS_PC26_S2: 169 // Forcing a signed division because Value can be negative. 170 Value = (int64_t) Value / 4; 171 // We now check if Value can be encoded as a 26-bit signed immediate. 172 if (!isInt<26>(Value) && Ctx) { 173 Ctx->reportError(Fixup.getLoc(), "out of range PC26 fixup"); 174 return 0; 175 } 176 break; 177 case Mips::fixup_MICROMIPS_PC26_S1: 178 // Forcing a signed division because Value can be negative. 179 Value = (int64_t)Value / 2; 180 // We now check if Value can be encoded as a 26-bit signed immediate. 181 if (!isInt<26>(Value) && Ctx) { 182 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC26 fixup"); 183 return 0; 184 } 185 break; 186 187 } 188 189 return Value; 190 } 191 192 MCObjectWriter * 193 MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { 194 return createMipsELFObjectWriter(OS, 195 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 196 } 197 198 // Little-endian fixup data byte ordering: 199 // mips32r2: a | b | x | x 200 // microMIPS: x | x | a | b 201 202 static bool needsMMLEByteOrder(unsigned Kind) { 203 return Kind != Mips::fixup_MICROMIPS_PC10_S1 && 204 Kind >= Mips::fixup_MICROMIPS_26_S1 && 205 Kind < Mips::LastTargetFixupKind; 206 } 207 208 // Calculate index for microMIPS specific little endian byte order 209 static unsigned calculateMMLEIndex(unsigned i) { 210 assert(i <= 3 && "Index out of range!"); 211 212 return (1 - i / 2) * 2 + i % 2; 213 } 214 215 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 216 /// data fragment, at the offset specified by the fixup and following the 217 /// fixup kind as appropriate. 218 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 219 unsigned DataSize, uint64_t Value, 220 bool IsPCRel) const { 221 MCFixupKind Kind = Fixup.getKind(); 222 Value = adjustFixupValue(Fixup, Value); 223 224 if (!Value) 225 return; // Doesn't change encoding. 226 227 // Where do we start in the object 228 unsigned Offset = Fixup.getOffset(); 229 // Number of bytes we need to fixup 230 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 231 // Used to point to big endian bytes 232 unsigned FullSize; 233 234 switch ((unsigned)Kind) { 235 case FK_Data_2: 236 case Mips::fixup_Mips_16: 237 case Mips::fixup_MICROMIPS_PC10_S1: 238 FullSize = 2; 239 break; 240 case FK_Data_8: 241 case Mips::fixup_Mips_64: 242 FullSize = 8; 243 break; 244 case FK_Data_4: 245 default: 246 FullSize = 4; 247 break; 248 } 249 250 // Grab current value, if any, from bits. 251 uint64_t CurVal = 0; 252 253 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); 254 255 for (unsigned i = 0; i != NumBytes; ++i) { 256 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 257 : i) 258 : (FullSize - 1 - i); 259 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 260 } 261 262 uint64_t Mask = ((uint64_t)(-1) >> 263 (64 - getFixupKindInfo(Kind).TargetSize)); 264 CurVal |= Value & Mask; 265 266 // Write out the fixed up bytes back to the code/data bits. 267 for (unsigned i = 0; i != NumBytes; ++i) { 268 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 269 : i) 270 : (FullSize - 1 - i); 271 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 272 } 273 } 274 275 Optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const { 276 return StringSwitch<Optional<MCFixupKind>>(Name) 277 .Case("R_MIPS_NONE", (MCFixupKind)Mips::fixup_Mips_NONE) 278 .Case("R_MIPS_32", FK_Data_4) 279 .Default(MCAsmBackend::getFixupKind(Name)); 280 } 281 282 const MCFixupKindInfo &MipsAsmBackend:: 283 getFixupKindInfo(MCFixupKind Kind) const { 284 const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = { 285 // This table *must* be in same the order of fixup_* kinds in 286 // MipsFixupKinds.h. 287 // 288 // name offset bits flags 289 { "fixup_Mips_NONE", 0, 0, 0 }, 290 { "fixup_Mips_16", 0, 16, 0 }, 291 { "fixup_Mips_32", 0, 32, 0 }, 292 { "fixup_Mips_REL32", 0, 32, 0 }, 293 { "fixup_Mips_26", 0, 26, 0 }, 294 { "fixup_Mips_HI16", 0, 16, 0 }, 295 { "fixup_Mips_LO16", 0, 16, 0 }, 296 { "fixup_Mips_GPREL16", 0, 16, 0 }, 297 { "fixup_Mips_LITERAL", 0, 16, 0 }, 298 { "fixup_Mips_GOT_Global", 0, 16, 0 }, 299 { "fixup_Mips_GOT_Local", 0, 16, 0 }, 300 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 301 { "fixup_Mips_CALL16", 0, 16, 0 }, 302 { "fixup_Mips_GPREL32", 0, 32, 0 }, 303 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 304 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 305 { "fixup_Mips_64", 0, 64, 0 }, 306 { "fixup_Mips_TLSGD", 0, 16, 0 }, 307 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 308 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 309 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 310 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 311 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 312 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 313 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 314 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 315 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 316 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 317 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 318 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 319 { "fixup_Mips_HIGHER", 0, 16, 0 }, 320 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 321 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 322 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 323 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 324 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 325 { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 326 { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 327 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 328 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 329 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 330 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 331 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 332 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 333 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 334 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 335 { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, 336 { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 337 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 338 { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 339 { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 340 { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 341 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 342 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 343 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 344 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 345 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, 346 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, 347 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 348 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 349 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 350 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } 351 }; 352 353 const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = { 354 // This table *must* be in same the order of fixup_* kinds in 355 // MipsFixupKinds.h. 356 // 357 // name offset bits flags 358 { "fixup_Mips_NONE", 0, 0, 0 }, 359 { "fixup_Mips_16", 16, 16, 0 }, 360 { "fixup_Mips_32", 0, 32, 0 }, 361 { "fixup_Mips_REL32", 0, 32, 0 }, 362 { "fixup_Mips_26", 6, 26, 0 }, 363 { "fixup_Mips_HI16", 16, 16, 0 }, 364 { "fixup_Mips_LO16", 16, 16, 0 }, 365 { "fixup_Mips_GPREL16", 16, 16, 0 }, 366 { "fixup_Mips_LITERAL", 16, 16, 0 }, 367 { "fixup_Mips_GOT_Global", 16, 16, 0 }, 368 { "fixup_Mips_GOT_Local", 16, 16, 0 }, 369 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 370 { "fixup_Mips_CALL16", 16, 16, 0 }, 371 { "fixup_Mips_GPREL32", 0, 32, 0 }, 372 { "fixup_Mips_SHIFT5", 21, 5, 0 }, 373 { "fixup_Mips_SHIFT6", 21, 5, 0 }, 374 { "fixup_Mips_64", 0, 64, 0 }, 375 { "fixup_Mips_TLSGD", 16, 16, 0 }, 376 { "fixup_Mips_GOTTPREL", 16, 16, 0 }, 377 { "fixup_Mips_TPREL_HI", 16, 16, 0 }, 378 { "fixup_Mips_TPREL_LO", 16, 16, 0 }, 379 { "fixup_Mips_TLSLDM", 16, 16, 0 }, 380 { "fixup_Mips_DTPREL_HI", 16, 16, 0 }, 381 { "fixup_Mips_DTPREL_LO", 16, 16, 0 }, 382 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 383 { "fixup_Mips_GPOFF_HI", 16, 16, 0 }, 384 { "fixup_Mips_GPOFF_LO", 16, 16, 0 }, 385 { "fixup_Mips_GOT_PAGE", 16, 16, 0 }, 386 { "fixup_Mips_GOT_OFST", 16, 16, 0 }, 387 { "fixup_Mips_GOT_DISP", 16, 16, 0 }, 388 { "fixup_Mips_HIGHER", 16, 16, 0 }, 389 { "fixup_Mips_HIGHEST", 16, 16, 0 }, 390 { "fixup_Mips_GOT_HI16", 16, 16, 0 }, 391 { "fixup_Mips_GOT_LO16", 16, 16, 0 }, 392 { "fixup_Mips_CALL_HI16", 16, 16, 0 }, 393 { "fixup_Mips_CALL_LO16", 16, 16, 0 }, 394 { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel }, 395 { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 396 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, 397 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 398 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 399 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 400 { "fixup_MICROMIPS_26_S1", 6, 26, 0 }, 401 { "fixup_MICROMIPS_HI16", 16, 16, 0 }, 402 { "fixup_MICROMIPS_LO16", 16, 16, 0 }, 403 { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, 404 { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, 405 { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, 406 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 407 { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 408 { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel }, 409 { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel }, 410 { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, 411 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, 412 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, 413 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 }, 414 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 }, 415 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 }, 416 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, 417 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, 418 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, 419 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 } 420 }; 421 422 if (Kind < FirstTargetFixupKind) 423 return MCAsmBackend::getFixupKindInfo(Kind); 424 425 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 426 "Invalid kind!"); 427 428 if (IsLittle) 429 return LittleEndianInfos[Kind - FirstTargetFixupKind]; 430 return BigEndianInfos[Kind - FirstTargetFixupKind]; 431 } 432 433 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 434 /// to the given output. If the target cannot generate such a sequence, 435 /// it should return an error. 436 /// 437 /// \return - True on success. 438 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 439 // Check for a less than instruction size number of bytes 440 // FIXME: 16 bit instructions are not handled yet here. 441 // We shouldn't be using a hard coded number for instruction size. 442 443 // If the count is not 4-byte aligned, we must be writing data into the text 444 // section (otherwise we have unaligned instructions, and thus have far 445 // bigger problems), so just write zeros instead. 446 OW->WriteZeros(Count); 447 return true; 448 } 449 450 /// processFixupValue - Target hook to process the literal value of a fixup 451 /// if necessary. 452 void MipsAsmBackend::processFixupValue(const MCAssembler &Asm, 453 const MCAsmLayout &Layout, 454 const MCFixup &Fixup, 455 const MCFragment *DF, 456 const MCValue &Target, 457 uint64_t &Value, 458 bool &IsResolved) { 459 // At this point we'll ignore the value returned by adjustFixupValue as 460 // we are only checking if the fixup can be applied correctly. We have 461 // access to MCContext from here which allows us to report a fatal error 462 // with *possibly* a source code location. 463 (void)adjustFixupValue(Fixup, Value, &Asm.getContext()); 464 } 465 466 // MCAsmBackend 467 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 468 const MCRegisterInfo &MRI, 469 const Triple &TT, StringRef CPU) { 470 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, 471 /*Is64Bit*/ false); 472 } 473 474 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 475 const MCRegisterInfo &MRI, 476 const Triple &TT, StringRef CPU) { 477 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, 478 /*Is64Bit*/ false); 479 } 480 481 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 482 const MCRegisterInfo &MRI, 483 const Triple &TT, StringRef CPU) { 484 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); 485 } 486 487 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 488 const MCRegisterInfo &MRI, 489 const Triple &TT, StringRef CPU) { 490 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, 491 /*Is64Bit*/ true); 492 } 493