1 //===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MipsFixupKinds.h" 16 #include "MCTargetDesc/MipsMCTargetDesc.h" 17 #include "llvm/MC/MCAsmBackend.h" 18 #include "llvm/MC/MCAssembler.h" 19 #include "llvm/MC/MCDirectives.h" 20 #include "llvm/MC/MCELFObjectWriter.h" 21 #include "llvm/MC/MCFixupKindInfo.h" 22 #include "llvm/MC/MCObjectWriter.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 using namespace llvm; 28 29 // Prepare value for the target space for it 30 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 31 32 // Add/subtract and shift 33 switch (Kind) { 34 default: 35 return 0; 36 case FK_GPRel_4: 37 case FK_Data_4: 38 case FK_Data_8: 39 case Mips::fixup_Mips_LO16: 40 case Mips::fixup_Mips_GPREL16: 41 case Mips::fixup_Mips_GPOFF_HI: 42 case Mips::fixup_Mips_GPOFF_LO: 43 case Mips::fixup_Mips_GOT_PAGE: 44 case Mips::fixup_Mips_GOT_OFST: 45 case Mips::fixup_Mips_GOT_DISP: 46 case Mips::fixup_Mips_GOT_LO16: 47 case Mips::fixup_Mips_CALL_LO16: 48 case Mips::fixup_MICROMIPS_LO16: 49 case Mips::fixup_MICROMIPS_GOT_PAGE: 50 case Mips::fixup_MICROMIPS_GOT_OFST: 51 case Mips::fixup_MICROMIPS_GOT_DISP: 52 break; 53 case Mips::fixup_Mips_PC16: 54 // So far we are only using this type for branches. 55 // For branches we start 1 instruction after the branch 56 // so the displacement will be one instruction size less. 57 Value -= 4; 58 // The displacement is then divided by 4 to give us an 18 bit 59 // address range. 60 Value >>= 2; 61 break; 62 case Mips::fixup_Mips_26: 63 // So far we are only using this type for jumps. 64 // The displacement is then divided by 4 to give us an 28 bit 65 // address range. 66 Value >>= 2; 67 break; 68 case Mips::fixup_Mips_HI16: 69 case Mips::fixup_Mips_GOT_Local: 70 case Mips::fixup_Mips_GOT_HI16: 71 case Mips::fixup_Mips_CALL_HI16: 72 case Mips::fixup_MICROMIPS_HI16: 73 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 74 Value = ((Value + 0x8000) >> 16) & 0xffff; 75 break; 76 case Mips::fixup_Mips_HIGHER: 77 // Get the 3rd 16-bits. 78 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 79 break; 80 case Mips::fixup_Mips_HIGHEST: 81 // Get the 4th 16-bits. 82 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 83 break; 84 } 85 86 return Value; 87 } 88 89 namespace { 90 class MipsAsmBackend : public MCAsmBackend { 91 Triple::OSType OSType; 92 bool IsLittle; // Big or little endian 93 bool Is64Bit; // 32 or 64 bit words 94 95 public: 96 MipsAsmBackend(const Target &T, Triple::OSType _OSType, 97 bool _isLittle, bool _is64Bit) 98 :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {} 99 100 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 101 return createMipsELFObjectWriter(OS, 102 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 103 } 104 105 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 106 /// data fragment, at the offset specified by the fixup and following the 107 /// fixup kind as appropriate. 108 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 109 uint64_t Value) const { 110 MCFixupKind Kind = Fixup.getKind(); 111 Value = adjustFixupValue((unsigned)Kind, Value); 112 113 if (!Value) 114 return; // Doesn't change encoding. 115 116 // Where do we start in the object 117 unsigned Offset = Fixup.getOffset(); 118 // Number of bytes we need to fixup 119 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 120 // Used to point to big endian bytes 121 unsigned FullSize; 122 123 switch ((unsigned)Kind) { 124 case Mips::fixup_Mips_16: 125 FullSize = 2; 126 break; 127 case Mips::fixup_Mips_64: 128 FullSize = 8; 129 break; 130 default: 131 FullSize = 4; 132 break; 133 } 134 135 // Grab current value, if any, from bits. 136 uint64_t CurVal = 0; 137 138 for (unsigned i = 0; i != NumBytes; ++i) { 139 unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 140 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 141 } 142 143 uint64_t Mask = ((uint64_t)(-1) >> 144 (64 - getFixupKindInfo(Kind).TargetSize)); 145 CurVal |= Value & Mask; 146 147 // Write out the fixed up bytes back to the code/data bits. 148 for (unsigned i = 0; i != NumBytes; ++i) { 149 unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 150 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 151 } 152 } 153 154 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } 155 156 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 157 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { 158 // This table *must* be in same the order of fixup_* kinds in 159 // MipsFixupKinds.h. 160 // 161 // name offset bits flags 162 { "fixup_Mips_16", 0, 16, 0 }, 163 { "fixup_Mips_32", 0, 32, 0 }, 164 { "fixup_Mips_REL32", 0, 32, 0 }, 165 { "fixup_Mips_26", 0, 26, 0 }, 166 { "fixup_Mips_HI16", 0, 16, 0 }, 167 { "fixup_Mips_LO16", 0, 16, 0 }, 168 { "fixup_Mips_GPREL16", 0, 16, 0 }, 169 { "fixup_Mips_LITERAL", 0, 16, 0 }, 170 { "fixup_Mips_GOT_Global", 0, 16, 0 }, 171 { "fixup_Mips_GOT_Local", 0, 16, 0 }, 172 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 173 { "fixup_Mips_CALL16", 0, 16, 0 }, 174 { "fixup_Mips_GPREL32", 0, 32, 0 }, 175 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 176 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 177 { "fixup_Mips_64", 0, 64, 0 }, 178 { "fixup_Mips_TLSGD", 0, 16, 0 }, 179 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 180 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 181 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 182 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 183 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 184 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 185 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 186 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 187 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 188 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 189 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 190 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 191 { "fixup_Mips_HIGHER", 0, 16, 0 }, 192 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 193 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 194 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 195 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 196 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 197 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 198 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 199 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 200 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 201 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 202 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 203 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 204 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 205 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 206 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 207 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } 208 }; 209 210 if (Kind < FirstTargetFixupKind) 211 return MCAsmBackend::getFixupKindInfo(Kind); 212 213 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 214 "Invalid kind!"); 215 return Infos[Kind - FirstTargetFixupKind]; 216 } 217 218 /// @name Target Relaxation Interfaces 219 /// @{ 220 221 /// MayNeedRelaxation - Check whether the given instruction may need 222 /// relaxation. 223 /// 224 /// \param Inst - The instruction to test. 225 bool mayNeedRelaxation(const MCInst &Inst) const { 226 return false; 227 } 228 229 /// fixupNeedsRelaxation - Target specific predicate for whether a given 230 /// fixup requires the associated instruction to be relaxed. 231 bool fixupNeedsRelaxation(const MCFixup &Fixup, 232 uint64_t Value, 233 const MCRelaxableFragment *DF, 234 const MCAsmLayout &Layout) const { 235 // FIXME. 236 assert(0 && "RelaxInstruction() unimplemented"); 237 return false; 238 } 239 240 /// RelaxInstruction - Relax the instruction in the given fragment 241 /// to the next wider instruction. 242 /// 243 /// \param Inst - The instruction to relax, which may be the same 244 /// as the output. 245 /// \param [out] Res On return, the relaxed instruction. 246 void relaxInstruction(const MCInst &Inst, MCInst &Res) const { 247 } 248 249 /// @} 250 251 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 252 /// to the given output. If the target cannot generate such a sequence, 253 /// it should return an error. 254 /// 255 /// \return - True on success. 256 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 257 // Check for a less than instruction size number of bytes 258 // FIXME: 16 bit instructions are not handled yet here. 259 // We shouldn't be using a hard coded number for instruction size. 260 if (Count % 4) return false; 261 262 uint64_t NumNops = Count / 4; 263 for (uint64_t i = 0; i != NumNops; ++i) 264 OW->Write32(0); 265 return true; 266 } 267 }; // class MipsAsmBackend 268 269 } // namespace 270 271 // MCAsmBackend 272 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 273 const MCRegisterInfo &MRI, 274 StringRef TT, 275 StringRef CPU) { 276 return new MipsAsmBackend(T, Triple(TT).getOS(), 277 /*IsLittle*/true, /*Is64Bit*/false); 278 } 279 280 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 281 const MCRegisterInfo &MRI, 282 StringRef TT, 283 StringRef CPU) { 284 return new MipsAsmBackend(T, Triple(TT).getOS(), 285 /*IsLittle*/false, /*Is64Bit*/false); 286 } 287 288 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 289 const MCRegisterInfo &MRI, 290 StringRef TT, 291 StringRef CPU) { 292 return new MipsAsmBackend(T, Triple(TT).getOS(), 293 /*IsLittle*/true, /*Is64Bit*/true); 294 } 295 296 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 297 const MCRegisterInfo &MRI, 298 StringRef TT, 299 StringRef CPU) { 300 return new MipsAsmBackend(T, Triple(TT).getOS(), 301 /*IsLittle*/false, /*Is64Bit*/true); 302 } 303 304