1 //===-- MipsASMBackend.cpp - ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MipsFixupKinds.h" 16 #include "MCTargetDesc/MipsMCTargetDesc.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/MC/MCAsmBackend.h" 19 #include "llvm/MC/MCAssembler.h" 20 #include "llvm/MC/MCDirectives.h" 21 #include "llvm/MC/MCELFObjectWriter.h" 22 #include "llvm/MC/MCExpr.h" 23 #include "llvm/MC/MCMachObjectWriter.h" 24 #include "llvm/MC/MCObjectWriter.h" 25 #include "llvm/MC/MCSectionELF.h" 26 #include "llvm/MC/MCSectionMachO.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/Object/MachOFormat.h" 29 #include "llvm/Support/ELF.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/raw_ostream.h" 32 33 using namespace llvm; 34 35 // Prepare value for the target space for it 36 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 37 38 // Add/subtract and shift 39 switch (Kind) { 40 default: 41 return 0; 42 case FK_GPRel_4: 43 case FK_Data_4: 44 case Mips::fixup_Mips_LO16: 45 break; 46 case Mips::fixup_Mips_PC16: 47 // So far we are only using this type for branches. 48 // For branches we start 1 instruction after the branch 49 // so the displacement will be one instruction size less. 50 Value -= 4; 51 // The displacement is then divided by 4 to give us an 18 bit 52 // address range. 53 Value >>= 2; 54 break; 55 case Mips::fixup_Mips_26: 56 // So far we are only using this type for jumps. 57 // The displacement is then divided by 4 to give us an 28 bit 58 // address range. 59 Value >>= 2; 60 break; 61 case Mips::fixup_Mips_HI16: 62 case Mips::fixup_Mips_GOT_Local: 63 // Get the higher 16-bits. Also add 1 if bit 15 is 1. 64 Value = (Value >> 16) + ((Value & 0x8000) != 0); 65 break; 66 } 67 68 return Value; 69 } 70 71 namespace { 72 73 class MipsELFObjectWriter : public MCELFObjectTargetWriter { 74 public: 75 MipsELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine, 76 bool HasRelocationAddend) 77 : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, 78 HasRelocationAddend) {} 79 }; 80 81 class MipsAsmBackend : public MCAsmBackend { 82 public: 83 MipsAsmBackend(const Target &T) : MCAsmBackend() {} 84 85 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided 86 /// data fragment, at the offset specified by the fixup and following the 87 /// fixup kind as appropriate. 88 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 89 uint64_t Value) const { 90 MCFixupKind Kind = Fixup.getKind(); 91 Value = adjustFixupValue((unsigned)Kind, Value); 92 93 if (!Value) 94 return; // Doesn't change encoding. 95 96 unsigned Offset = Fixup.getOffset(); 97 // FIXME: The below code will not work across endian models 98 // How many bytes/bits are we fixing up? 99 unsigned NumBytes = ((getFixupKindInfo(Kind).TargetSize-1)/8)+1; 100 uint64_t Mask = ((uint64_t)1 << getFixupKindInfo(Kind).TargetSize) - 1; 101 102 // Grab current value, if any, from bits. 103 uint64_t CurVal = 0; 104 for (unsigned i = 0; i != NumBytes; ++i) 105 CurVal |= ((uint8_t)Data[Offset + i]) << (i * 8); 106 107 CurVal = (CurVal & ~Mask) | ((CurVal + Value) & Mask); 108 109 // Write out the bytes back to the code/data bits. 110 // First the unaffected bits and then the fixup. 111 for (unsigned i = 0; i != NumBytes; ++i) { 112 Data[Offset + i] = uint8_t((CurVal >> (i * 8)) & 0xff); 113 } 114 } 115 116 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } 117 118 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 119 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { 120 // This table *must* be in same the order of fixup_* kinds in 121 // MipsFixupKinds.h. 122 // 123 // name offset bits flags 124 { "fixup_Mips_16", 0, 16, 0 }, 125 { "fixup_Mips_32", 0, 32, 0 }, 126 { "fixup_Mips_REL32", 0, 32, 0 }, 127 { "fixup_Mips_26", 0, 26, 0 }, 128 { "fixup_Mips_HI16", 0, 16, 0 }, 129 { "fixup_Mips_LO16", 0, 16, 0 }, 130 { "fixup_Mips_GPREL16", 0, 16, 0 }, 131 { "fixup_Mips_LITERAL", 0, 16, 0 }, 132 { "fixup_Mips_GOT_Global", 0, 16, 0 }, 133 { "fixup_Mips_GOT_Local", 0, 16, 0 }, 134 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 135 { "fixup_Mips_CALL16", 0, 16, 0 }, 136 { "fixup_Mips_GPREL32", 0, 32, 0 }, 137 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 138 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 139 { "fixup_Mips_64", 0, 64, 0 }, 140 { "fixup_Mips_TLSGD", 0, 16, 0 }, 141 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 142 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 143 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 144 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel } 145 }; 146 147 if (Kind < FirstTargetFixupKind) 148 return MCAsmBackend::getFixupKindInfo(Kind); 149 150 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 151 "Invalid kind!"); 152 return Infos[Kind - FirstTargetFixupKind]; 153 } 154 155 /// @name Target Relaxation Interfaces 156 /// @{ 157 158 /// MayNeedRelaxation - Check whether the given instruction may need 159 /// relaxation. 160 /// 161 /// \param Inst - The instruction to test. 162 bool MayNeedRelaxation(const MCInst &Inst) const { 163 return false; 164 } 165 166 /// fixupNeedsRelaxation - Target specific predicate for whether a given 167 /// fixup requires the associated instruction to be relaxed. 168 bool fixupNeedsRelaxation(const MCFixup &Fixup, 169 uint64_t Value, 170 const MCInstFragment *DF, 171 const MCAsmLayout &Layout) const { 172 // FIXME. 173 assert(0 && "RelaxInstruction() unimplemented"); 174 return false; 175 } 176 177 /// RelaxInstruction - Relax the instruction in the given fragment 178 /// to the next wider instruction. 179 /// 180 /// \param Inst - The instruction to relax, which may be the same 181 /// as the output. 182 /// \parm Res [output] - On return, the relaxed instruction. 183 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const { 184 } 185 186 /// @} 187 188 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 189 /// to the given output. If the target cannot generate such a sequence, 190 /// it should return an error. 191 /// 192 /// \return - True on success. 193 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const { 194 return true; 195 } 196 }; 197 198 class MipsEB_AsmBackend : public MipsAsmBackend { 199 public: 200 Triple::OSType OSType; 201 202 MipsEB_AsmBackend(const Target &T, Triple::OSType _OSType) 203 : MipsAsmBackend(T), OSType(_OSType) {} 204 205 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 206 return createELFObjectWriter(createELFObjectTargetWriter(), 207 OS, /*IsLittleEndian*/ false); 208 } 209 210 MCELFObjectTargetWriter *createELFObjectTargetWriter() const { 211 return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false); 212 } 213 }; 214 215 class MipsEL_AsmBackend : public MipsAsmBackend { 216 public: 217 Triple::OSType OSType; 218 219 MipsEL_AsmBackend(const Target &T, Triple::OSType _OSType) 220 : MipsAsmBackend(T), OSType(_OSType) {} 221 222 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 223 return createELFObjectWriter(createELFObjectTargetWriter(), 224 OS, /*IsLittleEndian*/ true); 225 } 226 227 MCELFObjectTargetWriter *createELFObjectTargetWriter() const { 228 return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false); 229 } 230 }; 231 } // namespace 232 233 MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, StringRef TT) { 234 Triple TheTriple(TT); 235 236 // just return little endian for now 237 // 238 return new MipsEL_AsmBackend(T, Triple(TT).getOS()); 239 } 240