1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 49 50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 51 52 bool hasCOP3() const { 53 // Only present in MIPS-I and MIPS-II 54 return !hasMips32() && !hasMips3(); 55 } 56 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &VStream, 60 raw_ostream &CStream) const override; 61 }; 62 63 } // end anonymous namespace 64 65 // Forward declare these because the autogenerated code will reference them. 66 // Definitions are further down. 67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 68 unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 78 unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 83 unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 93 unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 98 unsigned Insn, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 132 unsigned Insn, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 142 unsigned RegNo, 143 uint64_t Address, 144 const void *Decoder); 145 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 147 unsigned RegNo, 148 uint64_t Address, 149 const void *Decoder); 150 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 152 unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 157 unsigned RegNo, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 192 unsigned Offset, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 202 unsigned Offset, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 207 unsigned Offset, 208 uint64_t Address, 209 const void *Decoder); 210 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 212 // shifted left by 1 bit. 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 214 unsigned Offset, 215 uint64_t Address, 216 const void *Decoder); 217 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 219 // shifted left by 1 bit. 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 235 unsigned Offset, 236 uint64_t Address, 237 const void *Decoder); 238 239 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 240 // shifted left by 1 bit. 241 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 242 unsigned Insn, 243 uint64_t Address, 244 const void *Decoder); 245 246 static DecodeStatus DecodeMem(MCInst &Inst, 247 unsigned Insn, 248 uint64_t Address, 249 const void *Decoder); 250 251 static DecodeStatus DecodeMemEVA(MCInst &Inst, 252 unsigned Insn, 253 uint64_t Address, 254 const void *Decoder); 255 256 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 257 unsigned Insn, 258 uint64_t Address, 259 const void *Decoder); 260 261 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 262 unsigned Insn, 263 uint64_t Address, 264 const void *Decoder); 265 266 static DecodeStatus DecodeCacheOp(MCInst &Inst, 267 unsigned Insn, 268 uint64_t Address, 269 const void *Decoder); 270 271 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 272 unsigned Insn, 273 uint64_t Address, 274 const void *Decoder); 275 276 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 277 unsigned Insn, 278 uint64_t Address, 279 const void *Decoder); 280 281 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 282 unsigned Insn, 283 uint64_t Address, 284 const void *Decoder); 285 286 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 287 unsigned Insn, 288 uint64_t Address, 289 const void *Decoder); 290 291 static DecodeStatus DecodeSyncI(MCInst &Inst, 292 unsigned Insn, 293 uint64_t Address, 294 const void *Decoder); 295 296 static DecodeStatus DecodeSynciR6(MCInst &Inst, 297 unsigned Insn, 298 uint64_t Address, 299 const void *Decoder); 300 301 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 304 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 305 unsigned Insn, 306 uint64_t Address, 307 const void *Decoder); 308 309 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 310 unsigned Insn, 311 uint64_t Address, 312 const void *Decoder); 313 314 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 315 unsigned Insn, 316 uint64_t Address, 317 const void *Decoder); 318 319 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 320 unsigned Insn, 321 uint64_t Address, 322 const void *Decoder); 323 324 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 325 unsigned Insn, 326 uint64_t Address, 327 const void *Decoder); 328 329 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 330 unsigned Insn, 331 uint64_t Address, 332 const void *Decoder); 333 334 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 335 unsigned Insn, 336 uint64_t Address, 337 const void *Decoder); 338 339 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 344 uint64_t Address, 345 const void *Decoder); 346 347 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 348 uint64_t Address, 349 const void *Decoder); 350 351 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 352 uint64_t Address, 353 const void *Decoder); 354 355 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 356 unsigned Insn, 357 uint64_t Address, 358 const void *Decoder); 359 360 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 361 unsigned Value, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 366 unsigned Value, 367 uint64_t Address, 368 const void *Decoder); 369 370 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 371 unsigned Value, 372 uint64_t Address, 373 const void *Decoder); 374 375 static DecodeStatus DecodeSimm16(MCInst &Inst, 376 unsigned Insn, 377 uint64_t Address, 378 const void *Decoder); 379 380 template <unsigned Bits, int Offset, int Scale> 381 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 382 uint64_t Address, 383 const void *Decoder); 384 385 template <unsigned Bits, int Offset> 386 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 387 uint64_t Address, 388 const void *Decoder) { 389 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 390 Decoder); 391 } 392 393 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 394 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 395 uint64_t Address, 396 const void *Decoder); 397 398 static DecodeStatus DecodeInsSize(MCInst &Inst, 399 unsigned Insn, 400 uint64_t Address, 401 const void *Decoder); 402 403 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 404 uint64_t Address, const void *Decoder); 405 406 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 407 uint64_t Address, const void *Decoder); 408 409 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 410 uint64_t Address, const void *Decoder); 411 412 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 413 uint64_t Address, const void *Decoder); 414 415 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 416 uint64_t Address, const void *Decoder); 417 418 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 419 /// handle. 420 template <typename InsnType> 421 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 422 const void *Decoder); 423 424 template <typename InsnType> 425 static DecodeStatus 426 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 427 const void *Decoder); 428 429 template <typename InsnType> 430 static DecodeStatus 431 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 432 const void *Decoder); 433 434 template <typename InsnType> 435 static DecodeStatus 436 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 437 const void *Decoder); 438 439 template <typename InsnType> 440 static DecodeStatus 441 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 442 const void *Decoder); 443 444 template <typename InsnType> 445 static DecodeStatus 446 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 447 const void *Decoder); 448 449 template <typename InsnType> 450 static DecodeStatus 451 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 452 const void *Decoder); 453 454 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 455 uint64_t Address, 456 const void *Decoder); 457 458 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 459 uint64_t Address, 460 const void *Decoder); 461 462 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 463 uint64_t Address, 464 const void *Decoder); 465 466 namespace llvm { 467 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 468 TheMips64elTarget; 469 } 470 471 static MCDisassembler *createMipsDisassembler( 472 const Target &T, 473 const MCSubtargetInfo &STI, 474 MCContext &Ctx) { 475 return new MipsDisassembler(STI, Ctx, true); 476 } 477 478 static MCDisassembler *createMipselDisassembler( 479 const Target &T, 480 const MCSubtargetInfo &STI, 481 MCContext &Ctx) { 482 return new MipsDisassembler(STI, Ctx, false); 483 } 484 485 extern "C" void LLVMInitializeMipsDisassembler() { 486 // Register the disassembler. 487 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 488 createMipsDisassembler); 489 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 490 createMipselDisassembler); 491 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 492 createMipsDisassembler); 493 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 494 createMipselDisassembler); 495 } 496 497 #include "MipsGenDisassemblerTables.inc" 498 499 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 500 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 501 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 502 return *(RegInfo->getRegClass(RC).begin() + RegNo); 503 } 504 505 template <typename InsnType> 506 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 507 const void *Decoder) { 508 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 509 // The size of the n field depends on the element size 510 // The register class also depends on this. 511 InsnType tmp = fieldFromInstruction(insn, 17, 5); 512 unsigned NSize = 0; 513 DecodeFN RegDecoder = nullptr; 514 if ((tmp & 0x18) == 0x00) { // INSVE_B 515 NSize = 4; 516 RegDecoder = DecodeMSA128BRegisterClass; 517 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 518 NSize = 3; 519 RegDecoder = DecodeMSA128HRegisterClass; 520 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 521 NSize = 2; 522 RegDecoder = DecodeMSA128WRegisterClass; 523 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 524 NSize = 1; 525 RegDecoder = DecodeMSA128DRegisterClass; 526 } else 527 llvm_unreachable("Invalid encoding"); 528 529 assert(NSize != 0 && RegDecoder != nullptr); 530 531 // $wd 532 tmp = fieldFromInstruction(insn, 6, 5); 533 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 534 return MCDisassembler::Fail; 535 // $wd_in 536 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 537 return MCDisassembler::Fail; 538 // $n 539 tmp = fieldFromInstruction(insn, 16, NSize); 540 MI.addOperand(MCOperand::createImm(tmp)); 541 // $ws 542 tmp = fieldFromInstruction(insn, 11, 5); 543 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 544 return MCDisassembler::Fail; 545 // $n2 546 MI.addOperand(MCOperand::createImm(0)); 547 548 return MCDisassembler::Success; 549 } 550 551 template <typename InsnType> 552 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 553 uint64_t Address, 554 const void *Decoder) { 555 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 556 // (otherwise we would have matched the ADDI instruction from the earlier 557 // ISA's instead). 558 // 559 // We have: 560 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 561 // BOVC if rs >= rt 562 // BEQZALC if rs == 0 && rt != 0 563 // BEQC if rs < rt && rs != 0 564 565 InsnType Rs = fieldFromInstruction(insn, 21, 5); 566 InsnType Rt = fieldFromInstruction(insn, 16, 5); 567 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 568 bool HasRs = false; 569 570 if (Rs >= Rt) { 571 MI.setOpcode(Mips::BOVC); 572 HasRs = true; 573 } else if (Rs != 0 && Rs < Rt) { 574 MI.setOpcode(Mips::BEQC); 575 HasRs = true; 576 } else 577 MI.setOpcode(Mips::BEQZALC); 578 579 if (HasRs) 580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 581 Rs))); 582 583 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 584 Rt))); 585 MI.addOperand(MCOperand::createImm(Imm)); 586 587 return MCDisassembler::Success; 588 } 589 590 template <typename InsnType> 591 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 592 uint64_t Address, 593 const void *Decoder) { 594 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 595 // (otherwise we would have matched the ADDI instruction from the earlier 596 // ISA's instead). 597 // 598 // We have: 599 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 600 // BNVC if rs >= rt 601 // BNEZALC if rs == 0 && rt != 0 602 // BNEC if rs < rt && rs != 0 603 604 InsnType Rs = fieldFromInstruction(insn, 21, 5); 605 InsnType Rt = fieldFromInstruction(insn, 16, 5); 606 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 607 bool HasRs = false; 608 609 if (Rs >= Rt) { 610 MI.setOpcode(Mips::BNVC); 611 HasRs = true; 612 } else if (Rs != 0 && Rs < Rt) { 613 MI.setOpcode(Mips::BNEC); 614 HasRs = true; 615 } else 616 MI.setOpcode(Mips::BNEZALC); 617 618 if (HasRs) 619 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 620 Rs))); 621 622 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 623 Rt))); 624 MI.addOperand(MCOperand::createImm(Imm)); 625 626 return MCDisassembler::Success; 627 } 628 629 template <typename InsnType> 630 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 631 uint64_t Address, 632 const void *Decoder) { 633 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 634 // (otherwise we would have matched the BLEZL instruction from the earlier 635 // ISA's instead). 636 // 637 // We have: 638 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 639 // Invalid if rs == 0 640 // BLEZC if rs == 0 && rt != 0 641 // BGEZC if rs == rt && rt != 0 642 // BGEC if rs != rt && rs != 0 && rt != 0 643 644 InsnType Rs = fieldFromInstruction(insn, 21, 5); 645 InsnType Rt = fieldFromInstruction(insn, 16, 5); 646 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 647 bool HasRs = false; 648 649 if (Rt == 0) 650 return MCDisassembler::Fail; 651 else if (Rs == 0) 652 MI.setOpcode(Mips::BLEZC); 653 else if (Rs == Rt) 654 MI.setOpcode(Mips::BGEZC); 655 else { 656 HasRs = true; 657 MI.setOpcode(Mips::BGEC); 658 } 659 660 if (HasRs) 661 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 662 Rs))); 663 664 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 665 Rt))); 666 667 MI.addOperand(MCOperand::createImm(Imm)); 668 669 return MCDisassembler::Success; 670 } 671 672 template <typename InsnType> 673 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 674 uint64_t Address, 675 const void *Decoder) { 676 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 677 // (otherwise we would have matched the BGTZL instruction from the earlier 678 // ISA's instead). 679 // 680 // We have: 681 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 682 // Invalid if rs == 0 683 // BGTZC if rs == 0 && rt != 0 684 // BLTZC if rs == rt && rt != 0 685 // BLTC if rs != rt && rs != 0 && rt != 0 686 687 bool HasRs = false; 688 689 InsnType Rs = fieldFromInstruction(insn, 21, 5); 690 InsnType Rt = fieldFromInstruction(insn, 16, 5); 691 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 692 693 if (Rt == 0) 694 return MCDisassembler::Fail; 695 else if (Rs == 0) 696 MI.setOpcode(Mips::BGTZC); 697 else if (Rs == Rt) 698 MI.setOpcode(Mips::BLTZC); 699 else { 700 MI.setOpcode(Mips::BLTC); 701 HasRs = true; 702 } 703 704 if (HasRs) 705 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 706 Rs))); 707 708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 709 Rt))); 710 711 MI.addOperand(MCOperand::createImm(Imm)); 712 713 return MCDisassembler::Success; 714 } 715 716 template <typename InsnType> 717 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 718 uint64_t Address, 719 const void *Decoder) { 720 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 721 // (otherwise we would have matched the BGTZ instruction from the earlier 722 // ISA's instead). 723 // 724 // We have: 725 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 726 // BGTZ if rt == 0 727 // BGTZALC if rs == 0 && rt != 0 728 // BLTZALC if rs != 0 && rs == rt 729 // BLTUC if rs != 0 && rs != rt 730 731 InsnType Rs = fieldFromInstruction(insn, 21, 5); 732 InsnType Rt = fieldFromInstruction(insn, 16, 5); 733 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 734 bool HasRs = false; 735 bool HasRt = false; 736 737 if (Rt == 0) { 738 MI.setOpcode(Mips::BGTZ); 739 HasRs = true; 740 } else if (Rs == 0) { 741 MI.setOpcode(Mips::BGTZALC); 742 HasRt = true; 743 } else if (Rs == Rt) { 744 MI.setOpcode(Mips::BLTZALC); 745 HasRs = true; 746 } else { 747 MI.setOpcode(Mips::BLTUC); 748 HasRs = true; 749 HasRt = true; 750 } 751 752 if (HasRs) 753 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 754 Rs))); 755 756 if (HasRt) 757 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 758 Rt))); 759 760 MI.addOperand(MCOperand::createImm(Imm)); 761 762 return MCDisassembler::Success; 763 } 764 765 template <typename InsnType> 766 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 767 uint64_t Address, 768 const void *Decoder) { 769 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 770 // (otherwise we would have matched the BLEZL instruction from the earlier 771 // ISA's instead). 772 // 773 // We have: 774 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 775 // Invalid if rs == 0 776 // BLEZALC if rs == 0 && rt != 0 777 // BGEZALC if rs == rt && rt != 0 778 // BGEUC if rs != rt && rs != 0 && rt != 0 779 780 InsnType Rs = fieldFromInstruction(insn, 21, 5); 781 InsnType Rt = fieldFromInstruction(insn, 16, 5); 782 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 783 bool HasRs = false; 784 785 if (Rt == 0) 786 return MCDisassembler::Fail; 787 else if (Rs == 0) 788 MI.setOpcode(Mips::BLEZALC); 789 else if (Rs == Rt) 790 MI.setOpcode(Mips::BGEZALC); 791 else { 792 HasRs = true; 793 MI.setOpcode(Mips::BGEUC); 794 } 795 796 if (HasRs) 797 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 798 Rs))); 799 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 800 Rt))); 801 802 MI.addOperand(MCOperand::createImm(Imm)); 803 804 return MCDisassembler::Success; 805 } 806 807 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 808 /// according to the given endianess. 809 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 810 uint64_t &Size, uint32_t &Insn, 811 bool IsBigEndian) { 812 // We want to read exactly 2 Bytes of data. 813 if (Bytes.size() < 2) { 814 Size = 0; 815 return MCDisassembler::Fail; 816 } 817 818 if (IsBigEndian) { 819 Insn = (Bytes[0] << 8) | Bytes[1]; 820 } else { 821 Insn = (Bytes[1] << 8) | Bytes[0]; 822 } 823 824 return MCDisassembler::Success; 825 } 826 827 /// Read four bytes from the ArrayRef and return 32 bit word sorted 828 /// according to the given endianess 829 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 830 uint64_t &Size, uint32_t &Insn, 831 bool IsBigEndian, bool IsMicroMips) { 832 // We want to read exactly 4 Bytes of data. 833 if (Bytes.size() < 4) { 834 Size = 0; 835 return MCDisassembler::Fail; 836 } 837 838 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 839 // always precede the low 16 bits in the instruction stream (that is, they 840 // are placed at lower addresses in the instruction stream). 841 // 842 // microMIPS byte ordering: 843 // Big-endian: 0 | 1 | 2 | 3 844 // Little-endian: 1 | 0 | 3 | 2 845 846 if (IsBigEndian) { 847 // Encoded as a big-endian 32-bit word in the stream. 848 Insn = 849 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 850 } else { 851 if (IsMicroMips) { 852 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 853 (Bytes[1] << 24); 854 } else { 855 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 856 (Bytes[3] << 24); 857 } 858 } 859 860 return MCDisassembler::Success; 861 } 862 863 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 864 ArrayRef<uint8_t> Bytes, 865 uint64_t Address, 866 raw_ostream &VStream, 867 raw_ostream &CStream) const { 868 uint32_t Insn; 869 DecodeStatus Result; 870 871 if (IsMicroMips) { 872 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 873 if (Result == MCDisassembler::Fail) 874 return MCDisassembler::Fail; 875 876 if (hasMips32r6()) { 877 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 878 // Calling the auto-generated decoder function for microMIPS32R6 879 // (and microMIPS64R6) 16-bit instructions. 880 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 881 Address, this, STI); 882 if (Result != MCDisassembler::Fail) { 883 Size = 2; 884 return Result; 885 } 886 } 887 888 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 889 // Calling the auto-generated decoder function for microMIPS 16-bit 890 // instructions. 891 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 892 this, STI); 893 if (Result != MCDisassembler::Fail) { 894 Size = 2; 895 return Result; 896 } 897 898 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 899 if (Result == MCDisassembler::Fail) 900 return MCDisassembler::Fail; 901 902 if (hasMips32r6()) { 903 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 904 // Calling the auto-generated decoder function. 905 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 906 this, STI); 907 if (Result != MCDisassembler::Fail) { 908 Size = 4; 909 return Result; 910 } 911 } 912 913 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 914 // Calling the auto-generated decoder function. 915 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 916 this, STI); 917 if (Result != MCDisassembler::Fail) { 918 Size = 4; 919 return Result; 920 } 921 922 if (hasMips32r6()) { 923 DEBUG(dbgs() << "Trying MicroMips32r6FPU table (32-bit opcodes):\n"); 924 Result = decodeInstruction(DecoderTableMicroMips32r6FPU32, Instr, Insn, 925 Address, this, STI); 926 if (Result != MCDisassembler::Fail) { 927 Size = 4; 928 return Result; 929 } 930 } 931 932 // This is an invalid instruction. Let the disassembler move forward by the 933 // minimum instruction size. 934 Size = 2; 935 return MCDisassembler::Fail; 936 } 937 938 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 939 if (Result == MCDisassembler::Fail) { 940 Size = 4; 941 return MCDisassembler::Fail; 942 } 943 944 if (hasCOP3()) { 945 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 946 Result = 947 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 948 if (Result != MCDisassembler::Fail) { 949 Size = 4; 950 return Result; 951 } 952 } 953 954 if (hasMips32r6() && isGP64()) { 955 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 956 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 957 Address, this, STI); 958 if (Result != MCDisassembler::Fail) { 959 Size = 4; 960 return Result; 961 } 962 } 963 964 if (hasMips32r6()) { 965 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 966 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 967 Address, this, STI); 968 if (Result != MCDisassembler::Fail) { 969 Size = 4; 970 return Result; 971 } 972 } 973 974 if (hasCnMips()) { 975 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 976 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 977 Address, this, STI); 978 if (Result != MCDisassembler::Fail) { 979 Size = 4; 980 return Result; 981 } 982 } 983 984 if (isGP64()) { 985 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 986 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 987 Address, this, STI); 988 if (Result != MCDisassembler::Fail) { 989 Size = 4; 990 return Result; 991 } 992 } 993 994 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 995 // Calling the auto-generated decoder function. 996 Result = 997 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 998 if (Result != MCDisassembler::Fail) { 999 Size = 4; 1000 return Result; 1001 } 1002 1003 Size = 4; 1004 return MCDisassembler::Fail; 1005 } 1006 1007 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1008 unsigned RegNo, 1009 uint64_t Address, 1010 const void *Decoder) { 1011 1012 return MCDisassembler::Fail; 1013 1014 } 1015 1016 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1017 unsigned RegNo, 1018 uint64_t Address, 1019 const void *Decoder) { 1020 1021 if (RegNo > 31) 1022 return MCDisassembler::Fail; 1023 1024 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1025 Inst.addOperand(MCOperand::createReg(Reg)); 1026 return MCDisassembler::Success; 1027 } 1028 1029 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1030 unsigned RegNo, 1031 uint64_t Address, 1032 const void *Decoder) { 1033 if (RegNo > 7) 1034 return MCDisassembler::Fail; 1035 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1036 Inst.addOperand(MCOperand::createReg(Reg)); 1037 return MCDisassembler::Success; 1038 } 1039 1040 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1041 unsigned RegNo, 1042 uint64_t Address, 1043 const void *Decoder) { 1044 if (RegNo > 7) 1045 return MCDisassembler::Fail; 1046 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1047 Inst.addOperand(MCOperand::createReg(Reg)); 1048 return MCDisassembler::Success; 1049 } 1050 1051 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1052 unsigned RegNo, 1053 uint64_t Address, 1054 const void *Decoder) { 1055 if (RegNo > 7) 1056 return MCDisassembler::Fail; 1057 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1058 Inst.addOperand(MCOperand::createReg(Reg)); 1059 return MCDisassembler::Success; 1060 } 1061 1062 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1063 unsigned RegNo, 1064 uint64_t Address, 1065 const void *Decoder) { 1066 if (RegNo > 31) 1067 return MCDisassembler::Fail; 1068 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1069 Inst.addOperand(MCOperand::createReg(Reg)); 1070 return MCDisassembler::Success; 1071 } 1072 1073 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1074 unsigned RegNo, 1075 uint64_t Address, 1076 const void *Decoder) { 1077 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1078 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1079 1080 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1081 } 1082 1083 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1084 unsigned RegNo, 1085 uint64_t Address, 1086 const void *Decoder) { 1087 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1088 } 1089 1090 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1091 unsigned RegNo, 1092 uint64_t Address, 1093 const void *Decoder) { 1094 if (RegNo > 31) 1095 return MCDisassembler::Fail; 1096 1097 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1098 Inst.addOperand(MCOperand::createReg(Reg)); 1099 return MCDisassembler::Success; 1100 } 1101 1102 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1103 unsigned RegNo, 1104 uint64_t Address, 1105 const void *Decoder) { 1106 if (RegNo > 31) 1107 return MCDisassembler::Fail; 1108 1109 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1110 Inst.addOperand(MCOperand::createReg(Reg)); 1111 return MCDisassembler::Success; 1112 } 1113 1114 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1115 unsigned RegNo, 1116 uint64_t Address, 1117 const void *Decoder) { 1118 if (RegNo > 31) 1119 return MCDisassembler::Fail; 1120 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1121 Inst.addOperand(MCOperand::createReg(Reg)); 1122 return MCDisassembler::Success; 1123 } 1124 1125 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1126 unsigned RegNo, 1127 uint64_t Address, 1128 const void *Decoder) { 1129 if (RegNo > 7) 1130 return MCDisassembler::Fail; 1131 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1132 Inst.addOperand(MCOperand::createReg(Reg)); 1133 return MCDisassembler::Success; 1134 } 1135 1136 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1137 uint64_t Address, 1138 const void *Decoder) { 1139 if (RegNo > 31) 1140 return MCDisassembler::Fail; 1141 1142 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1143 Inst.addOperand(MCOperand::createReg(Reg)); 1144 return MCDisassembler::Success; 1145 } 1146 1147 static DecodeStatus DecodeMem(MCInst &Inst, 1148 unsigned Insn, 1149 uint64_t Address, 1150 const void *Decoder) { 1151 int Offset = SignExtend32<16>(Insn & 0xffff); 1152 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1153 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1154 1155 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1156 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1157 1158 if (Inst.getOpcode() == Mips::SC || 1159 Inst.getOpcode() == Mips::SCD) 1160 Inst.addOperand(MCOperand::createReg(Reg)); 1161 1162 Inst.addOperand(MCOperand::createReg(Reg)); 1163 Inst.addOperand(MCOperand::createReg(Base)); 1164 Inst.addOperand(MCOperand::createImm(Offset)); 1165 1166 return MCDisassembler::Success; 1167 } 1168 1169 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1170 unsigned Insn, 1171 uint64_t Address, 1172 const void *Decoder) { 1173 int Offset = SignExtend32<9>(Insn >> 7); 1174 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1175 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1176 1177 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1178 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1179 1180 if (Inst.getOpcode() == Mips::SCE) 1181 Inst.addOperand(MCOperand::createReg(Reg)); 1182 1183 Inst.addOperand(MCOperand::createReg(Reg)); 1184 Inst.addOperand(MCOperand::createReg(Base)); 1185 Inst.addOperand(MCOperand::createImm(Offset)); 1186 1187 return MCDisassembler::Success; 1188 } 1189 1190 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1191 unsigned Insn, 1192 uint64_t Address, 1193 const void *Decoder) { 1194 int Offset = SignExtend32<9>(Insn & 0x1ff); 1195 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1196 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1197 1198 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1199 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1200 1201 Inst.addOperand(MCOperand::createReg(Reg)); 1202 Inst.addOperand(MCOperand::createReg(Base)); 1203 Inst.addOperand(MCOperand::createImm(Offset)); 1204 1205 return MCDisassembler::Success; 1206 } 1207 1208 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1209 unsigned Insn, 1210 uint64_t Address, 1211 const void *Decoder) { 1212 int Offset = SignExtend32<16>(Insn & 0xffff); 1213 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1214 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1215 1216 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1217 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1218 1219 Inst.addOperand(MCOperand::createReg(Reg)); 1220 Inst.addOperand(MCOperand::createReg(Base)); 1221 Inst.addOperand(MCOperand::createImm(Offset)); 1222 1223 return MCDisassembler::Success; 1224 } 1225 1226 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1227 unsigned Insn, 1228 uint64_t Address, 1229 const void *Decoder) { 1230 int Offset = SignExtend32<16>(Insn & 0xffff); 1231 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1232 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1233 1234 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1235 1236 Inst.addOperand(MCOperand::createReg(Base)); 1237 Inst.addOperand(MCOperand::createImm(Offset)); 1238 Inst.addOperand(MCOperand::createImm(Hint)); 1239 1240 return MCDisassembler::Success; 1241 } 1242 1243 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1244 unsigned Insn, 1245 uint64_t Address, 1246 const void *Decoder) { 1247 int Offset = SignExtend32<12>(Insn & 0xfff); 1248 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1249 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1250 1251 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1252 1253 Inst.addOperand(MCOperand::createReg(Base)); 1254 Inst.addOperand(MCOperand::createImm(Offset)); 1255 Inst.addOperand(MCOperand::createImm(Hint)); 1256 1257 return MCDisassembler::Success; 1258 } 1259 1260 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1261 unsigned Insn, 1262 uint64_t Address, 1263 const void *Decoder) { 1264 int Offset = SignExtend32<9>(Insn & 0x1ff); 1265 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1266 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1267 1268 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1269 1270 Inst.addOperand(MCOperand::createReg(Base)); 1271 Inst.addOperand(MCOperand::createImm(Offset)); 1272 Inst.addOperand(MCOperand::createImm(Hint)); 1273 1274 return MCDisassembler::Success; 1275 } 1276 1277 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1278 unsigned Insn, 1279 uint64_t Address, 1280 const void *Decoder) { 1281 int Offset = SignExtend32<9>(Insn >> 7); 1282 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1283 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1284 1285 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1286 1287 Inst.addOperand(MCOperand::createReg(Base)); 1288 Inst.addOperand(MCOperand::createImm(Offset)); 1289 Inst.addOperand(MCOperand::createImm(Hint)); 1290 1291 return MCDisassembler::Success; 1292 } 1293 1294 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1295 unsigned Insn, 1296 uint64_t Address, 1297 const void *Decoder) { 1298 int Offset = SignExtend32<9>(Insn & 0x1ff); 1299 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1300 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1301 1302 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1303 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1304 1305 Inst.addOperand(MCOperand::createReg(Reg)); 1306 Inst.addOperand(MCOperand::createReg(Base)); 1307 Inst.addOperand(MCOperand::createImm(Offset)); 1308 1309 return MCDisassembler::Success; 1310 } 1311 1312 static DecodeStatus DecodeSyncI(MCInst &Inst, 1313 unsigned Insn, 1314 uint64_t Address, 1315 const void *Decoder) { 1316 int Offset = SignExtend32<16>(Insn & 0xffff); 1317 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1318 1319 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1320 1321 Inst.addOperand(MCOperand::createReg(Base)); 1322 Inst.addOperand(MCOperand::createImm(Offset)); 1323 1324 return MCDisassembler::Success; 1325 } 1326 1327 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1328 unsigned Insn, 1329 uint64_t Address, 1330 const void *Decoder) { 1331 int Immediate = SignExtend32<16>(Insn & 0xffff); 1332 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1333 1334 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1335 1336 Inst.addOperand(MCOperand::createReg(Base)); 1337 Inst.addOperand(MCOperand::createImm(Immediate)); 1338 1339 return MCDisassembler::Success; 1340 } 1341 1342 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1343 uint64_t Address, const void *Decoder) { 1344 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1345 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1346 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1347 1348 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1349 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1350 1351 Inst.addOperand(MCOperand::createReg(Reg)); 1352 Inst.addOperand(MCOperand::createReg(Base)); 1353 1354 // The immediate field of an LD/ST instruction is scaled which means it must 1355 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1356 // data format. 1357 // .b - 1 byte 1358 // .h - 2 bytes 1359 // .w - 4 bytes 1360 // .d - 8 bytes 1361 switch(Inst.getOpcode()) 1362 { 1363 default: 1364 assert (0 && "Unexpected instruction"); 1365 return MCDisassembler::Fail; 1366 break; 1367 case Mips::LD_B: 1368 case Mips::ST_B: 1369 Inst.addOperand(MCOperand::createImm(Offset)); 1370 break; 1371 case Mips::LD_H: 1372 case Mips::ST_H: 1373 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1374 break; 1375 case Mips::LD_W: 1376 case Mips::ST_W: 1377 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1378 break; 1379 case Mips::LD_D: 1380 case Mips::ST_D: 1381 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1382 break; 1383 } 1384 1385 return MCDisassembler::Success; 1386 } 1387 1388 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1389 unsigned Insn, 1390 uint64_t Address, 1391 const void *Decoder) { 1392 unsigned Offset = Insn & 0xf; 1393 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1394 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1395 1396 switch (Inst.getOpcode()) { 1397 case Mips::LBU16_MM: 1398 case Mips::LHU16_MM: 1399 case Mips::LW16_MM: 1400 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1401 == MCDisassembler::Fail) 1402 return MCDisassembler::Fail; 1403 break; 1404 case Mips::SB16_MM: 1405 case Mips::SB16_MMR6: 1406 case Mips::SH16_MM: 1407 case Mips::SH16_MMR6: 1408 case Mips::SW16_MM: 1409 case Mips::SW16_MMR6: 1410 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1411 == MCDisassembler::Fail) 1412 return MCDisassembler::Fail; 1413 break; 1414 } 1415 1416 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1417 == MCDisassembler::Fail) 1418 return MCDisassembler::Fail; 1419 1420 switch (Inst.getOpcode()) { 1421 case Mips::LBU16_MM: 1422 if (Offset == 0xf) 1423 Inst.addOperand(MCOperand::createImm(-1)); 1424 else 1425 Inst.addOperand(MCOperand::createImm(Offset)); 1426 break; 1427 case Mips::SB16_MM: 1428 case Mips::SB16_MMR6: 1429 Inst.addOperand(MCOperand::createImm(Offset)); 1430 break; 1431 case Mips::LHU16_MM: 1432 case Mips::SH16_MM: 1433 case Mips::SH16_MMR6: 1434 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1435 break; 1436 case Mips::LW16_MM: 1437 case Mips::SW16_MM: 1438 case Mips::SW16_MMR6: 1439 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1440 break; 1441 } 1442 1443 return MCDisassembler::Success; 1444 } 1445 1446 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1447 unsigned Insn, 1448 uint64_t Address, 1449 const void *Decoder) { 1450 unsigned Offset = Insn & 0x1F; 1451 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1452 1453 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1454 1455 Inst.addOperand(MCOperand::createReg(Reg)); 1456 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1457 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1458 1459 return MCDisassembler::Success; 1460 } 1461 1462 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1463 unsigned Insn, 1464 uint64_t Address, 1465 const void *Decoder) { 1466 unsigned Offset = Insn & 0x7F; 1467 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1468 1469 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1470 1471 Inst.addOperand(MCOperand::createReg(Reg)); 1472 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1473 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1474 1475 return MCDisassembler::Success; 1476 } 1477 1478 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1479 unsigned Insn, 1480 uint64_t Address, 1481 const void *Decoder) { 1482 int Offset; 1483 switch (Inst.getOpcode()) { 1484 case Mips::LWM16_MMR6: 1485 case Mips::SWM16_MMR6: 1486 Offset = fieldFromInstruction(Insn, 4, 4); 1487 break; 1488 default: 1489 Offset = SignExtend32<4>(Insn & 0xf); 1490 break; 1491 } 1492 1493 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1494 == MCDisassembler::Fail) 1495 return MCDisassembler::Fail; 1496 1497 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1498 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1499 1500 return MCDisassembler::Success; 1501 } 1502 1503 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1504 unsigned Insn, 1505 uint64_t Address, 1506 const void *Decoder) { 1507 int Offset = SignExtend32<9>(Insn & 0x1ff); 1508 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1509 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1510 1511 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1512 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1513 1514 if (Inst.getOpcode() == Mips::SCE_MM) 1515 Inst.addOperand(MCOperand::createReg(Reg)); 1516 1517 Inst.addOperand(MCOperand::createReg(Reg)); 1518 Inst.addOperand(MCOperand::createReg(Base)); 1519 Inst.addOperand(MCOperand::createImm(Offset)); 1520 1521 return MCDisassembler::Success; 1522 } 1523 1524 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1525 unsigned Insn, 1526 uint64_t Address, 1527 const void *Decoder) { 1528 int Offset = SignExtend32<12>(Insn & 0x0fff); 1529 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1530 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1531 1532 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1533 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1534 1535 switch (Inst.getOpcode()) { 1536 case Mips::SWM32_MM: 1537 case Mips::LWM32_MM: 1538 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1539 == MCDisassembler::Fail) 1540 return MCDisassembler::Fail; 1541 Inst.addOperand(MCOperand::createReg(Base)); 1542 Inst.addOperand(MCOperand::createImm(Offset)); 1543 break; 1544 case Mips::SC_MM: 1545 Inst.addOperand(MCOperand::createReg(Reg)); 1546 // fallthrough 1547 default: 1548 Inst.addOperand(MCOperand::createReg(Reg)); 1549 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1550 Inst.addOperand(MCOperand::createReg(Reg+1)); 1551 1552 Inst.addOperand(MCOperand::createReg(Base)); 1553 Inst.addOperand(MCOperand::createImm(Offset)); 1554 } 1555 1556 return MCDisassembler::Success; 1557 } 1558 1559 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1560 unsigned Insn, 1561 uint64_t Address, 1562 const void *Decoder) { 1563 int Offset = SignExtend32<16>(Insn & 0xffff); 1564 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1565 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1566 1567 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1568 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1569 1570 Inst.addOperand(MCOperand::createReg(Reg)); 1571 Inst.addOperand(MCOperand::createReg(Base)); 1572 Inst.addOperand(MCOperand::createImm(Offset)); 1573 1574 return MCDisassembler::Success; 1575 } 1576 1577 static DecodeStatus DecodeFMem(MCInst &Inst, 1578 unsigned Insn, 1579 uint64_t Address, 1580 const void *Decoder) { 1581 int Offset = SignExtend32<16>(Insn & 0xffff); 1582 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1583 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1584 1585 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1586 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1587 1588 Inst.addOperand(MCOperand::createReg(Reg)); 1589 Inst.addOperand(MCOperand::createReg(Base)); 1590 Inst.addOperand(MCOperand::createImm(Offset)); 1591 1592 return MCDisassembler::Success; 1593 } 1594 1595 static DecodeStatus DecodeFMem2(MCInst &Inst, 1596 unsigned Insn, 1597 uint64_t Address, 1598 const void *Decoder) { 1599 int Offset = SignExtend32<16>(Insn & 0xffff); 1600 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1601 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1602 1603 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1604 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1605 1606 Inst.addOperand(MCOperand::createReg(Reg)); 1607 Inst.addOperand(MCOperand::createReg(Base)); 1608 Inst.addOperand(MCOperand::createImm(Offset)); 1609 1610 return MCDisassembler::Success; 1611 } 1612 1613 static DecodeStatus DecodeFMem3(MCInst &Inst, 1614 unsigned Insn, 1615 uint64_t Address, 1616 const void *Decoder) { 1617 int Offset = SignExtend32<16>(Insn & 0xffff); 1618 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1619 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1620 1621 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1622 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1623 1624 Inst.addOperand(MCOperand::createReg(Reg)); 1625 Inst.addOperand(MCOperand::createReg(Base)); 1626 Inst.addOperand(MCOperand::createImm(Offset)); 1627 1628 return MCDisassembler::Success; 1629 } 1630 1631 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1632 unsigned Insn, 1633 uint64_t Address, 1634 const void *Decoder) { 1635 int Offset = SignExtend32<11>(Insn & 0x07ff); 1636 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1637 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1638 1639 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1640 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1641 1642 Inst.addOperand(MCOperand::createReg(Reg)); 1643 Inst.addOperand(MCOperand::createReg(Base)); 1644 Inst.addOperand(MCOperand::createImm(Offset)); 1645 1646 return MCDisassembler::Success; 1647 } 1648 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1649 unsigned Insn, 1650 uint64_t Address, 1651 const void *Decoder) { 1652 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1653 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1654 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1655 1656 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1657 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1658 1659 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1660 Inst.addOperand(MCOperand::createReg(Rt)); 1661 } 1662 1663 Inst.addOperand(MCOperand::createReg(Rt)); 1664 Inst.addOperand(MCOperand::createReg(Base)); 1665 Inst.addOperand(MCOperand::createImm(Offset)); 1666 1667 return MCDisassembler::Success; 1668 } 1669 1670 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1671 unsigned RegNo, 1672 uint64_t Address, 1673 const void *Decoder) { 1674 // Currently only hardware register 29 is supported. 1675 if (RegNo != 29) 1676 return MCDisassembler::Fail; 1677 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1678 return MCDisassembler::Success; 1679 } 1680 1681 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1682 unsigned RegNo, 1683 uint64_t Address, 1684 const void *Decoder) { 1685 if (RegNo > 30 || RegNo %2) 1686 return MCDisassembler::Fail; 1687 1688 ; 1689 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1690 Inst.addOperand(MCOperand::createReg(Reg)); 1691 return MCDisassembler::Success; 1692 } 1693 1694 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1695 unsigned RegNo, 1696 uint64_t Address, 1697 const void *Decoder) { 1698 if (RegNo >= 4) 1699 return MCDisassembler::Fail; 1700 1701 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1702 Inst.addOperand(MCOperand::createReg(Reg)); 1703 return MCDisassembler::Success; 1704 } 1705 1706 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1707 unsigned RegNo, 1708 uint64_t Address, 1709 const void *Decoder) { 1710 if (RegNo >= 4) 1711 return MCDisassembler::Fail; 1712 1713 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1714 Inst.addOperand(MCOperand::createReg(Reg)); 1715 return MCDisassembler::Success; 1716 } 1717 1718 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1719 unsigned RegNo, 1720 uint64_t Address, 1721 const void *Decoder) { 1722 if (RegNo >= 4) 1723 return MCDisassembler::Fail; 1724 1725 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1726 Inst.addOperand(MCOperand::createReg(Reg)); 1727 return MCDisassembler::Success; 1728 } 1729 1730 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1731 unsigned RegNo, 1732 uint64_t Address, 1733 const void *Decoder) { 1734 if (RegNo > 31) 1735 return MCDisassembler::Fail; 1736 1737 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1738 Inst.addOperand(MCOperand::createReg(Reg)); 1739 return MCDisassembler::Success; 1740 } 1741 1742 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1743 unsigned RegNo, 1744 uint64_t Address, 1745 const void *Decoder) { 1746 if (RegNo > 31) 1747 return MCDisassembler::Fail; 1748 1749 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1750 Inst.addOperand(MCOperand::createReg(Reg)); 1751 return MCDisassembler::Success; 1752 } 1753 1754 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1755 unsigned RegNo, 1756 uint64_t Address, 1757 const void *Decoder) { 1758 if (RegNo > 31) 1759 return MCDisassembler::Fail; 1760 1761 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1762 Inst.addOperand(MCOperand::createReg(Reg)); 1763 return MCDisassembler::Success; 1764 } 1765 1766 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1767 unsigned RegNo, 1768 uint64_t Address, 1769 const void *Decoder) { 1770 if (RegNo > 31) 1771 return MCDisassembler::Fail; 1772 1773 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1774 Inst.addOperand(MCOperand::createReg(Reg)); 1775 return MCDisassembler::Success; 1776 } 1777 1778 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1779 unsigned RegNo, 1780 uint64_t Address, 1781 const void *Decoder) { 1782 if (RegNo > 7) 1783 return MCDisassembler::Fail; 1784 1785 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1786 Inst.addOperand(MCOperand::createReg(Reg)); 1787 return MCDisassembler::Success; 1788 } 1789 1790 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1791 unsigned RegNo, 1792 uint64_t Address, 1793 const void *Decoder) { 1794 if (RegNo > 31) 1795 return MCDisassembler::Fail; 1796 1797 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1798 Inst.addOperand(MCOperand::createReg(Reg)); 1799 return MCDisassembler::Success; 1800 } 1801 1802 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1803 unsigned RegNo, 1804 uint64_t Address, 1805 const void *Decoder) { 1806 if (RegNo > 31) 1807 return MCDisassembler::Fail; 1808 1809 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1810 Inst.addOperand(MCOperand::createReg(Reg)); 1811 return MCDisassembler::Success; 1812 } 1813 1814 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1815 unsigned Offset, 1816 uint64_t Address, 1817 const void *Decoder) { 1818 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1819 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1820 return MCDisassembler::Success; 1821 } 1822 1823 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1824 unsigned Insn, 1825 uint64_t Address, 1826 const void *Decoder) { 1827 1828 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1829 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1830 return MCDisassembler::Success; 1831 } 1832 1833 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1834 unsigned Offset, 1835 uint64_t Address, 1836 const void *Decoder) { 1837 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1838 1839 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1840 return MCDisassembler::Success; 1841 } 1842 1843 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1844 unsigned Offset, 1845 uint64_t Address, 1846 const void *Decoder) { 1847 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1848 1849 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1850 return MCDisassembler::Success; 1851 } 1852 1853 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1854 unsigned Offset, 1855 uint64_t Address, 1856 const void *Decoder) { 1857 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1858 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1859 return MCDisassembler::Success; 1860 } 1861 1862 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1863 unsigned Offset, 1864 uint64_t Address, 1865 const void *Decoder) { 1866 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1867 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1868 return MCDisassembler::Success; 1869 } 1870 1871 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1872 unsigned Offset, 1873 uint64_t Address, 1874 const void *Decoder) { 1875 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1876 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1877 return MCDisassembler::Success; 1878 } 1879 1880 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 1881 unsigned Offset, 1882 uint64_t Address, 1883 const void *Decoder) { 1884 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 1885 1886 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1887 return MCDisassembler::Success; 1888 } 1889 1890 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1891 unsigned Insn, 1892 uint64_t Address, 1893 const void *Decoder) { 1894 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1895 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1896 return MCDisassembler::Success; 1897 } 1898 1899 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1900 unsigned Value, 1901 uint64_t Address, 1902 const void *Decoder) { 1903 if (Value == 0) 1904 Inst.addOperand(MCOperand::createImm(1)); 1905 else if (Value == 0x7) 1906 Inst.addOperand(MCOperand::createImm(-1)); 1907 else 1908 Inst.addOperand(MCOperand::createImm(Value << 2)); 1909 return MCDisassembler::Success; 1910 } 1911 1912 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 1913 unsigned Value, 1914 uint64_t Address, 1915 const void *Decoder) { 1916 if (Value == 0x7F) 1917 Inst.addOperand(MCOperand::createImm(-1)); 1918 else 1919 Inst.addOperand(MCOperand::createImm(Value)); 1920 return MCDisassembler::Success; 1921 } 1922 1923 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1924 unsigned Value, 1925 uint64_t Address, 1926 const void *Decoder) { 1927 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1928 return MCDisassembler::Success; 1929 } 1930 1931 static DecodeStatus DecodeSimm16(MCInst &Inst, 1932 unsigned Insn, 1933 uint64_t Address, 1934 const void *Decoder) { 1935 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); 1936 return MCDisassembler::Success; 1937 } 1938 1939 template <unsigned Bits, int Offset, int Scale> 1940 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1941 uint64_t Address, 1942 const void *Decoder) { 1943 Value &= ((1 << Bits) - 1); 1944 Value *= Scale; 1945 Inst.addOperand(MCOperand::createImm(Value + Offset)); 1946 return MCDisassembler::Success; 1947 } 1948 1949 template <unsigned Bits, int Offset, int ScaleBy> 1950 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1951 uint64_t Address, 1952 const void *Decoder) { 1953 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 1954 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 1955 return MCDisassembler::Success; 1956 } 1957 1958 static DecodeStatus DecodeInsSize(MCInst &Inst, 1959 unsigned Insn, 1960 uint64_t Address, 1961 const void *Decoder) { 1962 // First we need to grab the pos(lsb) from MCInst. 1963 int Pos = Inst.getOperand(2).getImm(); 1964 int Size = (int) Insn - Pos + 1; 1965 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1966 return MCDisassembler::Success; 1967 } 1968 1969 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1970 uint64_t Address, const void *Decoder) { 1971 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 1972 return MCDisassembler::Success; 1973 } 1974 1975 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1976 uint64_t Address, const void *Decoder) { 1977 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 1978 return MCDisassembler::Success; 1979 } 1980 1981 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1982 uint64_t Address, const void *Decoder) { 1983 int32_t DecodedValue; 1984 switch (Insn) { 1985 case 0: DecodedValue = 256; break; 1986 case 1: DecodedValue = 257; break; 1987 case 510: DecodedValue = -258; break; 1988 case 511: DecodedValue = -257; break; 1989 default: DecodedValue = SignExtend32<9>(Insn); break; 1990 } 1991 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 1992 return MCDisassembler::Success; 1993 } 1994 1995 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1996 uint64_t Address, const void *Decoder) { 1997 // Insn must be >= 0, since it is unsigned that condition is always true. 1998 assert(Insn < 16); 1999 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2000 255, 32768, 65535}; 2001 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2002 return MCDisassembler::Success; 2003 } 2004 2005 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2006 unsigned Insn, 2007 uint64_t Address, 2008 const void *Decoder) { 2009 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2010 Mips::S6, Mips::S7, Mips::FP}; 2011 unsigned RegNum; 2012 2013 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2014 2015 // Empty register lists are not allowed. 2016 if (RegLst == 0) 2017 return MCDisassembler::Fail; 2018 2019 RegNum = RegLst & 0xf; 2020 2021 // RegLst values 10-15, and 26-31 are reserved. 2022 if (RegNum > 9) 2023 return MCDisassembler::Fail; 2024 2025 for (unsigned i = 0; i < RegNum; i++) 2026 Inst.addOperand(MCOperand::createReg(Regs[i])); 2027 2028 if (RegLst & 0x10) 2029 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2030 2031 return MCDisassembler::Success; 2032 } 2033 2034 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2035 uint64_t Address, 2036 const void *Decoder) { 2037 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2038 unsigned RegLst; 2039 switch(Inst.getOpcode()) { 2040 default: 2041 RegLst = fieldFromInstruction(Insn, 4, 2); 2042 break; 2043 case Mips::LWM16_MMR6: 2044 case Mips::SWM16_MMR6: 2045 RegLst = fieldFromInstruction(Insn, 8, 2); 2046 break; 2047 } 2048 unsigned RegNum = RegLst & 0x3; 2049 2050 for (unsigned i = 0; i <= RegNum; i++) 2051 Inst.addOperand(MCOperand::createReg(Regs[i])); 2052 2053 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2054 2055 return MCDisassembler::Success; 2056 } 2057 2058 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2059 uint64_t Address, const void *Decoder) { 2060 2061 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2062 2063 switch (RegPair) { 2064 default: 2065 return MCDisassembler::Fail; 2066 case 0: 2067 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2068 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2069 break; 2070 case 1: 2071 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2072 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2073 break; 2074 case 2: 2075 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2076 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2077 break; 2078 case 3: 2079 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2080 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2081 break; 2082 case 4: 2083 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2084 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2085 break; 2086 case 5: 2087 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2088 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2089 break; 2090 case 6: 2091 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2092 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2093 break; 2094 case 7: 2095 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2096 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2097 break; 2098 } 2099 2100 return MCDisassembler::Success; 2101 } 2102 2103 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2104 uint64_t Address, const void *Decoder) { 2105 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2106 return MCDisassembler::Success; 2107 } 2108