1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the Mips Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/MipsMCTargetDesc.h" 14 #include "Mips.h" 15 #include "TargetInfo/MipsTargetInfo.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCOP3() const { 67 // Only present in MIPS-I and MIPS-II 68 return !hasMips32() && !hasMips3(); 69 } 70 71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 72 ArrayRef<uint8_t> Bytes, uint64_t Address, 73 raw_ostream &VStream, 74 raw_ostream &CStream) const override; 75 }; 76 77 } // end anonymous namespace 78 79 // Forward declare these because the autogenerated code will reference them. 80 // Definitions are further down. 81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 102 unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 112 unsigned Insn, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 132 unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 146 unsigned Insn, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 201 unsigned RegNo, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 206 unsigned Offset, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 216 unsigned Insn, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 226 unsigned Offset, 227 uint64_t Address, 228 const void *Decoder); 229 230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 231 unsigned Offset, 232 uint64_t Address, 233 const void *Decoder); 234 235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 236 // shifted left by 1 bit. 237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 238 unsigned Offset, 239 uint64_t Address, 240 const void *Decoder); 241 242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 243 // shifted left by 1 bit. 244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 245 unsigned Offset, 246 uint64_t Address, 247 const void *Decoder); 248 249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 250 // shifted left by 1 bit. 251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 252 unsigned Offset, 253 uint64_t Address, 254 const void *Decoder); 255 256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 257 // shifted left by 1 bit. 258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 259 unsigned Offset, 260 uint64_t Address, 261 const void *Decoder); 262 263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 264 // shifted left by 1 bit. 265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, 271 // which is shifted left by 2 bit. 272 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 273 unsigned Insn, 274 uint64_t Address, 275 const void *Decoder); 276 277 static DecodeStatus DecodeMem(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeMemEVA(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 293 const void *Decoder); 294 295 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 296 unsigned Insn, 297 uint64_t Address, 298 const void *Decoder); 299 300 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 301 unsigned Insn, 302 uint64_t Address, 303 const void *Decoder); 304 305 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeSyncI(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, 316 unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeSynciR6(MCInst &Inst, 321 unsigned Insn, 322 uint64_t Address, 323 const void *Decoder); 324 325 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 326 uint64_t Address, const void *Decoder); 327 328 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 329 unsigned Insn, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 334 unsigned Insn, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 339 unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 344 unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 349 unsigned Insn, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 354 unsigned Insn, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 359 unsigned Insn, 360 uint64_t Address, 361 const void *Decoder); 362 363 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 364 uint64_t Address, 365 const void *Decoder); 366 367 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 368 uint64_t Address, 369 const void *Decoder); 370 371 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 372 const void *Decoder); 373 374 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 375 const void *Decoder); 376 377 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 380 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 381 uint64_t Address, 382 const void *Decoder); 383 384 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 385 unsigned Insn, 386 uint64_t Address, 387 const void *Decoder); 388 389 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 390 unsigned Value, 391 uint64_t Address, 392 const void *Decoder); 393 394 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 395 unsigned Value, 396 uint64_t Address, 397 const void *Decoder); 398 399 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 400 unsigned Value, 401 uint64_t Address, 402 const void *Decoder); 403 404 template <unsigned Bits, int Offset, int Scale> 405 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 406 uint64_t Address, 407 const void *Decoder); 408 409 template <unsigned Bits, int Offset> 410 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 411 uint64_t Address, 412 const void *Decoder) { 413 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 414 Decoder); 415 } 416 417 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 418 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 419 uint64_t Address, 420 const void *Decoder); 421 422 static DecodeStatus DecodeInsSize(MCInst &Inst, 423 unsigned Insn, 424 uint64_t Address, 425 const void *Decoder); 426 427 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 428 uint64_t Address, const void *Decoder); 429 430 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 431 uint64_t Address, const void *Decoder); 432 433 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 434 uint64_t Address, const void *Decoder); 435 436 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 437 uint64_t Address, const void *Decoder); 438 439 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 440 uint64_t Address, const void *Decoder); 441 442 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 443 /// handle. 444 template <typename InsnType> 445 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 446 const void *Decoder); 447 448 template <typename InsnType> 449 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 450 uint64_t Address, const void *Decoder); 451 452 template <typename InsnType> 453 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 454 const void *Decoder); 455 456 template <typename InsnType> 457 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 458 uint64_t Address, const void *Decoder); 459 460 template <typename InsnType> 461 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 462 const void *Decoder); 463 464 template <typename InsnType> 465 static DecodeStatus 466 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 467 const void *Decoder); 468 469 template <typename InsnType> 470 static DecodeStatus 471 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 472 const void *Decoder); 473 474 template <typename InsnType> 475 static DecodeStatus 476 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 477 const void *Decoder); 478 479 template <typename InsnType> 480 static DecodeStatus 481 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 482 const void *Decoder); 483 484 template <typename InsnType> 485 static DecodeStatus 486 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 487 const void *Decoder); 488 489 template <typename InsnType> 490 static DecodeStatus 491 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 492 const void *Decoder); 493 494 template <typename InsnType> 495 static DecodeStatus 496 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 497 const void *Decoder); 498 499 template <typename InsnType> 500 static DecodeStatus 501 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 502 const void *Decoder); 503 504 template <typename InsnType> 505 static DecodeStatus 506 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 507 const void *Decoder); 508 509 template <typename InsnType> 510 static DecodeStatus 511 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 512 const void *Decoder); 513 514 template <typename InsnType> 515 static DecodeStatus 516 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 517 const void *Decoder); 518 519 template <typename InsnType> 520 static DecodeStatus 521 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 522 const void *Decoder); 523 524 template <typename InsnType> 525 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 526 const void *Decoder); 527 528 template <typename InsnType> 529 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 530 const void *Decoder); 531 532 template <typename InsnType> 533 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 534 const void *Decoder); 535 536 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 537 uint64_t Address, 538 const void *Decoder); 539 540 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 541 uint64_t Address, 542 const void *Decoder); 543 544 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 545 uint64_t Address, 546 const void *Decoder); 547 548 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 549 uint64_t Address, const void *Decoder); 550 551 static MCDisassembler *createMipsDisassembler( 552 const Target &T, 553 const MCSubtargetInfo &STI, 554 MCContext &Ctx) { 555 return new MipsDisassembler(STI, Ctx, true); 556 } 557 558 static MCDisassembler *createMipselDisassembler( 559 const Target &T, 560 const MCSubtargetInfo &STI, 561 MCContext &Ctx) { 562 return new MipsDisassembler(STI, Ctx, false); 563 } 564 565 extern "C" void LLVMInitializeMipsDisassembler() { 566 // Register the disassembler. 567 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 568 createMipsDisassembler); 569 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 570 createMipselDisassembler); 571 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 572 createMipsDisassembler); 573 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 574 createMipselDisassembler); 575 } 576 577 #include "MipsGenDisassemblerTables.inc" 578 579 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 580 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 581 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 582 return *(RegInfo->getRegClass(RC).begin() + RegNo); 583 } 584 585 template <typename InsnType> 586 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 587 const void *Decoder) { 588 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 589 590 // The size of the n field depends on the element size 591 // The register class also depends on this. 592 InsnType tmp = fieldFromInstruction(insn, 17, 5); 593 unsigned NSize = 0; 594 DecodeFN RegDecoder = nullptr; 595 if ((tmp & 0x18) == 0x00) { // INSVE_B 596 NSize = 4; 597 RegDecoder = DecodeMSA128BRegisterClass; 598 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 599 NSize = 3; 600 RegDecoder = DecodeMSA128HRegisterClass; 601 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 602 NSize = 2; 603 RegDecoder = DecodeMSA128WRegisterClass; 604 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 605 NSize = 1; 606 RegDecoder = DecodeMSA128DRegisterClass; 607 } else 608 llvm_unreachable("Invalid encoding"); 609 610 assert(NSize != 0 && RegDecoder != nullptr); 611 612 // $wd 613 tmp = fieldFromInstruction(insn, 6, 5); 614 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 615 return MCDisassembler::Fail; 616 // $wd_in 617 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 618 return MCDisassembler::Fail; 619 // $n 620 tmp = fieldFromInstruction(insn, 16, NSize); 621 MI.addOperand(MCOperand::createImm(tmp)); 622 // $ws 623 tmp = fieldFromInstruction(insn, 11, 5); 624 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 625 return MCDisassembler::Fail; 626 // $n2 627 MI.addOperand(MCOperand::createImm(0)); 628 629 return MCDisassembler::Success; 630 } 631 632 template <typename InsnType> 633 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, 634 uint64_t Address, const void *Decoder) { 635 InsnType Rs = fieldFromInstruction(insn, 16, 5); 636 InsnType Imm = fieldFromInstruction(insn, 0, 16); 637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 638 Rs))); 639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 640 Rs))); 641 MI.addOperand(MCOperand::createImm(Imm)); 642 643 return MCDisassembler::Success; 644 } 645 646 template <typename InsnType> 647 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 648 const void *Decoder) { 649 InsnType Rs = fieldFromInstruction(insn, 21, 5); 650 InsnType Imm = fieldFromInstruction(insn, 0, 16); 651 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 652 Rs))); 653 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 654 Rs))); 655 MI.addOperand(MCOperand::createImm(Imm)); 656 657 return MCDisassembler::Success; 658 } 659 660 template <typename InsnType> 661 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 662 uint64_t Address, 663 const void *Decoder) { 664 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 665 // (otherwise we would have matched the ADDI instruction from the earlier 666 // ISA's instead). 667 // 668 // We have: 669 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 670 // BOVC if rs >= rt 671 // BEQZALC if rs == 0 && rt != 0 672 // BEQC if rs < rt && rs != 0 673 674 InsnType Rs = fieldFromInstruction(insn, 21, 5); 675 InsnType Rt = fieldFromInstruction(insn, 16, 5); 676 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 677 bool HasRs = false; 678 679 if (Rs >= Rt) { 680 MI.setOpcode(Mips::BOVC); 681 HasRs = true; 682 } else if (Rs != 0 && Rs < Rt) { 683 MI.setOpcode(Mips::BEQC); 684 HasRs = true; 685 } else 686 MI.setOpcode(Mips::BEQZALC); 687 688 if (HasRs) 689 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 690 Rs))); 691 692 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 693 Rt))); 694 MI.addOperand(MCOperand::createImm(Imm)); 695 696 return MCDisassembler::Success; 697 } 698 699 template <typename InsnType> 700 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 701 uint64_t Address, 702 const void *Decoder) { 703 InsnType Rt = fieldFromInstruction(insn, 21, 5); 704 InsnType Rs = fieldFromInstruction(insn, 16, 5); 705 int64_t Imm = 0; 706 707 if (Rs >= Rt) { 708 MI.setOpcode(Mips::BOVC_MMR6); 709 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 710 Rt))); 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rs))); 713 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 714 } else if (Rs != 0 && Rs < Rt) { 715 MI.setOpcode(Mips::BEQC_MMR6); 716 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 717 Rs))); 718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 719 Rt))); 720 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 721 } else { 722 MI.setOpcode(Mips::BEQZALC_MMR6); 723 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 724 Rt))); 725 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 726 } 727 728 MI.addOperand(MCOperand::createImm(Imm)); 729 730 return MCDisassembler::Success; 731 } 732 733 template <typename InsnType> 734 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 735 uint64_t Address, 736 const void *Decoder) { 737 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 738 // (otherwise we would have matched the ADDI instruction from the earlier 739 // ISA's instead). 740 // 741 // We have: 742 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 743 // BNVC if rs >= rt 744 // BNEZALC if rs == 0 && rt != 0 745 // BNEC if rs < rt && rs != 0 746 747 InsnType Rs = fieldFromInstruction(insn, 21, 5); 748 InsnType Rt = fieldFromInstruction(insn, 16, 5); 749 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 750 bool HasRs = false; 751 752 if (Rs >= Rt) { 753 MI.setOpcode(Mips::BNVC); 754 HasRs = true; 755 } else if (Rs != 0 && Rs < Rt) { 756 MI.setOpcode(Mips::BNEC); 757 HasRs = true; 758 } else 759 MI.setOpcode(Mips::BNEZALC); 760 761 if (HasRs) 762 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 763 Rs))); 764 765 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 766 Rt))); 767 MI.addOperand(MCOperand::createImm(Imm)); 768 769 return MCDisassembler::Success; 770 } 771 772 template <typename InsnType> 773 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 774 uint64_t Address, 775 const void *Decoder) { 776 InsnType Rt = fieldFromInstruction(insn, 21, 5); 777 InsnType Rs = fieldFromInstruction(insn, 16, 5); 778 int64_t Imm = 0; 779 780 if (Rs >= Rt) { 781 MI.setOpcode(Mips::BNVC_MMR6); 782 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 783 Rt))); 784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 785 Rs))); 786 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 787 } else if (Rs != 0 && Rs < Rt) { 788 MI.setOpcode(Mips::BNEC_MMR6); 789 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 790 Rs))); 791 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 792 Rt))); 793 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 794 } else { 795 MI.setOpcode(Mips::BNEZALC_MMR6); 796 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 797 Rt))); 798 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 799 } 800 801 MI.addOperand(MCOperand::createImm(Imm)); 802 803 return MCDisassembler::Success; 804 } 805 806 template <typename InsnType> 807 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 808 uint64_t Address, 809 const void *Decoder) { 810 // We have: 811 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 812 // Invalid if rt == 0 813 // BGTZC_MMR6 if rs == 0 && rt != 0 814 // BLTZC_MMR6 if rs == rt && rt != 0 815 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 816 817 InsnType Rt = fieldFromInstruction(insn, 21, 5); 818 InsnType Rs = fieldFromInstruction(insn, 16, 5); 819 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 820 bool HasRs = false; 821 822 if (Rt == 0) 823 return MCDisassembler::Fail; 824 else if (Rs == 0) 825 MI.setOpcode(Mips::BGTZC_MMR6); 826 else if (Rs == Rt) 827 MI.setOpcode(Mips::BLTZC_MMR6); 828 else { 829 MI.setOpcode(Mips::BLTC_MMR6); 830 HasRs = true; 831 } 832 833 if (HasRs) 834 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 835 Rs))); 836 837 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 838 Rt))); 839 840 MI.addOperand(MCOperand::createImm(Imm)); 841 842 return MCDisassembler::Success; 843 } 844 845 template <typename InsnType> 846 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 847 uint64_t Address, 848 const void *Decoder) { 849 // We have: 850 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 851 // Invalid if rt == 0 852 // BLEZC_MMR6 if rs == 0 && rt != 0 853 // BGEZC_MMR6 if rs == rt && rt != 0 854 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 855 856 InsnType Rt = fieldFromInstruction(insn, 21, 5); 857 InsnType Rs = fieldFromInstruction(insn, 16, 5); 858 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 859 bool HasRs = false; 860 861 if (Rt == 0) 862 return MCDisassembler::Fail; 863 else if (Rs == 0) 864 MI.setOpcode(Mips::BLEZC_MMR6); 865 else if (Rs == Rt) 866 MI.setOpcode(Mips::BGEZC_MMR6); 867 else { 868 HasRs = true; 869 MI.setOpcode(Mips::BGEC_MMR6); 870 } 871 872 if (HasRs) 873 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 874 Rs))); 875 876 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 877 Rt))); 878 879 MI.addOperand(MCOperand::createImm(Imm)); 880 881 return MCDisassembler::Success; 882 } 883 884 template <typename InsnType> 885 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 886 uint64_t Address, 887 const void *Decoder) { 888 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 889 // (otherwise we would have matched the BLEZL instruction from the earlier 890 // ISA's instead). 891 // 892 // We have: 893 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 894 // Invalid if rs == 0 895 // BLEZC if rs == 0 && rt != 0 896 // BGEZC if rs == rt && rt != 0 897 // BGEC if rs != rt && rs != 0 && rt != 0 898 899 InsnType Rs = fieldFromInstruction(insn, 21, 5); 900 InsnType Rt = fieldFromInstruction(insn, 16, 5); 901 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 902 bool HasRs = false; 903 904 if (Rt == 0) 905 return MCDisassembler::Fail; 906 else if (Rs == 0) 907 MI.setOpcode(Mips::BLEZC); 908 else if (Rs == Rt) 909 MI.setOpcode(Mips::BGEZC); 910 else { 911 HasRs = true; 912 MI.setOpcode(Mips::BGEC); 913 } 914 915 if (HasRs) 916 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 917 Rs))); 918 919 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 920 Rt))); 921 922 MI.addOperand(MCOperand::createImm(Imm)); 923 924 return MCDisassembler::Success; 925 } 926 927 template <typename InsnType> 928 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 929 uint64_t Address, 930 const void *Decoder) { 931 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 932 // (otherwise we would have matched the BGTZL instruction from the earlier 933 // ISA's instead). 934 // 935 // We have: 936 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 937 // Invalid if rs == 0 938 // BGTZC if rs == 0 && rt != 0 939 // BLTZC if rs == rt && rt != 0 940 // BLTC if rs != rt && rs != 0 && rt != 0 941 942 bool HasRs = false; 943 944 InsnType Rs = fieldFromInstruction(insn, 21, 5); 945 InsnType Rt = fieldFromInstruction(insn, 16, 5); 946 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 947 948 if (Rt == 0) 949 return MCDisassembler::Fail; 950 else if (Rs == 0) 951 MI.setOpcode(Mips::BGTZC); 952 else if (Rs == Rt) 953 MI.setOpcode(Mips::BLTZC); 954 else { 955 MI.setOpcode(Mips::BLTC); 956 HasRs = true; 957 } 958 959 if (HasRs) 960 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 961 Rs))); 962 963 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 964 Rt))); 965 966 MI.addOperand(MCOperand::createImm(Imm)); 967 968 return MCDisassembler::Success; 969 } 970 971 template <typename InsnType> 972 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 973 uint64_t Address, 974 const void *Decoder) { 975 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 976 // (otherwise we would have matched the BGTZ instruction from the earlier 977 // ISA's instead). 978 // 979 // We have: 980 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 981 // BGTZ if rt == 0 982 // BGTZALC if rs == 0 && rt != 0 983 // BLTZALC if rs != 0 && rs == rt 984 // BLTUC if rs != 0 && rs != rt 985 986 InsnType Rs = fieldFromInstruction(insn, 21, 5); 987 InsnType Rt = fieldFromInstruction(insn, 16, 5); 988 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 989 bool HasRs = false; 990 bool HasRt = false; 991 992 if (Rt == 0) { 993 MI.setOpcode(Mips::BGTZ); 994 HasRs = true; 995 } else if (Rs == 0) { 996 MI.setOpcode(Mips::BGTZALC); 997 HasRt = true; 998 } else if (Rs == Rt) { 999 MI.setOpcode(Mips::BLTZALC); 1000 HasRs = true; 1001 } else { 1002 MI.setOpcode(Mips::BLTUC); 1003 HasRs = true; 1004 HasRt = true; 1005 } 1006 1007 if (HasRs) 1008 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1009 Rs))); 1010 1011 if (HasRt) 1012 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1013 Rt))); 1014 1015 MI.addOperand(MCOperand::createImm(Imm)); 1016 1017 return MCDisassembler::Success; 1018 } 1019 1020 template <typename InsnType> 1021 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1022 uint64_t Address, 1023 const void *Decoder) { 1024 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1025 // (otherwise we would have matched the BLEZL instruction from the earlier 1026 // ISA's instead). 1027 // 1028 // We have: 1029 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1030 // Invalid if rs == 0 1031 // BLEZALC if rs == 0 && rt != 0 1032 // BGEZALC if rs == rt && rt != 0 1033 // BGEUC if rs != rt && rs != 0 && rt != 0 1034 1035 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1036 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1037 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1038 bool HasRs = false; 1039 1040 if (Rt == 0) 1041 return MCDisassembler::Fail; 1042 else if (Rs == 0) 1043 MI.setOpcode(Mips::BLEZALC); 1044 else if (Rs == Rt) 1045 MI.setOpcode(Mips::BGEZALC); 1046 else { 1047 HasRs = true; 1048 MI.setOpcode(Mips::BGEUC); 1049 } 1050 1051 if (HasRs) 1052 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1053 Rs))); 1054 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1055 Rt))); 1056 1057 MI.addOperand(MCOperand::createImm(Imm)); 1058 1059 return MCDisassembler::Success; 1060 } 1061 1062 // Override the generated disassembler to produce DEXT all the time. This is 1063 // for feature / behaviour parity with binutils. 1064 template <typename InsnType> 1065 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1066 const void *Decoder) { 1067 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1068 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1069 unsigned Size = 0; 1070 unsigned Pos = 0; 1071 1072 switch (MI.getOpcode()) { 1073 case Mips::DEXT: 1074 Pos = Lsb; 1075 Size = Msbd + 1; 1076 break; 1077 case Mips::DEXTM: 1078 Pos = Lsb; 1079 Size = Msbd + 1 + 32; 1080 break; 1081 case Mips::DEXTU: 1082 Pos = Lsb + 32; 1083 Size = Msbd + 1; 1084 break; 1085 default: 1086 llvm_unreachable("Unknown DEXT instruction!"); 1087 } 1088 1089 MI.setOpcode(Mips::DEXT); 1090 1091 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1092 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1093 1094 MI.addOperand( 1095 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1096 MI.addOperand( 1097 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1098 MI.addOperand(MCOperand::createImm(Pos)); 1099 MI.addOperand(MCOperand::createImm(Size)); 1100 1101 return MCDisassembler::Success; 1102 } 1103 1104 // Override the generated disassembler to produce DINS all the time. This is 1105 // for feature / behaviour parity with binutils. 1106 template <typename InsnType> 1107 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1108 const void *Decoder) { 1109 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1110 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1111 unsigned Size = 0; 1112 unsigned Pos = 0; 1113 1114 switch (MI.getOpcode()) { 1115 case Mips::DINS: 1116 Pos = Lsb; 1117 Size = Msbd + 1 - Pos; 1118 break; 1119 case Mips::DINSM: 1120 Pos = Lsb; 1121 Size = Msbd + 33 - Pos; 1122 break; 1123 case Mips::DINSU: 1124 Pos = Lsb + 32; 1125 // mbsd = pos + size - 33 1126 // mbsd - pos + 33 = size 1127 Size = Msbd + 33 - Pos; 1128 break; 1129 default: 1130 llvm_unreachable("Unknown DINS instruction!"); 1131 } 1132 1133 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1134 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1135 1136 MI.setOpcode(Mips::DINS); 1137 MI.addOperand( 1138 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1139 MI.addOperand( 1140 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1141 MI.addOperand(MCOperand::createImm(Pos)); 1142 MI.addOperand(MCOperand::createImm(Size)); 1143 1144 return MCDisassembler::Success; 1145 } 1146 1147 // Auto-generated decoder wouldn't add the third operand for CRC32*. 1148 template <typename InsnType> 1149 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 1150 const void *Decoder) { 1151 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1152 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1153 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1154 Rt))); 1155 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1156 Rs))); 1157 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1158 Rt))); 1159 return MCDisassembler::Success; 1160 } 1161 1162 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1163 /// according to the given endianness. 1164 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1165 uint64_t &Size, uint32_t &Insn, 1166 bool IsBigEndian) { 1167 // We want to read exactly 2 Bytes of data. 1168 if (Bytes.size() < 2) { 1169 Size = 0; 1170 return MCDisassembler::Fail; 1171 } 1172 1173 if (IsBigEndian) { 1174 Insn = (Bytes[0] << 8) | Bytes[1]; 1175 } else { 1176 Insn = (Bytes[1] << 8) | Bytes[0]; 1177 } 1178 1179 return MCDisassembler::Success; 1180 } 1181 1182 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1183 /// according to the given endianness. 1184 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1185 uint64_t &Size, uint32_t &Insn, 1186 bool IsBigEndian, bool IsMicroMips) { 1187 // We want to read exactly 4 Bytes of data. 1188 if (Bytes.size() < 4) { 1189 Size = 0; 1190 return MCDisassembler::Fail; 1191 } 1192 1193 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1194 // always precede the low 16 bits in the instruction stream (that is, they 1195 // are placed at lower addresses in the instruction stream). 1196 // 1197 // microMIPS byte ordering: 1198 // Big-endian: 0 | 1 | 2 | 3 1199 // Little-endian: 1 | 0 | 3 | 2 1200 1201 if (IsBigEndian) { 1202 // Encoded as a big-endian 32-bit word in the stream. 1203 Insn = 1204 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1205 } else { 1206 if (IsMicroMips) { 1207 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1208 (Bytes[1] << 24); 1209 } else { 1210 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1211 (Bytes[3] << 24); 1212 } 1213 } 1214 1215 return MCDisassembler::Success; 1216 } 1217 1218 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1219 ArrayRef<uint8_t> Bytes, 1220 uint64_t Address, 1221 raw_ostream &VStream, 1222 raw_ostream &CStream) const { 1223 uint32_t Insn; 1224 DecodeStatus Result; 1225 Size = 0; 1226 1227 if (IsMicroMips) { 1228 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1229 if (Result == MCDisassembler::Fail) 1230 return MCDisassembler::Fail; 1231 1232 if (hasMips32r6()) { 1233 LLVM_DEBUG( 1234 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1235 // Calling the auto-generated decoder function for microMIPS32R6 1236 // 16-bit instructions. 1237 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1238 Address, this, STI); 1239 if (Result != MCDisassembler::Fail) { 1240 Size = 2; 1241 return Result; 1242 } 1243 } 1244 1245 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1246 // Calling the auto-generated decoder function for microMIPS 16-bit 1247 // instructions. 1248 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1249 this, STI); 1250 if (Result != MCDisassembler::Fail) { 1251 Size = 2; 1252 return Result; 1253 } 1254 1255 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1256 if (Result == MCDisassembler::Fail) 1257 return MCDisassembler::Fail; 1258 1259 if (hasMips32r6()) { 1260 LLVM_DEBUG( 1261 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1262 // Calling the auto-generated decoder function. 1263 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, 1264 Address, this, STI); 1265 if (Result != MCDisassembler::Fail) { 1266 Size = 4; 1267 return Result; 1268 } 1269 } 1270 1271 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1272 // Calling the auto-generated decoder function. 1273 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1274 this, STI); 1275 if (Result != MCDisassembler::Fail) { 1276 Size = 4; 1277 return Result; 1278 } 1279 1280 if (isFP64()) { 1281 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1282 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1283 Address, this, STI); 1284 if (Result != MCDisassembler::Fail) { 1285 Size = 4; 1286 return Result; 1287 } 1288 } 1289 1290 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1291 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1292 // could form a valid instruction. The two bytes we rejected as an 1293 // instruction could have actually beeen an inline constant pool that is 1294 // unconditionally branched over. 1295 Size = 2; 1296 return MCDisassembler::Fail; 1297 } 1298 1299 // Attempt to read the instruction so that we can attempt to decode it. If 1300 // the buffer is not 4 bytes long, let the higher level logic figure out 1301 // what to do with a size of zero and MCDisassembler::Fail. 1302 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1303 if (Result == MCDisassembler::Fail) 1304 return MCDisassembler::Fail; 1305 1306 // The only instruction size for standard encoded MIPS. 1307 Size = 4; 1308 1309 if (hasCOP3()) { 1310 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1311 Result = 1312 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1313 if (Result != MCDisassembler::Fail) 1314 return Result; 1315 } 1316 1317 if (hasMips32r6() && isGP64()) { 1318 LLVM_DEBUG( 1319 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1320 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1321 Address, this, STI); 1322 if (Result != MCDisassembler::Fail) 1323 return Result; 1324 } 1325 1326 if (hasMips32r6() && isPTR64()) { 1327 LLVM_DEBUG( 1328 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1329 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1330 Address, this, STI); 1331 if (Result != MCDisassembler::Fail) 1332 return Result; 1333 } 1334 1335 if (hasMips32r6()) { 1336 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1337 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1338 Address, this, STI); 1339 if (Result != MCDisassembler::Fail) 1340 return Result; 1341 } 1342 1343 if (hasMips2() && isPTR64()) { 1344 LLVM_DEBUG( 1345 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1346 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1347 Address, this, STI); 1348 if (Result != MCDisassembler::Fail) 1349 return Result; 1350 } 1351 1352 if (hasCnMips()) { 1353 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1354 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1355 Address, this, STI); 1356 if (Result != MCDisassembler::Fail) 1357 return Result; 1358 } 1359 1360 if (isGP64()) { 1361 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1362 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1363 Address, this, STI); 1364 if (Result != MCDisassembler::Fail) 1365 return Result; 1366 } 1367 1368 if (isFP64()) { 1369 LLVM_DEBUG( 1370 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1371 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1372 Address, this, STI); 1373 if (Result != MCDisassembler::Fail) 1374 return Result; 1375 } 1376 1377 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1378 // Calling the auto-generated decoder function. 1379 Result = 1380 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1381 if (Result != MCDisassembler::Fail) 1382 return Result; 1383 1384 return MCDisassembler::Fail; 1385 } 1386 1387 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1388 unsigned RegNo, 1389 uint64_t Address, 1390 const void *Decoder) { 1391 return MCDisassembler::Fail; 1392 } 1393 1394 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1395 unsigned RegNo, 1396 uint64_t Address, 1397 const void *Decoder) { 1398 if (RegNo > 31) 1399 return MCDisassembler::Fail; 1400 1401 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1402 Inst.addOperand(MCOperand::createReg(Reg)); 1403 return MCDisassembler::Success; 1404 } 1405 1406 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1407 unsigned RegNo, 1408 uint64_t Address, 1409 const void *Decoder) { 1410 if (RegNo > 7) 1411 return MCDisassembler::Fail; 1412 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1413 Inst.addOperand(MCOperand::createReg(Reg)); 1414 return MCDisassembler::Success; 1415 } 1416 1417 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1418 unsigned RegNo, 1419 uint64_t Address, 1420 const void *Decoder) { 1421 if (RegNo > 7) 1422 return MCDisassembler::Fail; 1423 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1424 Inst.addOperand(MCOperand::createReg(Reg)); 1425 return MCDisassembler::Success; 1426 } 1427 1428 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1429 unsigned RegNo, 1430 uint64_t Address, 1431 const void *Decoder) { 1432 if (RegNo > 7) 1433 return MCDisassembler::Fail; 1434 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1435 Inst.addOperand(MCOperand::createReg(Reg)); 1436 return MCDisassembler::Success; 1437 } 1438 1439 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1440 unsigned RegNo, 1441 uint64_t Address, 1442 const void *Decoder) { 1443 if (RegNo > 31) 1444 return MCDisassembler::Fail; 1445 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1446 Inst.addOperand(MCOperand::createReg(Reg)); 1447 return MCDisassembler::Success; 1448 } 1449 1450 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1451 unsigned RegNo, 1452 uint64_t Address, 1453 const void *Decoder) { 1454 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1455 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1456 1457 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1458 } 1459 1460 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1461 unsigned RegNo, 1462 uint64_t Address, 1463 const void *Decoder) { 1464 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1465 } 1466 1467 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1468 unsigned RegNo, 1469 uint64_t Address, 1470 const void *Decoder) { 1471 if (RegNo > 31) 1472 return MCDisassembler::Fail; 1473 1474 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1475 Inst.addOperand(MCOperand::createReg(Reg)); 1476 return MCDisassembler::Success; 1477 } 1478 1479 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1480 unsigned RegNo, 1481 uint64_t Address, 1482 const void *Decoder) { 1483 if (RegNo > 31) 1484 return MCDisassembler::Fail; 1485 1486 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1487 Inst.addOperand(MCOperand::createReg(Reg)); 1488 return MCDisassembler::Success; 1489 } 1490 1491 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1492 unsigned RegNo, 1493 uint64_t Address, 1494 const void *Decoder) { 1495 if (RegNo > 31) 1496 return MCDisassembler::Fail; 1497 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1498 Inst.addOperand(MCOperand::createReg(Reg)); 1499 return MCDisassembler::Success; 1500 } 1501 1502 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1503 unsigned RegNo, 1504 uint64_t Address, 1505 const void *Decoder) { 1506 if (RegNo > 7) 1507 return MCDisassembler::Fail; 1508 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1509 Inst.addOperand(MCOperand::createReg(Reg)); 1510 return MCDisassembler::Success; 1511 } 1512 1513 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1514 uint64_t Address, 1515 const void *Decoder) { 1516 if (RegNo > 31) 1517 return MCDisassembler::Fail; 1518 1519 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1520 Inst.addOperand(MCOperand::createReg(Reg)); 1521 return MCDisassembler::Success; 1522 } 1523 1524 static DecodeStatus DecodeMem(MCInst &Inst, 1525 unsigned Insn, 1526 uint64_t Address, 1527 const void *Decoder) { 1528 int Offset = SignExtend32<16>(Insn & 0xffff); 1529 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1530 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1531 1532 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1533 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1534 1535 if (Inst.getOpcode() == Mips::SC || 1536 Inst.getOpcode() == Mips::SCD) 1537 Inst.addOperand(MCOperand::createReg(Reg)); 1538 1539 Inst.addOperand(MCOperand::createReg(Reg)); 1540 Inst.addOperand(MCOperand::createReg(Base)); 1541 Inst.addOperand(MCOperand::createImm(Offset)); 1542 1543 return MCDisassembler::Success; 1544 } 1545 1546 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1547 unsigned Insn, 1548 uint64_t Address, 1549 const void *Decoder) { 1550 int Offset = SignExtend32<9>(Insn >> 7); 1551 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1552 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1553 1554 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1555 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1556 1557 if (Inst.getOpcode() == Mips::SCE) 1558 Inst.addOperand(MCOperand::createReg(Reg)); 1559 1560 Inst.addOperand(MCOperand::createReg(Reg)); 1561 Inst.addOperand(MCOperand::createReg(Base)); 1562 Inst.addOperand(MCOperand::createImm(Offset)); 1563 1564 return MCDisassembler::Success; 1565 } 1566 1567 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1568 unsigned Insn, 1569 uint64_t Address, 1570 const void *Decoder) { 1571 int Offset = SignExtend32<16>(Insn & 0xffff); 1572 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1573 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1574 1575 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1576 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1577 1578 Inst.addOperand(MCOperand::createReg(Reg)); 1579 Inst.addOperand(MCOperand::createReg(Base)); 1580 Inst.addOperand(MCOperand::createImm(Offset)); 1581 1582 return MCDisassembler::Success; 1583 } 1584 1585 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1586 unsigned Insn, 1587 uint64_t Address, 1588 const void *Decoder) { 1589 int Offset = SignExtend32<16>(Insn & 0xffff); 1590 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1591 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1592 1593 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1594 1595 Inst.addOperand(MCOperand::createReg(Base)); 1596 Inst.addOperand(MCOperand::createImm(Offset)); 1597 Inst.addOperand(MCOperand::createImm(Hint)); 1598 1599 return MCDisassembler::Success; 1600 } 1601 1602 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1603 unsigned Insn, 1604 uint64_t Address, 1605 const void *Decoder) { 1606 int Offset = SignExtend32<12>(Insn & 0xfff); 1607 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1608 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1609 1610 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1611 1612 Inst.addOperand(MCOperand::createReg(Base)); 1613 Inst.addOperand(MCOperand::createImm(Offset)); 1614 Inst.addOperand(MCOperand::createImm(Hint)); 1615 1616 return MCDisassembler::Success; 1617 } 1618 1619 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1620 unsigned Insn, 1621 uint64_t Address, 1622 const void *Decoder) { 1623 int Offset = SignExtend32<9>(Insn & 0x1ff); 1624 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1625 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1626 1627 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1628 1629 Inst.addOperand(MCOperand::createReg(Base)); 1630 Inst.addOperand(MCOperand::createImm(Offset)); 1631 Inst.addOperand(MCOperand::createImm(Hint)); 1632 1633 return MCDisassembler::Success; 1634 } 1635 1636 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1637 unsigned Insn, 1638 uint64_t Address, 1639 const void *Decoder) { 1640 int Offset = SignExtend32<9>(Insn >> 7); 1641 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1642 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1643 1644 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1645 1646 Inst.addOperand(MCOperand::createReg(Base)); 1647 Inst.addOperand(MCOperand::createImm(Offset)); 1648 Inst.addOperand(MCOperand::createImm(Hint)); 1649 1650 return MCDisassembler::Success; 1651 } 1652 1653 static DecodeStatus DecodeSyncI(MCInst &Inst, 1654 unsigned Insn, 1655 uint64_t Address, 1656 const void *Decoder) { 1657 int Offset = SignExtend32<16>(Insn & 0xffff); 1658 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1659 1660 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1661 1662 Inst.addOperand(MCOperand::createReg(Base)); 1663 Inst.addOperand(MCOperand::createImm(Offset)); 1664 1665 return MCDisassembler::Success; 1666 } 1667 1668 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 1669 uint64_t Address, const void *Decoder) { 1670 int Offset = SignExtend32<16>(Insn & 0xffff); 1671 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1672 1673 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1674 1675 Inst.addOperand(MCOperand::createReg(Base)); 1676 Inst.addOperand(MCOperand::createImm(Offset)); 1677 1678 return MCDisassembler::Success; 1679 } 1680 1681 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1682 unsigned Insn, 1683 uint64_t Address, 1684 const void *Decoder) { 1685 int Immediate = SignExtend32<16>(Insn & 0xffff); 1686 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1687 1688 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1689 1690 Inst.addOperand(MCOperand::createReg(Base)); 1691 Inst.addOperand(MCOperand::createImm(Immediate)); 1692 1693 return MCDisassembler::Success; 1694 } 1695 1696 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1697 uint64_t Address, const void *Decoder) { 1698 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1699 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1700 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1701 1702 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1703 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1704 1705 Inst.addOperand(MCOperand::createReg(Reg)); 1706 Inst.addOperand(MCOperand::createReg(Base)); 1707 1708 // The immediate field of an LD/ST instruction is scaled which means it must 1709 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1710 // data format. 1711 // .b - 1 byte 1712 // .h - 2 bytes 1713 // .w - 4 bytes 1714 // .d - 8 bytes 1715 switch(Inst.getOpcode()) 1716 { 1717 default: 1718 assert(false && "Unexpected instruction"); 1719 return MCDisassembler::Fail; 1720 break; 1721 case Mips::LD_B: 1722 case Mips::ST_B: 1723 Inst.addOperand(MCOperand::createImm(Offset)); 1724 break; 1725 case Mips::LD_H: 1726 case Mips::ST_H: 1727 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1728 break; 1729 case Mips::LD_W: 1730 case Mips::ST_W: 1731 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1732 break; 1733 case Mips::LD_D: 1734 case Mips::ST_D: 1735 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1736 break; 1737 } 1738 1739 return MCDisassembler::Success; 1740 } 1741 1742 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1743 unsigned Insn, 1744 uint64_t Address, 1745 const void *Decoder) { 1746 unsigned Offset = Insn & 0xf; 1747 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1748 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1749 1750 switch (Inst.getOpcode()) { 1751 case Mips::LBU16_MM: 1752 case Mips::LHU16_MM: 1753 case Mips::LW16_MM: 1754 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1755 == MCDisassembler::Fail) 1756 return MCDisassembler::Fail; 1757 break; 1758 case Mips::SB16_MM: 1759 case Mips::SB16_MMR6: 1760 case Mips::SH16_MM: 1761 case Mips::SH16_MMR6: 1762 case Mips::SW16_MM: 1763 case Mips::SW16_MMR6: 1764 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1765 == MCDisassembler::Fail) 1766 return MCDisassembler::Fail; 1767 break; 1768 } 1769 1770 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1771 == MCDisassembler::Fail) 1772 return MCDisassembler::Fail; 1773 1774 switch (Inst.getOpcode()) { 1775 case Mips::LBU16_MM: 1776 if (Offset == 0xf) 1777 Inst.addOperand(MCOperand::createImm(-1)); 1778 else 1779 Inst.addOperand(MCOperand::createImm(Offset)); 1780 break; 1781 case Mips::SB16_MM: 1782 case Mips::SB16_MMR6: 1783 Inst.addOperand(MCOperand::createImm(Offset)); 1784 break; 1785 case Mips::LHU16_MM: 1786 case Mips::SH16_MM: 1787 case Mips::SH16_MMR6: 1788 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1789 break; 1790 case Mips::LW16_MM: 1791 case Mips::SW16_MM: 1792 case Mips::SW16_MMR6: 1793 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1794 break; 1795 } 1796 1797 return MCDisassembler::Success; 1798 } 1799 1800 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1801 unsigned Insn, 1802 uint64_t Address, 1803 const void *Decoder) { 1804 unsigned Offset = Insn & 0x1F; 1805 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1806 1807 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1808 1809 Inst.addOperand(MCOperand::createReg(Reg)); 1810 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1811 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1812 1813 return MCDisassembler::Success; 1814 } 1815 1816 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1817 unsigned Insn, 1818 uint64_t Address, 1819 const void *Decoder) { 1820 unsigned Offset = Insn & 0x7F; 1821 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1822 1823 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1824 1825 Inst.addOperand(MCOperand::createReg(Reg)); 1826 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1827 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1828 1829 return MCDisassembler::Success; 1830 } 1831 1832 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1833 unsigned Insn, 1834 uint64_t Address, 1835 const void *Decoder) { 1836 int Offset; 1837 switch (Inst.getOpcode()) { 1838 case Mips::LWM16_MMR6: 1839 case Mips::SWM16_MMR6: 1840 Offset = fieldFromInstruction(Insn, 4, 4); 1841 break; 1842 default: 1843 Offset = SignExtend32<4>(Insn & 0xf); 1844 break; 1845 } 1846 1847 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1848 == MCDisassembler::Fail) 1849 return MCDisassembler::Fail; 1850 1851 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1852 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1853 1854 return MCDisassembler::Success; 1855 } 1856 1857 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1858 unsigned Insn, 1859 uint64_t Address, 1860 const void *Decoder) { 1861 int Offset = SignExtend32<9>(Insn & 0x1ff); 1862 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1863 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1864 1865 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1866 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1867 1868 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) 1869 Inst.addOperand(MCOperand::createReg(Reg)); 1870 1871 Inst.addOperand(MCOperand::createReg(Reg)); 1872 Inst.addOperand(MCOperand::createReg(Base)); 1873 Inst.addOperand(MCOperand::createImm(Offset)); 1874 1875 return MCDisassembler::Success; 1876 } 1877 1878 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1879 unsigned Insn, 1880 uint64_t Address, 1881 const void *Decoder) { 1882 int Offset = SignExtend32<12>(Insn & 0x0fff); 1883 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1884 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1885 1886 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1887 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1888 1889 switch (Inst.getOpcode()) { 1890 case Mips::SWM32_MM: 1891 case Mips::LWM32_MM: 1892 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1893 == MCDisassembler::Fail) 1894 return MCDisassembler::Fail; 1895 Inst.addOperand(MCOperand::createReg(Base)); 1896 Inst.addOperand(MCOperand::createImm(Offset)); 1897 break; 1898 case Mips::SC_MM: 1899 Inst.addOperand(MCOperand::createReg(Reg)); 1900 LLVM_FALLTHROUGH; 1901 default: 1902 Inst.addOperand(MCOperand::createReg(Reg)); 1903 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1904 Inst.addOperand(MCOperand::createReg(Reg+1)); 1905 1906 Inst.addOperand(MCOperand::createReg(Base)); 1907 Inst.addOperand(MCOperand::createImm(Offset)); 1908 } 1909 1910 return MCDisassembler::Success; 1911 } 1912 1913 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1914 unsigned Insn, 1915 uint64_t Address, 1916 const void *Decoder) { 1917 int Offset = SignExtend32<16>(Insn & 0xffff); 1918 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1919 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1920 1921 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1922 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1923 1924 Inst.addOperand(MCOperand::createReg(Reg)); 1925 Inst.addOperand(MCOperand::createReg(Base)); 1926 Inst.addOperand(MCOperand::createImm(Offset)); 1927 1928 return MCDisassembler::Success; 1929 } 1930 1931 static DecodeStatus DecodeFMem(MCInst &Inst, 1932 unsigned Insn, 1933 uint64_t Address, 1934 const void *Decoder) { 1935 int Offset = SignExtend32<16>(Insn & 0xffff); 1936 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1937 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1938 1939 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1940 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1941 1942 Inst.addOperand(MCOperand::createReg(Reg)); 1943 Inst.addOperand(MCOperand::createReg(Base)); 1944 Inst.addOperand(MCOperand::createImm(Offset)); 1945 1946 return MCDisassembler::Success; 1947 } 1948 1949 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1950 uint64_t Address, const void *Decoder) { 1951 // This function is the same as DecodeFMem but with the Reg and Base fields 1952 // swapped according to microMIPS spec. 1953 int Offset = SignExtend32<16>(Insn & 0xffff); 1954 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1955 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1956 1957 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1958 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1959 1960 Inst.addOperand(MCOperand::createReg(Reg)); 1961 Inst.addOperand(MCOperand::createReg(Base)); 1962 Inst.addOperand(MCOperand::createImm(Offset)); 1963 1964 return MCDisassembler::Success; 1965 } 1966 1967 static DecodeStatus DecodeFMem2(MCInst &Inst, 1968 unsigned Insn, 1969 uint64_t Address, 1970 const void *Decoder) { 1971 int Offset = SignExtend32<16>(Insn & 0xffff); 1972 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1973 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1974 1975 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1976 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1977 1978 Inst.addOperand(MCOperand::createReg(Reg)); 1979 Inst.addOperand(MCOperand::createReg(Base)); 1980 Inst.addOperand(MCOperand::createImm(Offset)); 1981 1982 return MCDisassembler::Success; 1983 } 1984 1985 static DecodeStatus DecodeFMem3(MCInst &Inst, 1986 unsigned Insn, 1987 uint64_t Address, 1988 const void *Decoder) { 1989 int Offset = SignExtend32<16>(Insn & 0xffff); 1990 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1991 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1992 1993 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1994 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1995 1996 Inst.addOperand(MCOperand::createReg(Reg)); 1997 Inst.addOperand(MCOperand::createReg(Base)); 1998 Inst.addOperand(MCOperand::createImm(Offset)); 1999 2000 return MCDisassembler::Success; 2001 } 2002 2003 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 2004 unsigned Insn, 2005 uint64_t Address, 2006 const void *Decoder) { 2007 int Offset = SignExtend32<11>(Insn & 0x07ff); 2008 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2009 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2010 2011 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2012 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2013 2014 Inst.addOperand(MCOperand::createReg(Reg)); 2015 Inst.addOperand(MCOperand::createReg(Base)); 2016 Inst.addOperand(MCOperand::createImm(Offset)); 2017 2018 return MCDisassembler::Success; 2019 } 2020 2021 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2022 uint64_t Address, const void *Decoder) { 2023 int Offset = SignExtend32<11>(Insn & 0x07ff); 2024 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2025 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2026 2027 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2028 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2029 2030 Inst.addOperand(MCOperand::createReg(Reg)); 2031 Inst.addOperand(MCOperand::createReg(Base)); 2032 Inst.addOperand(MCOperand::createImm(Offset)); 2033 2034 return MCDisassembler::Success; 2035 } 2036 2037 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2038 unsigned Insn, 2039 uint64_t Address, 2040 const void *Decoder) { 2041 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2042 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2043 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2044 2045 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2046 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2047 2048 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2049 Inst.addOperand(MCOperand::createReg(Rt)); 2050 } 2051 2052 Inst.addOperand(MCOperand::createReg(Rt)); 2053 Inst.addOperand(MCOperand::createReg(Base)); 2054 Inst.addOperand(MCOperand::createImm(Offset)); 2055 2056 return MCDisassembler::Success; 2057 } 2058 2059 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2060 unsigned RegNo, 2061 uint64_t Address, 2062 const void *Decoder) { 2063 // Currently only hardware register 29 is supported. 2064 if (RegNo != 29) 2065 return MCDisassembler::Fail; 2066 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2067 return MCDisassembler::Success; 2068 } 2069 2070 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2071 unsigned RegNo, 2072 uint64_t Address, 2073 const void *Decoder) { 2074 if (RegNo > 30 || RegNo %2) 2075 return MCDisassembler::Fail; 2076 2077 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2078 Inst.addOperand(MCOperand::createReg(Reg)); 2079 return MCDisassembler::Success; 2080 } 2081 2082 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2083 unsigned RegNo, 2084 uint64_t Address, 2085 const void *Decoder) { 2086 if (RegNo >= 4) 2087 return MCDisassembler::Fail; 2088 2089 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2090 Inst.addOperand(MCOperand::createReg(Reg)); 2091 return MCDisassembler::Success; 2092 } 2093 2094 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2095 unsigned RegNo, 2096 uint64_t Address, 2097 const void *Decoder) { 2098 if (RegNo >= 4) 2099 return MCDisassembler::Fail; 2100 2101 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2102 Inst.addOperand(MCOperand::createReg(Reg)); 2103 return MCDisassembler::Success; 2104 } 2105 2106 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2107 unsigned RegNo, 2108 uint64_t Address, 2109 const void *Decoder) { 2110 if (RegNo >= 4) 2111 return MCDisassembler::Fail; 2112 2113 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2114 Inst.addOperand(MCOperand::createReg(Reg)); 2115 return MCDisassembler::Success; 2116 } 2117 2118 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2119 unsigned RegNo, 2120 uint64_t Address, 2121 const void *Decoder) { 2122 if (RegNo > 31) 2123 return MCDisassembler::Fail; 2124 2125 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2126 Inst.addOperand(MCOperand::createReg(Reg)); 2127 return MCDisassembler::Success; 2128 } 2129 2130 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2131 unsigned RegNo, 2132 uint64_t Address, 2133 const void *Decoder) { 2134 if (RegNo > 31) 2135 return MCDisassembler::Fail; 2136 2137 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2138 Inst.addOperand(MCOperand::createReg(Reg)); 2139 return MCDisassembler::Success; 2140 } 2141 2142 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2143 unsigned RegNo, 2144 uint64_t Address, 2145 const void *Decoder) { 2146 if (RegNo > 31) 2147 return MCDisassembler::Fail; 2148 2149 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2150 Inst.addOperand(MCOperand::createReg(Reg)); 2151 return MCDisassembler::Success; 2152 } 2153 2154 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2155 unsigned RegNo, 2156 uint64_t Address, 2157 const void *Decoder) { 2158 if (RegNo > 31) 2159 return MCDisassembler::Fail; 2160 2161 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2162 Inst.addOperand(MCOperand::createReg(Reg)); 2163 return MCDisassembler::Success; 2164 } 2165 2166 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2167 unsigned RegNo, 2168 uint64_t Address, 2169 const void *Decoder) { 2170 if (RegNo > 7) 2171 return MCDisassembler::Fail; 2172 2173 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2174 Inst.addOperand(MCOperand::createReg(Reg)); 2175 return MCDisassembler::Success; 2176 } 2177 2178 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2179 unsigned RegNo, 2180 uint64_t Address, 2181 const void *Decoder) { 2182 if (RegNo > 31) 2183 return MCDisassembler::Fail; 2184 2185 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2186 Inst.addOperand(MCOperand::createReg(Reg)); 2187 return MCDisassembler::Success; 2188 } 2189 2190 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2191 unsigned RegNo, 2192 uint64_t Address, 2193 const void *Decoder) { 2194 if (RegNo > 31) 2195 return MCDisassembler::Fail; 2196 2197 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2198 Inst.addOperand(MCOperand::createReg(Reg)); 2199 return MCDisassembler::Success; 2200 } 2201 2202 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2203 unsigned Offset, 2204 uint64_t Address, 2205 const void *Decoder) { 2206 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2207 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2208 return MCDisassembler::Success; 2209 } 2210 2211 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2212 unsigned Offset, 2213 uint64_t Address, 2214 const void *Decoder) { 2215 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2216 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2217 return MCDisassembler::Success; 2218 } 2219 2220 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2221 unsigned Insn, 2222 uint64_t Address, 2223 const void *Decoder) { 2224 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2225 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2226 return MCDisassembler::Success; 2227 } 2228 2229 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2230 unsigned Offset, 2231 uint64_t Address, 2232 const void *Decoder) { 2233 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2234 2235 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2236 return MCDisassembler::Success; 2237 } 2238 2239 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2240 unsigned Offset, 2241 uint64_t Address, 2242 const void *Decoder) { 2243 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2244 2245 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2246 return MCDisassembler::Success; 2247 } 2248 2249 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2250 unsigned Offset, 2251 uint64_t Address, 2252 const void *Decoder) { 2253 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2254 2255 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2256 return MCDisassembler::Success; 2257 } 2258 2259 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2260 unsigned Offset, 2261 uint64_t Address, 2262 const void *Decoder) { 2263 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2264 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2265 return MCDisassembler::Success; 2266 } 2267 2268 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2269 unsigned Offset, 2270 uint64_t Address, 2271 const void *Decoder) { 2272 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2273 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2274 return MCDisassembler::Success; 2275 } 2276 2277 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2278 unsigned Offset, 2279 uint64_t Address, 2280 const void *Decoder) { 2281 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2282 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2283 return MCDisassembler::Success; 2284 } 2285 2286 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2287 unsigned Offset, 2288 uint64_t Address, 2289 const void *Decoder) { 2290 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2291 2292 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2293 return MCDisassembler::Success; 2294 } 2295 2296 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2297 unsigned Insn, 2298 uint64_t Address, 2299 const void *Decoder) { 2300 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2301 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2302 return MCDisassembler::Success; 2303 } 2304 2305 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 2306 unsigned Insn, 2307 uint64_t Address, 2308 const void *Decoder) { 2309 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2310 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2311 return MCDisassembler::Success; 2312 } 2313 2314 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2315 unsigned Value, 2316 uint64_t Address, 2317 const void *Decoder) { 2318 if (Value == 0) 2319 Inst.addOperand(MCOperand::createImm(1)); 2320 else if (Value == 0x7) 2321 Inst.addOperand(MCOperand::createImm(-1)); 2322 else 2323 Inst.addOperand(MCOperand::createImm(Value << 2)); 2324 return MCDisassembler::Success; 2325 } 2326 2327 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2328 unsigned Value, 2329 uint64_t Address, 2330 const void *Decoder) { 2331 if (Value == 0x7F) 2332 Inst.addOperand(MCOperand::createImm(-1)); 2333 else 2334 Inst.addOperand(MCOperand::createImm(Value)); 2335 return MCDisassembler::Success; 2336 } 2337 2338 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2339 unsigned Value, 2340 uint64_t Address, 2341 const void *Decoder) { 2342 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2343 return MCDisassembler::Success; 2344 } 2345 2346 template <unsigned Bits, int Offset, int Scale> 2347 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2348 uint64_t Address, 2349 const void *Decoder) { 2350 Value &= ((1 << Bits) - 1); 2351 Value *= Scale; 2352 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2353 return MCDisassembler::Success; 2354 } 2355 2356 template <unsigned Bits, int Offset, int ScaleBy> 2357 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2358 uint64_t Address, 2359 const void *Decoder) { 2360 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2361 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2362 return MCDisassembler::Success; 2363 } 2364 2365 static DecodeStatus DecodeInsSize(MCInst &Inst, 2366 unsigned Insn, 2367 uint64_t Address, 2368 const void *Decoder) { 2369 // First we need to grab the pos(lsb) from MCInst. 2370 // This function only handles the 32 bit variants of ins, as dins 2371 // variants are handled differently. 2372 int Pos = Inst.getOperand(2).getImm(); 2373 int Size = (int) Insn - Pos + 1; 2374 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2375 return MCDisassembler::Success; 2376 } 2377 2378 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2379 uint64_t Address, const void *Decoder) { 2380 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2381 return MCDisassembler::Success; 2382 } 2383 2384 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2385 uint64_t Address, const void *Decoder) { 2386 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2387 return MCDisassembler::Success; 2388 } 2389 2390 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2391 uint64_t Address, const void *Decoder) { 2392 int32_t DecodedValue; 2393 switch (Insn) { 2394 case 0: DecodedValue = 256; break; 2395 case 1: DecodedValue = 257; break; 2396 case 510: DecodedValue = -258; break; 2397 case 511: DecodedValue = -257; break; 2398 default: DecodedValue = SignExtend32<9>(Insn); break; 2399 } 2400 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2401 return MCDisassembler::Success; 2402 } 2403 2404 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2405 uint64_t Address, const void *Decoder) { 2406 // Insn must be >= 0, since it is unsigned that condition is always true. 2407 assert(Insn < 16); 2408 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2409 255, 32768, 65535}; 2410 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2411 return MCDisassembler::Success; 2412 } 2413 2414 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2415 unsigned Insn, 2416 uint64_t Address, 2417 const void *Decoder) { 2418 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2419 Mips::S6, Mips::S7, Mips::FP}; 2420 unsigned RegNum; 2421 2422 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2423 2424 // Empty register lists are not allowed. 2425 if (RegLst == 0) 2426 return MCDisassembler::Fail; 2427 2428 RegNum = RegLst & 0xf; 2429 2430 // RegLst values 10-15, and 26-31 are reserved. 2431 if (RegNum > 9) 2432 return MCDisassembler::Fail; 2433 2434 for (unsigned i = 0; i < RegNum; i++) 2435 Inst.addOperand(MCOperand::createReg(Regs[i])); 2436 2437 if (RegLst & 0x10) 2438 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2439 2440 return MCDisassembler::Success; 2441 } 2442 2443 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2444 uint64_t Address, 2445 const void *Decoder) { 2446 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2447 unsigned RegLst; 2448 switch(Inst.getOpcode()) { 2449 default: 2450 RegLst = fieldFromInstruction(Insn, 4, 2); 2451 break; 2452 case Mips::LWM16_MMR6: 2453 case Mips::SWM16_MMR6: 2454 RegLst = fieldFromInstruction(Insn, 8, 2); 2455 break; 2456 } 2457 unsigned RegNum = RegLst & 0x3; 2458 2459 for (unsigned i = 0; i <= RegNum; i++) 2460 Inst.addOperand(MCOperand::createReg(Regs[i])); 2461 2462 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2463 2464 return MCDisassembler::Success; 2465 } 2466 2467 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 2468 uint64_t Address, 2469 const void *Decoder) { 2470 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2471 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == 2472 MCDisassembler::Fail) 2473 return MCDisassembler::Fail; 2474 2475 unsigned RegRs; 2476 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) 2477 RegRs = fieldFromInstruction(Insn, 0, 2) | 2478 (fieldFromInstruction(Insn, 3, 1) << 2); 2479 else 2480 RegRs = fieldFromInstruction(Insn, 1, 3); 2481 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == 2482 MCDisassembler::Fail) 2483 return MCDisassembler::Fail; 2484 2485 unsigned RegRt = fieldFromInstruction(Insn, 4, 3); 2486 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == 2487 MCDisassembler::Fail) 2488 return MCDisassembler::Fail; 2489 2490 return MCDisassembler::Success; 2491 } 2492 2493 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2494 uint64_t Address, const void *Decoder) { 2495 switch (RegPair) { 2496 default: 2497 return MCDisassembler::Fail; 2498 case 0: 2499 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2500 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2501 break; 2502 case 1: 2503 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2504 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2505 break; 2506 case 2: 2507 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2508 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2509 break; 2510 case 3: 2511 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2512 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2513 break; 2514 case 4: 2515 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2516 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2517 break; 2518 case 5: 2519 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2520 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2521 break; 2522 case 6: 2523 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2524 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2525 break; 2526 case 7: 2527 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2528 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2529 break; 2530 } 2531 2532 return MCDisassembler::Success; 2533 } 2534 2535 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2536 uint64_t Address, const void *Decoder) { 2537 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2538 return MCDisassembler::Success; 2539 } 2540 2541 template <typename InsnType> 2542 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2543 uint64_t Address, 2544 const void *Decoder) { 2545 // We have: 2546 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2547 // Invalid if rt == 0 2548 // BGTZALC_MMR6 if rs == 0 && rt != 0 2549 // BLTZALC_MMR6 if rs != 0 && rs == rt 2550 // BLTUC_MMR6 if rs != 0 && rs != rt 2551 2552 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2553 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2554 InsnType Imm = 0; 2555 bool HasRs = false; 2556 bool HasRt = false; 2557 2558 if (Rt == 0) 2559 return MCDisassembler::Fail; 2560 else if (Rs == 0) { 2561 MI.setOpcode(Mips::BGTZALC_MMR6); 2562 HasRt = true; 2563 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2564 } 2565 else if (Rs == Rt) { 2566 MI.setOpcode(Mips::BLTZALC_MMR6); 2567 HasRs = true; 2568 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2569 } 2570 else { 2571 MI.setOpcode(Mips::BLTUC_MMR6); 2572 HasRs = true; 2573 HasRt = true; 2574 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2575 } 2576 2577 if (HasRs) 2578 MI.addOperand( 2579 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2580 2581 if (HasRt) 2582 MI.addOperand( 2583 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2584 2585 MI.addOperand(MCOperand::createImm(Imm)); 2586 2587 return MCDisassembler::Success; 2588 } 2589 2590 template <typename InsnType> 2591 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2592 uint64_t Address, 2593 const void *Decoder) { 2594 // We have: 2595 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2596 // Invalid if rt == 0 2597 // BLEZALC_MMR6 if rs == 0 && rt != 0 2598 // BGEZALC_MMR6 if rs == rt && rt != 0 2599 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2600 2601 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2602 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2603 InsnType Imm = 0; 2604 bool HasRs = false; 2605 2606 if (Rt == 0) 2607 return MCDisassembler::Fail; 2608 else if (Rs == 0) { 2609 MI.setOpcode(Mips::BLEZALC_MMR6); 2610 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2611 } 2612 else if (Rs == Rt) { 2613 MI.setOpcode(Mips::BGEZALC_MMR6); 2614 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2615 } 2616 else { 2617 HasRs = true; 2618 MI.setOpcode(Mips::BGEUC_MMR6); 2619 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2620 } 2621 2622 if (HasRs) 2623 MI.addOperand( 2624 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2625 MI.addOperand( 2626 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2627 2628 MI.addOperand(MCOperand::createImm(Imm)); 2629 2630 return MCDisassembler::Success; 2631 } 2632