1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 48 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 49 50 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 51 52 bool hasCOP3() const { 53 // Only present in MIPS-I and MIPS-II 54 return !hasMips32() && !hasMips3(); 55 } 56 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &VStream, 60 raw_ostream &CStream) const override; 61 }; 62 63 } // end anonymous namespace 64 65 // Forward declare these because the autogenerated code will reference them. 66 // Definitions are further down. 67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 68 unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 73 unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 78 unsigned RegNo, 79 uint64_t Address, 80 const void *Decoder); 81 82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 83 unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 93 unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 98 unsigned Insn, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 132 unsigned Insn, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 142 unsigned RegNo, 143 uint64_t Address, 144 const void *Decoder); 145 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 147 unsigned RegNo, 148 uint64_t Address, 149 const void *Decoder); 150 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 152 unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 157 unsigned RegNo, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 192 unsigned Offset, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 202 unsigned Offset, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 207 unsigned Offset, 208 uint64_t Address, 209 const void *Decoder); 210 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 212 // shifted left by 1 bit. 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 214 unsigned Offset, 215 uint64_t Address, 216 const void *Decoder); 217 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 219 // shifted left by 1 bit. 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 235 unsigned Insn, 236 uint64_t Address, 237 const void *Decoder); 238 239 static DecodeStatus DecodeMem(MCInst &Inst, 240 unsigned Insn, 241 uint64_t Address, 242 const void *Decoder); 243 244 static DecodeStatus DecodeMemEVA(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 249 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 250 unsigned Insn, 251 uint64_t Address, 252 const void *Decoder); 253 254 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 255 unsigned Insn, 256 uint64_t Address, 257 const void *Decoder); 258 259 static DecodeStatus DecodeCacheOp(MCInst &Inst, 260 unsigned Insn, 261 uint64_t Address, 262 const void *Decoder); 263 264 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 265 unsigned Insn, 266 uint64_t Address, 267 const void *Decoder); 268 269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 270 unsigned Insn, 271 uint64_t Address, 272 const void *Decoder); 273 274 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 275 unsigned Insn, 276 uint64_t Address, 277 const void *Decoder); 278 279 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 280 unsigned Insn, 281 uint64_t Address, 282 const void *Decoder); 283 284 static DecodeStatus DecodeSyncI(MCInst &Inst, 285 unsigned Insn, 286 uint64_t Address, 287 const void *Decoder); 288 289 static DecodeStatus DecodeSynciR6(MCInst &Inst, 290 unsigned Insn, 291 uint64_t Address, 292 const void *Decoder); 293 294 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 297 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 313 unsigned Insn, 314 uint64_t Address, 315 const void *Decoder); 316 317 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 318 unsigned Insn, 319 uint64_t Address, 320 const void *Decoder); 321 322 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 323 unsigned Insn, 324 uint64_t Address, 325 const void *Decoder); 326 327 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 328 unsigned Insn, 329 uint64_t Address, 330 const void *Decoder); 331 332 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 333 uint64_t Address, 334 const void *Decoder); 335 336 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 341 uint64_t Address, 342 const void *Decoder); 343 344 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 349 unsigned Insn, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 354 unsigned Value, 355 uint64_t Address, 356 const void *Decoder); 357 358 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 359 unsigned Value, 360 uint64_t Address, 361 const void *Decoder); 362 363 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 364 unsigned Value, 365 uint64_t Address, 366 const void *Decoder); 367 368 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 369 unsigned Value, 370 uint64_t Address, 371 const void *Decoder); 372 373 static DecodeStatus DecodeSimm4(MCInst &Inst, 374 unsigned Value, 375 uint64_t Address, 376 const void *Decoder); 377 378 static DecodeStatus DecodeSimm16(MCInst &Inst, 379 unsigned Insn, 380 uint64_t Address, 381 const void *Decoder); 382 383 template <unsigned Bits, int Offset> 384 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 385 uint64_t Address, const void *Decoder); 386 387 static DecodeStatus DecodeInsSize(MCInst &Inst, 388 unsigned Insn, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodeExtSize(MCInst &Inst, 393 unsigned Insn, 394 uint64_t Address, 395 const void *Decoder); 396 397 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 398 uint64_t Address, const void *Decoder); 399 400 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 401 uint64_t Address, const void *Decoder); 402 403 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 404 uint64_t Address, const void *Decoder); 405 406 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 407 uint64_t Address, const void *Decoder); 408 409 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 410 uint64_t Address, const void *Decoder); 411 412 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 413 uint64_t Address, const void *Decoder); 414 415 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 416 /// handle. 417 template <typename InsnType> 418 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 419 const void *Decoder); 420 421 template <typename InsnType> 422 static DecodeStatus 423 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 424 const void *Decoder); 425 426 template <typename InsnType> 427 static DecodeStatus 428 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 429 const void *Decoder); 430 431 template <typename InsnType> 432 static DecodeStatus 433 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 434 const void *Decoder); 435 436 template <typename InsnType> 437 static DecodeStatus 438 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 439 const void *Decoder); 440 441 template <typename InsnType> 442 static DecodeStatus 443 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 444 const void *Decoder); 445 446 template <typename InsnType> 447 static DecodeStatus 448 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 449 const void *Decoder); 450 451 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 452 uint64_t Address, 453 const void *Decoder); 454 455 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 456 uint64_t Address, 457 const void *Decoder); 458 459 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 460 uint64_t Address, 461 const void *Decoder); 462 463 namespace llvm { 464 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 465 TheMips64elTarget; 466 } 467 468 static MCDisassembler *createMipsDisassembler( 469 const Target &T, 470 const MCSubtargetInfo &STI, 471 MCContext &Ctx) { 472 return new MipsDisassembler(STI, Ctx, true); 473 } 474 475 static MCDisassembler *createMipselDisassembler( 476 const Target &T, 477 const MCSubtargetInfo &STI, 478 MCContext &Ctx) { 479 return new MipsDisassembler(STI, Ctx, false); 480 } 481 482 extern "C" void LLVMInitializeMipsDisassembler() { 483 // Register the disassembler. 484 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 485 createMipsDisassembler); 486 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 487 createMipselDisassembler); 488 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 489 createMipsDisassembler); 490 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 491 createMipselDisassembler); 492 } 493 494 #include "MipsGenDisassemblerTables.inc" 495 496 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 497 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 498 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 499 return *(RegInfo->getRegClass(RC).begin() + RegNo); 500 } 501 502 template <typename InsnType> 503 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 504 const void *Decoder) { 505 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 506 // The size of the n field depends on the element size 507 // The register class also depends on this. 508 InsnType tmp = fieldFromInstruction(insn, 17, 5); 509 unsigned NSize = 0; 510 DecodeFN RegDecoder = nullptr; 511 if ((tmp & 0x18) == 0x00) { // INSVE_B 512 NSize = 4; 513 RegDecoder = DecodeMSA128BRegisterClass; 514 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 515 NSize = 3; 516 RegDecoder = DecodeMSA128HRegisterClass; 517 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 518 NSize = 2; 519 RegDecoder = DecodeMSA128WRegisterClass; 520 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 521 NSize = 1; 522 RegDecoder = DecodeMSA128DRegisterClass; 523 } else 524 llvm_unreachable("Invalid encoding"); 525 526 assert(NSize != 0 && RegDecoder != nullptr); 527 528 // $wd 529 tmp = fieldFromInstruction(insn, 6, 5); 530 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 531 return MCDisassembler::Fail; 532 // $wd_in 533 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 534 return MCDisassembler::Fail; 535 // $n 536 tmp = fieldFromInstruction(insn, 16, NSize); 537 MI.addOperand(MCOperand::createImm(tmp)); 538 // $ws 539 tmp = fieldFromInstruction(insn, 11, 5); 540 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 541 return MCDisassembler::Fail; 542 // $n2 543 MI.addOperand(MCOperand::createImm(0)); 544 545 return MCDisassembler::Success; 546 } 547 548 template <typename InsnType> 549 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 550 uint64_t Address, 551 const void *Decoder) { 552 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 553 // (otherwise we would have matched the ADDI instruction from the earlier 554 // ISA's instead). 555 // 556 // We have: 557 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 558 // BOVC if rs >= rt 559 // BEQZALC if rs == 0 && rt != 0 560 // BEQC if rs < rt && rs != 0 561 562 InsnType Rs = fieldFromInstruction(insn, 21, 5); 563 InsnType Rt = fieldFromInstruction(insn, 16, 5); 564 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 565 bool HasRs = false; 566 567 if (Rs >= Rt) { 568 MI.setOpcode(Mips::BOVC); 569 HasRs = true; 570 } else if (Rs != 0 && Rs < Rt) { 571 MI.setOpcode(Mips::BEQC); 572 HasRs = true; 573 } else 574 MI.setOpcode(Mips::BEQZALC); 575 576 if (HasRs) 577 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 578 Rs))); 579 580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 581 Rt))); 582 MI.addOperand(MCOperand::createImm(Imm)); 583 584 return MCDisassembler::Success; 585 } 586 587 template <typename InsnType> 588 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 589 uint64_t Address, 590 const void *Decoder) { 591 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 592 // (otherwise we would have matched the ADDI instruction from the earlier 593 // ISA's instead). 594 // 595 // We have: 596 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 597 // BNVC if rs >= rt 598 // BNEZALC if rs == 0 && rt != 0 599 // BNEC if rs < rt && rs != 0 600 601 InsnType Rs = fieldFromInstruction(insn, 21, 5); 602 InsnType Rt = fieldFromInstruction(insn, 16, 5); 603 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 604 bool HasRs = false; 605 606 if (Rs >= Rt) { 607 MI.setOpcode(Mips::BNVC); 608 HasRs = true; 609 } else if (Rs != 0 && Rs < Rt) { 610 MI.setOpcode(Mips::BNEC); 611 HasRs = true; 612 } else 613 MI.setOpcode(Mips::BNEZALC); 614 615 if (HasRs) 616 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 617 Rs))); 618 619 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 620 Rt))); 621 MI.addOperand(MCOperand::createImm(Imm)); 622 623 return MCDisassembler::Success; 624 } 625 626 template <typename InsnType> 627 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 628 uint64_t Address, 629 const void *Decoder) { 630 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 631 // (otherwise we would have matched the BLEZL instruction from the earlier 632 // ISA's instead). 633 // 634 // We have: 635 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 636 // Invalid if rs == 0 637 // BLEZC if rs == 0 && rt != 0 638 // BGEZC if rs == rt && rt != 0 639 // BGEC if rs != rt && rs != 0 && rt != 0 640 641 InsnType Rs = fieldFromInstruction(insn, 21, 5); 642 InsnType Rt = fieldFromInstruction(insn, 16, 5); 643 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 644 bool HasRs = false; 645 646 if (Rt == 0) 647 return MCDisassembler::Fail; 648 else if (Rs == 0) 649 MI.setOpcode(Mips::BLEZC); 650 else if (Rs == Rt) 651 MI.setOpcode(Mips::BGEZC); 652 else { 653 HasRs = true; 654 MI.setOpcode(Mips::BGEC); 655 } 656 657 if (HasRs) 658 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 659 Rs))); 660 661 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 662 Rt))); 663 664 MI.addOperand(MCOperand::createImm(Imm)); 665 666 return MCDisassembler::Success; 667 } 668 669 template <typename InsnType> 670 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 671 uint64_t Address, 672 const void *Decoder) { 673 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 674 // (otherwise we would have matched the BGTZL instruction from the earlier 675 // ISA's instead). 676 // 677 // We have: 678 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 679 // Invalid if rs == 0 680 // BGTZC if rs == 0 && rt != 0 681 // BLTZC if rs == rt && rt != 0 682 // BLTC if rs != rt && rs != 0 && rt != 0 683 684 bool HasRs = false; 685 686 InsnType Rs = fieldFromInstruction(insn, 21, 5); 687 InsnType Rt = fieldFromInstruction(insn, 16, 5); 688 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 689 690 if (Rt == 0) 691 return MCDisassembler::Fail; 692 else if (Rs == 0) 693 MI.setOpcode(Mips::BGTZC); 694 else if (Rs == Rt) 695 MI.setOpcode(Mips::BLTZC); 696 else { 697 MI.setOpcode(Mips::BLTC); 698 HasRs = true; 699 } 700 701 if (HasRs) 702 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 703 Rs))); 704 705 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 706 Rt))); 707 708 MI.addOperand(MCOperand::createImm(Imm)); 709 710 return MCDisassembler::Success; 711 } 712 713 template <typename InsnType> 714 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 715 uint64_t Address, 716 const void *Decoder) { 717 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 718 // (otherwise we would have matched the BGTZ instruction from the earlier 719 // ISA's instead). 720 // 721 // We have: 722 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 723 // BGTZ if rt == 0 724 // BGTZALC if rs == 0 && rt != 0 725 // BLTZALC if rs != 0 && rs == rt 726 // BLTUC if rs != 0 && rs != rt 727 728 InsnType Rs = fieldFromInstruction(insn, 21, 5); 729 InsnType Rt = fieldFromInstruction(insn, 16, 5); 730 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 731 bool HasRs = false; 732 bool HasRt = false; 733 734 if (Rt == 0) { 735 MI.setOpcode(Mips::BGTZ); 736 HasRs = true; 737 } else if (Rs == 0) { 738 MI.setOpcode(Mips::BGTZALC); 739 HasRt = true; 740 } else if (Rs == Rt) { 741 MI.setOpcode(Mips::BLTZALC); 742 HasRs = true; 743 } else { 744 MI.setOpcode(Mips::BLTUC); 745 HasRs = true; 746 HasRt = true; 747 } 748 749 if (HasRs) 750 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 751 Rs))); 752 753 if (HasRt) 754 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 755 Rt))); 756 757 MI.addOperand(MCOperand::createImm(Imm)); 758 759 return MCDisassembler::Success; 760 } 761 762 template <typename InsnType> 763 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 764 uint64_t Address, 765 const void *Decoder) { 766 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 767 // (otherwise we would have matched the BLEZL instruction from the earlier 768 // ISA's instead). 769 // 770 // We have: 771 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 772 // Invalid if rs == 0 773 // BLEZALC if rs == 0 && rt != 0 774 // BGEZALC if rs == rt && rt != 0 775 // BGEUC if rs != rt && rs != 0 && rt != 0 776 777 InsnType Rs = fieldFromInstruction(insn, 21, 5); 778 InsnType Rt = fieldFromInstruction(insn, 16, 5); 779 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 780 bool HasRs = false; 781 782 if (Rt == 0) 783 return MCDisassembler::Fail; 784 else if (Rs == 0) 785 MI.setOpcode(Mips::BLEZALC); 786 else if (Rs == Rt) 787 MI.setOpcode(Mips::BGEZALC); 788 else { 789 HasRs = true; 790 MI.setOpcode(Mips::BGEUC); 791 } 792 793 if (HasRs) 794 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 795 Rs))); 796 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 797 Rt))); 798 799 MI.addOperand(MCOperand::createImm(Imm)); 800 801 return MCDisassembler::Success; 802 } 803 804 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 805 /// according to the given endianess. 806 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 807 uint64_t &Size, uint32_t &Insn, 808 bool IsBigEndian) { 809 // We want to read exactly 2 Bytes of data. 810 if (Bytes.size() < 2) { 811 Size = 0; 812 return MCDisassembler::Fail; 813 } 814 815 if (IsBigEndian) { 816 Insn = (Bytes[0] << 8) | Bytes[1]; 817 } else { 818 Insn = (Bytes[1] << 8) | Bytes[0]; 819 } 820 821 return MCDisassembler::Success; 822 } 823 824 /// Read four bytes from the ArrayRef and return 32 bit word sorted 825 /// according to the given endianess 826 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 827 uint64_t &Size, uint32_t &Insn, 828 bool IsBigEndian, bool IsMicroMips) { 829 // We want to read exactly 4 Bytes of data. 830 if (Bytes.size() < 4) { 831 Size = 0; 832 return MCDisassembler::Fail; 833 } 834 835 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 836 // always precede the low 16 bits in the instruction stream (that is, they 837 // are placed at lower addresses in the instruction stream). 838 // 839 // microMIPS byte ordering: 840 // Big-endian: 0 | 1 | 2 | 3 841 // Little-endian: 1 | 0 | 3 | 2 842 843 if (IsBigEndian) { 844 // Encoded as a big-endian 32-bit word in the stream. 845 Insn = 846 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 847 } else { 848 if (IsMicroMips) { 849 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 850 (Bytes[1] << 24); 851 } else { 852 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 853 (Bytes[3] << 24); 854 } 855 } 856 857 return MCDisassembler::Success; 858 } 859 860 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 861 ArrayRef<uint8_t> Bytes, 862 uint64_t Address, 863 raw_ostream &VStream, 864 raw_ostream &CStream) const { 865 uint32_t Insn; 866 DecodeStatus Result; 867 868 if (IsMicroMips) { 869 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 870 871 if (hasMips32r6()) { 872 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 873 // Calling the auto-generated decoder function for microMIPS32R6 874 // (and microMIPS64R6) 16-bit instructions. 875 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 876 Address, this, STI); 877 if (Result != MCDisassembler::Fail) { 878 Size = 2; 879 return Result; 880 } 881 } 882 883 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 884 // Calling the auto-generated decoder function for microMIPS 16-bit 885 // instructions. 886 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 887 this, STI); 888 if (Result != MCDisassembler::Fail) { 889 Size = 2; 890 return Result; 891 } 892 893 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 894 if (Result == MCDisassembler::Fail) 895 return MCDisassembler::Fail; 896 897 if (hasMips32r6()) { 898 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 899 // Calling the auto-generated decoder function. 900 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 901 this, STI); 902 if (Result != MCDisassembler::Fail) { 903 Size = 4; 904 return Result; 905 } 906 } 907 908 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 909 // Calling the auto-generated decoder function. 910 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 911 this, STI); 912 if (Result != MCDisassembler::Fail) { 913 Size = 4; 914 return Result; 915 } 916 return MCDisassembler::Fail; 917 } 918 919 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 920 if (Result == MCDisassembler::Fail) 921 return MCDisassembler::Fail; 922 923 if (hasCOP3()) { 924 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 925 Result = 926 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 927 if (Result != MCDisassembler::Fail) { 928 Size = 4; 929 return Result; 930 } 931 } 932 933 if (hasMips32r6() && isGP64()) { 934 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 935 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 936 Address, this, STI); 937 if (Result != MCDisassembler::Fail) { 938 Size = 4; 939 return Result; 940 } 941 } 942 943 if (hasMips32r6()) { 944 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 945 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 946 Address, this, STI); 947 if (Result != MCDisassembler::Fail) { 948 Size = 4; 949 return Result; 950 } 951 } 952 953 if (hasCnMips()) { 954 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 955 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 956 Address, this, STI); 957 if (Result != MCDisassembler::Fail) { 958 Size = 4; 959 return Result; 960 } 961 } 962 963 if (isGP64()) { 964 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 965 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 966 Address, this, STI); 967 if (Result != MCDisassembler::Fail) { 968 Size = 4; 969 return Result; 970 } 971 } 972 973 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 974 // Calling the auto-generated decoder function. 975 Result = 976 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 977 if (Result != MCDisassembler::Fail) { 978 Size = 4; 979 return Result; 980 } 981 982 return MCDisassembler::Fail; 983 } 984 985 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 986 unsigned RegNo, 987 uint64_t Address, 988 const void *Decoder) { 989 990 return MCDisassembler::Fail; 991 992 } 993 994 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 995 unsigned RegNo, 996 uint64_t Address, 997 const void *Decoder) { 998 999 if (RegNo > 31) 1000 return MCDisassembler::Fail; 1001 1002 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1003 Inst.addOperand(MCOperand::createReg(Reg)); 1004 return MCDisassembler::Success; 1005 } 1006 1007 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1008 unsigned RegNo, 1009 uint64_t Address, 1010 const void *Decoder) { 1011 if (RegNo > 7) 1012 return MCDisassembler::Fail; 1013 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1014 Inst.addOperand(MCOperand::createReg(Reg)); 1015 return MCDisassembler::Success; 1016 } 1017 1018 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1019 unsigned RegNo, 1020 uint64_t Address, 1021 const void *Decoder) { 1022 if (RegNo > 7) 1023 return MCDisassembler::Fail; 1024 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1025 Inst.addOperand(MCOperand::createReg(Reg)); 1026 return MCDisassembler::Success; 1027 } 1028 1029 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1030 unsigned RegNo, 1031 uint64_t Address, 1032 const void *Decoder) { 1033 if (RegNo > 7) 1034 return MCDisassembler::Fail; 1035 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1036 Inst.addOperand(MCOperand::createReg(Reg)); 1037 return MCDisassembler::Success; 1038 } 1039 1040 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1041 unsigned RegNo, 1042 uint64_t Address, 1043 const void *Decoder) { 1044 if (RegNo > 31) 1045 return MCDisassembler::Fail; 1046 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1047 Inst.addOperand(MCOperand::createReg(Reg)); 1048 return MCDisassembler::Success; 1049 } 1050 1051 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1052 unsigned RegNo, 1053 uint64_t Address, 1054 const void *Decoder) { 1055 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1056 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1057 1058 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1059 } 1060 1061 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1062 unsigned RegNo, 1063 uint64_t Address, 1064 const void *Decoder) { 1065 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1066 } 1067 1068 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1069 unsigned RegNo, 1070 uint64_t Address, 1071 const void *Decoder) { 1072 if (RegNo > 31) 1073 return MCDisassembler::Fail; 1074 1075 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1076 Inst.addOperand(MCOperand::createReg(Reg)); 1077 return MCDisassembler::Success; 1078 } 1079 1080 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1081 unsigned RegNo, 1082 uint64_t Address, 1083 const void *Decoder) { 1084 if (RegNo > 31) 1085 return MCDisassembler::Fail; 1086 1087 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1088 Inst.addOperand(MCOperand::createReg(Reg)); 1089 return MCDisassembler::Success; 1090 } 1091 1092 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1093 unsigned RegNo, 1094 uint64_t Address, 1095 const void *Decoder) { 1096 if (RegNo > 31) 1097 return MCDisassembler::Fail; 1098 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1099 Inst.addOperand(MCOperand::createReg(Reg)); 1100 return MCDisassembler::Success; 1101 } 1102 1103 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1104 unsigned RegNo, 1105 uint64_t Address, 1106 const void *Decoder) { 1107 if (RegNo > 7) 1108 return MCDisassembler::Fail; 1109 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1110 Inst.addOperand(MCOperand::createReg(Reg)); 1111 return MCDisassembler::Success; 1112 } 1113 1114 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1115 uint64_t Address, 1116 const void *Decoder) { 1117 if (RegNo > 31) 1118 return MCDisassembler::Fail; 1119 1120 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1121 Inst.addOperand(MCOperand::createReg(Reg)); 1122 return MCDisassembler::Success; 1123 } 1124 1125 static DecodeStatus DecodeMem(MCInst &Inst, 1126 unsigned Insn, 1127 uint64_t Address, 1128 const void *Decoder) { 1129 int Offset = SignExtend32<16>(Insn & 0xffff); 1130 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1131 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1132 1133 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1134 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1135 1136 if (Inst.getOpcode() == Mips::SC || 1137 Inst.getOpcode() == Mips::SCD) 1138 Inst.addOperand(MCOperand::createReg(Reg)); 1139 1140 Inst.addOperand(MCOperand::createReg(Reg)); 1141 Inst.addOperand(MCOperand::createReg(Base)); 1142 Inst.addOperand(MCOperand::createImm(Offset)); 1143 1144 return MCDisassembler::Success; 1145 } 1146 1147 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1148 unsigned Insn, 1149 uint64_t Address, 1150 const void *Decoder) { 1151 int Offset = SignExtend32<9>(Insn >> 7); 1152 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1153 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1154 1155 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1156 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1157 1158 if (Inst.getOpcode() == Mips::SCE) 1159 Inst.addOperand(MCOperand::createReg(Reg)); 1160 1161 Inst.addOperand(MCOperand::createReg(Reg)); 1162 Inst.addOperand(MCOperand::createReg(Base)); 1163 Inst.addOperand(MCOperand::createImm(Offset)); 1164 1165 return MCDisassembler::Success; 1166 } 1167 1168 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1169 unsigned Insn, 1170 uint64_t Address, 1171 const void *Decoder) { 1172 int Offset = SignExtend32<9>(Insn & 0x1ff); 1173 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1174 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1175 1176 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1177 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1178 1179 Inst.addOperand(MCOperand::createReg(Reg)); 1180 Inst.addOperand(MCOperand::createReg(Base)); 1181 Inst.addOperand(MCOperand::createImm(Offset)); 1182 1183 return MCDisassembler::Success; 1184 } 1185 1186 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1187 unsigned Insn, 1188 uint64_t Address, 1189 const void *Decoder) { 1190 int Offset = SignExtend32<16>(Insn & 0xffff); 1191 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1192 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1193 1194 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1195 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1196 1197 Inst.addOperand(MCOperand::createReg(Reg)); 1198 Inst.addOperand(MCOperand::createReg(Base)); 1199 Inst.addOperand(MCOperand::createImm(Offset)); 1200 1201 return MCDisassembler::Success; 1202 } 1203 1204 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1205 unsigned Insn, 1206 uint64_t Address, 1207 const void *Decoder) { 1208 int Offset = SignExtend32<16>(Insn & 0xffff); 1209 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1210 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1211 1212 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1213 1214 Inst.addOperand(MCOperand::createReg(Base)); 1215 Inst.addOperand(MCOperand::createImm(Offset)); 1216 Inst.addOperand(MCOperand::createImm(Hint)); 1217 1218 return MCDisassembler::Success; 1219 } 1220 1221 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1222 unsigned Insn, 1223 uint64_t Address, 1224 const void *Decoder) { 1225 int Offset = SignExtend32<12>(Insn & 0xfff); 1226 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1227 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1228 1229 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1230 1231 Inst.addOperand(MCOperand::createReg(Base)); 1232 Inst.addOperand(MCOperand::createImm(Offset)); 1233 Inst.addOperand(MCOperand::createImm(Hint)); 1234 1235 return MCDisassembler::Success; 1236 } 1237 1238 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1239 unsigned Insn, 1240 uint64_t Address, 1241 const void *Decoder) { 1242 int Offset = SignExtend32<9>(Insn & 0x1ff); 1243 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1244 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1245 1246 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1247 1248 Inst.addOperand(MCOperand::createReg(Base)); 1249 Inst.addOperand(MCOperand::createImm(Offset)); 1250 Inst.addOperand(MCOperand::createImm(Hint)); 1251 1252 return MCDisassembler::Success; 1253 } 1254 1255 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1256 unsigned Insn, 1257 uint64_t Address, 1258 const void *Decoder) { 1259 int Offset = SignExtend32<9>(Insn >> 7); 1260 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1261 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1262 1263 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1264 1265 Inst.addOperand(MCOperand::createReg(Base)); 1266 Inst.addOperand(MCOperand::createImm(Offset)); 1267 Inst.addOperand(MCOperand::createImm(Hint)); 1268 1269 return MCDisassembler::Success; 1270 } 1271 1272 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1273 unsigned Insn, 1274 uint64_t Address, 1275 const void *Decoder) { 1276 int Offset = SignExtend32<9>(Insn & 0x1ff); 1277 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1278 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1279 1280 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1281 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1282 1283 Inst.addOperand(MCOperand::createReg(Reg)); 1284 Inst.addOperand(MCOperand::createReg(Base)); 1285 Inst.addOperand(MCOperand::createImm(Offset)); 1286 1287 return MCDisassembler::Success; 1288 } 1289 1290 static DecodeStatus DecodeSyncI(MCInst &Inst, 1291 unsigned Insn, 1292 uint64_t Address, 1293 const void *Decoder) { 1294 int Offset = SignExtend32<16>(Insn & 0xffff); 1295 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1296 1297 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1298 1299 Inst.addOperand(MCOperand::createReg(Base)); 1300 Inst.addOperand(MCOperand::createImm(Offset)); 1301 1302 return MCDisassembler::Success; 1303 } 1304 1305 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1306 unsigned Insn, 1307 uint64_t Address, 1308 const void *Decoder) { 1309 int Immediate = SignExtend32<16>(Insn & 0xffff); 1310 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1311 1312 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1313 1314 Inst.addOperand(MCOperand::createReg(Base)); 1315 Inst.addOperand(MCOperand::createImm(Immediate)); 1316 1317 return MCDisassembler::Success; 1318 } 1319 1320 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1321 uint64_t Address, const void *Decoder) { 1322 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1323 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1324 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1325 1326 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1327 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1328 1329 Inst.addOperand(MCOperand::createReg(Reg)); 1330 Inst.addOperand(MCOperand::createReg(Base)); 1331 1332 // The immediate field of an LD/ST instruction is scaled which means it must 1333 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1334 // data format. 1335 // .b - 1 byte 1336 // .h - 2 bytes 1337 // .w - 4 bytes 1338 // .d - 8 bytes 1339 switch(Inst.getOpcode()) 1340 { 1341 default: 1342 assert (0 && "Unexpected instruction"); 1343 return MCDisassembler::Fail; 1344 break; 1345 case Mips::LD_B: 1346 case Mips::ST_B: 1347 Inst.addOperand(MCOperand::createImm(Offset)); 1348 break; 1349 case Mips::LD_H: 1350 case Mips::ST_H: 1351 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1352 break; 1353 case Mips::LD_W: 1354 case Mips::ST_W: 1355 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1356 break; 1357 case Mips::LD_D: 1358 case Mips::ST_D: 1359 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1360 break; 1361 } 1362 1363 return MCDisassembler::Success; 1364 } 1365 1366 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1367 unsigned Insn, 1368 uint64_t Address, 1369 const void *Decoder) { 1370 unsigned Offset = Insn & 0xf; 1371 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1372 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1373 1374 switch (Inst.getOpcode()) { 1375 case Mips::LBU16_MM: 1376 case Mips::LHU16_MM: 1377 case Mips::LW16_MM: 1378 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1379 == MCDisassembler::Fail) 1380 return MCDisassembler::Fail; 1381 break; 1382 case Mips::SB16_MM: 1383 case Mips::SH16_MM: 1384 case Mips::SW16_MM: 1385 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1386 == MCDisassembler::Fail) 1387 return MCDisassembler::Fail; 1388 break; 1389 } 1390 1391 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1392 == MCDisassembler::Fail) 1393 return MCDisassembler::Fail; 1394 1395 switch (Inst.getOpcode()) { 1396 case Mips::LBU16_MM: 1397 if (Offset == 0xf) 1398 Inst.addOperand(MCOperand::createImm(-1)); 1399 else 1400 Inst.addOperand(MCOperand::createImm(Offset)); 1401 break; 1402 case Mips::SB16_MM: 1403 Inst.addOperand(MCOperand::createImm(Offset)); 1404 break; 1405 case Mips::LHU16_MM: 1406 case Mips::SH16_MM: 1407 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1408 break; 1409 case Mips::LW16_MM: 1410 case Mips::SW16_MM: 1411 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1412 break; 1413 } 1414 1415 return MCDisassembler::Success; 1416 } 1417 1418 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1419 unsigned Insn, 1420 uint64_t Address, 1421 const void *Decoder) { 1422 unsigned Offset = Insn & 0x1F; 1423 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1424 1425 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1426 1427 Inst.addOperand(MCOperand::createReg(Reg)); 1428 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1429 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1430 1431 return MCDisassembler::Success; 1432 } 1433 1434 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1435 unsigned Insn, 1436 uint64_t Address, 1437 const void *Decoder) { 1438 unsigned Offset = Insn & 0x7F; 1439 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1440 1441 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1442 1443 Inst.addOperand(MCOperand::createReg(Reg)); 1444 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1445 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1446 1447 return MCDisassembler::Success; 1448 } 1449 1450 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1451 unsigned Insn, 1452 uint64_t Address, 1453 const void *Decoder) { 1454 int Offset = SignExtend32<4>(Insn & 0xf); 1455 1456 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1457 == MCDisassembler::Fail) 1458 return MCDisassembler::Fail; 1459 1460 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1461 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1462 1463 return MCDisassembler::Success; 1464 } 1465 1466 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1467 unsigned Insn, 1468 uint64_t Address, 1469 const void *Decoder) { 1470 int Offset = SignExtend32<9>(Insn & 0x1ff); 1471 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1472 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1473 1474 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1475 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1476 1477 if (Inst.getOpcode() == Mips::SCE_MM) 1478 Inst.addOperand(MCOperand::createReg(Reg)); 1479 1480 Inst.addOperand(MCOperand::createReg(Reg)); 1481 Inst.addOperand(MCOperand::createReg(Base)); 1482 Inst.addOperand(MCOperand::createImm(Offset)); 1483 1484 return MCDisassembler::Success; 1485 } 1486 1487 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1488 unsigned Insn, 1489 uint64_t Address, 1490 const void *Decoder) { 1491 int Offset = SignExtend32<12>(Insn & 0x0fff); 1492 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1493 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1494 1495 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1496 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1497 1498 switch (Inst.getOpcode()) { 1499 case Mips::SWM32_MM: 1500 case Mips::LWM32_MM: 1501 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1502 == MCDisassembler::Fail) 1503 return MCDisassembler::Fail; 1504 Inst.addOperand(MCOperand::createReg(Base)); 1505 Inst.addOperand(MCOperand::createImm(Offset)); 1506 break; 1507 case Mips::SC_MM: 1508 Inst.addOperand(MCOperand::createReg(Reg)); 1509 // fallthrough 1510 default: 1511 Inst.addOperand(MCOperand::createReg(Reg)); 1512 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1513 Inst.addOperand(MCOperand::createReg(Reg+1)); 1514 1515 Inst.addOperand(MCOperand::createReg(Base)); 1516 Inst.addOperand(MCOperand::createImm(Offset)); 1517 } 1518 1519 return MCDisassembler::Success; 1520 } 1521 1522 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1523 unsigned Insn, 1524 uint64_t Address, 1525 const void *Decoder) { 1526 int Offset = SignExtend32<16>(Insn & 0xffff); 1527 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1528 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1529 1530 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1531 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1532 1533 Inst.addOperand(MCOperand::createReg(Reg)); 1534 Inst.addOperand(MCOperand::createReg(Base)); 1535 Inst.addOperand(MCOperand::createImm(Offset)); 1536 1537 return MCDisassembler::Success; 1538 } 1539 1540 static DecodeStatus DecodeFMem(MCInst &Inst, 1541 unsigned Insn, 1542 uint64_t Address, 1543 const void *Decoder) { 1544 int Offset = SignExtend32<16>(Insn & 0xffff); 1545 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1546 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1547 1548 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1549 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1550 1551 Inst.addOperand(MCOperand::createReg(Reg)); 1552 Inst.addOperand(MCOperand::createReg(Base)); 1553 Inst.addOperand(MCOperand::createImm(Offset)); 1554 1555 return MCDisassembler::Success; 1556 } 1557 1558 static DecodeStatus DecodeFMem2(MCInst &Inst, 1559 unsigned Insn, 1560 uint64_t Address, 1561 const void *Decoder) { 1562 int Offset = SignExtend32<16>(Insn & 0xffff); 1563 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1564 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1565 1566 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1567 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1568 1569 Inst.addOperand(MCOperand::createReg(Reg)); 1570 Inst.addOperand(MCOperand::createReg(Base)); 1571 Inst.addOperand(MCOperand::createImm(Offset)); 1572 1573 return MCDisassembler::Success; 1574 } 1575 1576 static DecodeStatus DecodeFMem3(MCInst &Inst, 1577 unsigned Insn, 1578 uint64_t Address, 1579 const void *Decoder) { 1580 int Offset = SignExtend32<16>(Insn & 0xffff); 1581 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1582 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1583 1584 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1585 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1586 1587 Inst.addOperand(MCOperand::createReg(Reg)); 1588 Inst.addOperand(MCOperand::createReg(Base)); 1589 Inst.addOperand(MCOperand::createImm(Offset)); 1590 1591 return MCDisassembler::Success; 1592 } 1593 1594 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1595 unsigned Insn, 1596 uint64_t Address, 1597 const void *Decoder) { 1598 int Offset = SignExtend32<11>(Insn & 0x07ff); 1599 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1600 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1601 1602 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1603 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1604 1605 Inst.addOperand(MCOperand::createReg(Reg)); 1606 Inst.addOperand(MCOperand::createReg(Base)); 1607 Inst.addOperand(MCOperand::createImm(Offset)); 1608 1609 return MCDisassembler::Success; 1610 } 1611 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1612 unsigned Insn, 1613 uint64_t Address, 1614 const void *Decoder) { 1615 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1616 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1617 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1618 1619 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1620 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1621 1622 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1623 Inst.addOperand(MCOperand::createReg(Rt)); 1624 } 1625 1626 Inst.addOperand(MCOperand::createReg(Rt)); 1627 Inst.addOperand(MCOperand::createReg(Base)); 1628 Inst.addOperand(MCOperand::createImm(Offset)); 1629 1630 return MCDisassembler::Success; 1631 } 1632 1633 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1634 unsigned RegNo, 1635 uint64_t Address, 1636 const void *Decoder) { 1637 // Currently only hardware register 29 is supported. 1638 if (RegNo != 29) 1639 return MCDisassembler::Fail; 1640 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1641 return MCDisassembler::Success; 1642 } 1643 1644 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1645 unsigned RegNo, 1646 uint64_t Address, 1647 const void *Decoder) { 1648 if (RegNo > 30 || RegNo %2) 1649 return MCDisassembler::Fail; 1650 1651 ; 1652 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1653 Inst.addOperand(MCOperand::createReg(Reg)); 1654 return MCDisassembler::Success; 1655 } 1656 1657 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1658 unsigned RegNo, 1659 uint64_t Address, 1660 const void *Decoder) { 1661 if (RegNo >= 4) 1662 return MCDisassembler::Fail; 1663 1664 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1665 Inst.addOperand(MCOperand::createReg(Reg)); 1666 return MCDisassembler::Success; 1667 } 1668 1669 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1670 unsigned RegNo, 1671 uint64_t Address, 1672 const void *Decoder) { 1673 if (RegNo >= 4) 1674 return MCDisassembler::Fail; 1675 1676 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1677 Inst.addOperand(MCOperand::createReg(Reg)); 1678 return MCDisassembler::Success; 1679 } 1680 1681 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1682 unsigned RegNo, 1683 uint64_t Address, 1684 const void *Decoder) { 1685 if (RegNo >= 4) 1686 return MCDisassembler::Fail; 1687 1688 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1689 Inst.addOperand(MCOperand::createReg(Reg)); 1690 return MCDisassembler::Success; 1691 } 1692 1693 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1694 unsigned RegNo, 1695 uint64_t Address, 1696 const void *Decoder) { 1697 if (RegNo > 31) 1698 return MCDisassembler::Fail; 1699 1700 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1701 Inst.addOperand(MCOperand::createReg(Reg)); 1702 return MCDisassembler::Success; 1703 } 1704 1705 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1706 unsigned RegNo, 1707 uint64_t Address, 1708 const void *Decoder) { 1709 if (RegNo > 31) 1710 return MCDisassembler::Fail; 1711 1712 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1713 Inst.addOperand(MCOperand::createReg(Reg)); 1714 return MCDisassembler::Success; 1715 } 1716 1717 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1718 unsigned RegNo, 1719 uint64_t Address, 1720 const void *Decoder) { 1721 if (RegNo > 31) 1722 return MCDisassembler::Fail; 1723 1724 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1725 Inst.addOperand(MCOperand::createReg(Reg)); 1726 return MCDisassembler::Success; 1727 } 1728 1729 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1730 unsigned RegNo, 1731 uint64_t Address, 1732 const void *Decoder) { 1733 if (RegNo > 31) 1734 return MCDisassembler::Fail; 1735 1736 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1737 Inst.addOperand(MCOperand::createReg(Reg)); 1738 return MCDisassembler::Success; 1739 } 1740 1741 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1742 unsigned RegNo, 1743 uint64_t Address, 1744 const void *Decoder) { 1745 if (RegNo > 7) 1746 return MCDisassembler::Fail; 1747 1748 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1749 Inst.addOperand(MCOperand::createReg(Reg)); 1750 return MCDisassembler::Success; 1751 } 1752 1753 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1754 unsigned RegNo, 1755 uint64_t Address, 1756 const void *Decoder) { 1757 if (RegNo > 31) 1758 return MCDisassembler::Fail; 1759 1760 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1761 Inst.addOperand(MCOperand::createReg(Reg)); 1762 return MCDisassembler::Success; 1763 } 1764 1765 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1766 unsigned RegNo, 1767 uint64_t Address, 1768 const void *Decoder) { 1769 if (RegNo > 31) 1770 return MCDisassembler::Fail; 1771 1772 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1773 Inst.addOperand(MCOperand::createReg(Reg)); 1774 return MCDisassembler::Success; 1775 } 1776 1777 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1778 unsigned Offset, 1779 uint64_t Address, 1780 const void *Decoder) { 1781 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1782 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1783 return MCDisassembler::Success; 1784 } 1785 1786 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1787 unsigned Insn, 1788 uint64_t Address, 1789 const void *Decoder) { 1790 1791 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1792 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1793 return MCDisassembler::Success; 1794 } 1795 1796 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1797 unsigned Offset, 1798 uint64_t Address, 1799 const void *Decoder) { 1800 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1801 1802 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1803 return MCDisassembler::Success; 1804 } 1805 1806 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1807 unsigned Offset, 1808 uint64_t Address, 1809 const void *Decoder) { 1810 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1811 1812 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1813 return MCDisassembler::Success; 1814 } 1815 1816 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1817 unsigned Offset, 1818 uint64_t Address, 1819 const void *Decoder) { 1820 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1821 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1822 return MCDisassembler::Success; 1823 } 1824 1825 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1826 unsigned Offset, 1827 uint64_t Address, 1828 const void *Decoder) { 1829 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1830 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1831 return MCDisassembler::Success; 1832 } 1833 1834 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1835 unsigned Offset, 1836 uint64_t Address, 1837 const void *Decoder) { 1838 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1839 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1840 return MCDisassembler::Success; 1841 } 1842 1843 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1844 unsigned Insn, 1845 uint64_t Address, 1846 const void *Decoder) { 1847 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1848 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1849 return MCDisassembler::Success; 1850 } 1851 1852 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1853 unsigned Value, 1854 uint64_t Address, 1855 const void *Decoder) { 1856 if (Value == 0) 1857 Inst.addOperand(MCOperand::createImm(1)); 1858 else if (Value == 0x7) 1859 Inst.addOperand(MCOperand::createImm(-1)); 1860 else 1861 Inst.addOperand(MCOperand::createImm(Value << 2)); 1862 return MCDisassembler::Success; 1863 } 1864 1865 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1866 unsigned Value, 1867 uint64_t Address, 1868 const void *Decoder) { 1869 Inst.addOperand(MCOperand::createImm(Value << 2)); 1870 return MCDisassembler::Success; 1871 } 1872 1873 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1874 unsigned Value, 1875 uint64_t Address, 1876 const void *Decoder) { 1877 if (Value == 0x7F) 1878 Inst.addOperand(MCOperand::createImm(-1)); 1879 else 1880 Inst.addOperand(MCOperand::createImm(Value)); 1881 return MCDisassembler::Success; 1882 } 1883 1884 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1885 unsigned Value, 1886 uint64_t Address, 1887 const void *Decoder) { 1888 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1889 return MCDisassembler::Success; 1890 } 1891 1892 static DecodeStatus DecodeSimm4(MCInst &Inst, 1893 unsigned Value, 1894 uint64_t Address, 1895 const void *Decoder) { 1896 Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value))); 1897 return MCDisassembler::Success; 1898 } 1899 1900 static DecodeStatus DecodeSimm16(MCInst &Inst, 1901 unsigned Insn, 1902 uint64_t Address, 1903 const void *Decoder) { 1904 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); 1905 return MCDisassembler::Success; 1906 } 1907 1908 template <unsigned Bits, int Offset> 1909 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 1910 uint64_t Address, 1911 const void *Decoder) { 1912 Value &= ((1 << Bits) - 1); 1913 Inst.addOperand(MCOperand::createImm(Value + Offset)); 1914 return MCDisassembler::Success; 1915 } 1916 1917 static DecodeStatus DecodeInsSize(MCInst &Inst, 1918 unsigned Insn, 1919 uint64_t Address, 1920 const void *Decoder) { 1921 // First we need to grab the pos(lsb) from MCInst. 1922 int Pos = Inst.getOperand(2).getImm(); 1923 int Size = (int) Insn - Pos + 1; 1924 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1925 return MCDisassembler::Success; 1926 } 1927 1928 static DecodeStatus DecodeExtSize(MCInst &Inst, 1929 unsigned Insn, 1930 uint64_t Address, 1931 const void *Decoder) { 1932 int Size = (int) Insn + 1; 1933 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 1934 return MCDisassembler::Success; 1935 } 1936 1937 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1938 uint64_t Address, const void *Decoder) { 1939 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 1940 return MCDisassembler::Success; 1941 } 1942 1943 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1944 uint64_t Address, const void *Decoder) { 1945 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 1946 return MCDisassembler::Success; 1947 } 1948 1949 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1950 uint64_t Address, const void *Decoder) { 1951 int32_t DecodedValue; 1952 switch (Insn) { 1953 case 0: DecodedValue = 256; break; 1954 case 1: DecodedValue = 257; break; 1955 case 510: DecodedValue = -258; break; 1956 case 511: DecodedValue = -257; break; 1957 default: DecodedValue = SignExtend32<9>(Insn); break; 1958 } 1959 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 1960 return MCDisassembler::Success; 1961 } 1962 1963 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1964 uint64_t Address, const void *Decoder) { 1965 // Insn must be >= 0, since it is unsigned that condition is always true. 1966 assert(Insn < 16); 1967 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1968 255, 32768, 65535}; 1969 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 1970 return MCDisassembler::Success; 1971 } 1972 1973 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 1974 uint64_t Address, const void *Decoder) { 1975 Inst.addOperand(MCOperand::createImm(Insn << 2)); 1976 return MCDisassembler::Success; 1977 } 1978 1979 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 1980 unsigned Insn, 1981 uint64_t Address, 1982 const void *Decoder) { 1983 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 1984 Mips::S6, Mips::S7, Mips::FP}; 1985 unsigned RegNum; 1986 1987 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 1988 1989 // Empty register lists are not allowed. 1990 if (RegLst == 0) 1991 return MCDisassembler::Fail; 1992 1993 RegNum = RegLst & 0xf; 1994 1995 // RegLst values 10-15, and 26-31 are reserved. 1996 if (RegNum > 9) 1997 return MCDisassembler::Fail; 1998 1999 for (unsigned i = 0; i < RegNum; i++) 2000 Inst.addOperand(MCOperand::createReg(Regs[i])); 2001 2002 if (RegLst & 0x10) 2003 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2004 2005 return MCDisassembler::Success; 2006 } 2007 2008 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2009 uint64_t Address, 2010 const void *Decoder) { 2011 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2012 unsigned RegLst = fieldFromInstruction(Insn, 4, 2); 2013 unsigned RegNum = RegLst & 0x3; 2014 2015 for (unsigned i = 0; i <= RegNum; i++) 2016 Inst.addOperand(MCOperand::createReg(Regs[i])); 2017 2018 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2019 2020 return MCDisassembler::Success; 2021 } 2022 2023 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2024 uint64_t Address, const void *Decoder) { 2025 2026 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2027 2028 switch (RegPair) { 2029 default: 2030 return MCDisassembler::Fail; 2031 case 0: 2032 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2033 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2034 break; 2035 case 1: 2036 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2037 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2038 break; 2039 case 2: 2040 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2041 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2042 break; 2043 case 3: 2044 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2045 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2046 break; 2047 case 4: 2048 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2049 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2050 break; 2051 case 5: 2052 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2053 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2054 break; 2055 case 6: 2056 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2057 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2058 break; 2059 case 7: 2060 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2061 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2062 break; 2063 } 2064 2065 return MCDisassembler::Success; 2066 } 2067 2068 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2069 uint64_t Address, const void *Decoder) { 2070 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2071 return MCDisassembler::Success; 2072 } 2073