1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/TargetRegistry.h" 25 26 using namespace llvm; 27 28 #define DEBUG_TYPE "mips-disassembler" 29 30 typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32 namespace { 33 34 /// MipsDisassemblerBase - a disasembler class for Mips. 35 class MipsDisassemblerBase : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, 40 bool bigEndian) : 41 MCDisassembler(STI, Ctx), 42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {} 43 44 virtual ~MipsDisassemblerBase() {} 45 46 bool isN64() const { return IsN64; } 47 48 private: 49 bool IsN64; 50 protected: 51 bool isBigEndian; 52 }; 53 54 /// MipsDisassembler - a disasembler class for Mips32. 55 class MipsDisassembler : public MipsDisassemblerBase { 56 bool IsMicroMips; 57 public: 58 /// Constructor - Initializes the disassembler. 59 /// 60 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) 61 : MipsDisassemblerBase(STI, Ctx, bigEndian) { 62 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; 63 } 64 65 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; } 66 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; } 67 bool hasMips32r6() const { 68 return STI.getFeatureBits() & Mips::FeatureMips32r6; 69 } 70 71 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; } 72 73 bool hasCOP3() const { 74 // Only present in MIPS-I and MIPS-II 75 return !hasMips32() && !hasMips3(); 76 } 77 78 /// getInstruction - See MCDisassembler. 79 DecodeStatus getInstruction(MCInst &instr, 80 uint64_t &size, 81 const MemoryObject ®ion, 82 uint64_t address, 83 raw_ostream &vStream, 84 raw_ostream &cStream) const override; 85 }; 86 87 88 /// Mips64Disassembler - a disasembler class for Mips64. 89 class Mips64Disassembler : public MipsDisassemblerBase { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 94 bool bigEndian) : 95 MipsDisassemblerBase(STI, Ctx, bigEndian) {} 96 97 /// getInstruction - See MCDisassembler. 98 DecodeStatus getInstruction(MCInst &instr, 99 uint64_t &size, 100 const MemoryObject ®ion, 101 uint64_t address, 102 raw_ostream &vStream, 103 raw_ostream &cStream) const override; 104 }; 105 106 } // end anonymous namespace 107 108 // Forward declare these because the autogenerated code will reference them. 109 // Definitions are further down. 110 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 111 unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder); 114 115 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 116 unsigned RegNo, 117 uint64_t Address, 118 const void *Decoder); 119 120 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 121 unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 125 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 126 unsigned Insn, 127 uint64_t Address, 128 const void *Decoder); 129 130 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 131 unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 136 unsigned RegNo, 137 uint64_t Address, 138 const void *Decoder); 139 140 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 141 unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst, 146 unsigned RegNo, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 161 uint64_t Address, 162 const void *Decoder); 163 164 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 165 unsigned Insn, 166 uint64_t Address, 167 const void *Decoder); 168 169 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 170 unsigned RegNo, 171 uint64_t Address, 172 const void *Decoder); 173 174 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 175 unsigned RegNo, 176 uint64_t Address, 177 const void *Decoder); 178 179 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 180 unsigned RegNo, 181 uint64_t Address, 182 const void *Decoder); 183 184 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 185 unsigned RegNo, 186 uint64_t Address, 187 const void *Decoder); 188 189 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 190 unsigned RegNo, 191 uint64_t Address, 192 const void *Decoder); 193 194 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 195 unsigned RegNo, 196 uint64_t Address, 197 const void *Decoder); 198 199 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 200 unsigned RegNo, 201 uint64_t Address, 202 const void *Decoder); 203 204 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 205 unsigned RegNo, 206 uint64_t Address, 207 const void *Decoder); 208 209 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 210 unsigned RegNo, 211 uint64_t Address, 212 const void *Decoder); 213 214 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 215 unsigned RegNo, 216 uint64_t Address, 217 const void *Decoder); 218 219 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 220 unsigned Offset, 221 uint64_t Address, 222 const void *Decoder); 223 224 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 225 unsigned Insn, 226 uint64_t Address, 227 const void *Decoder); 228 229 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 230 unsigned Offset, 231 uint64_t Address, 232 const void *Decoder); 233 234 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 235 unsigned Offset, 236 uint64_t Address, 237 const void *Decoder); 238 239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 240 // shifted left by 1 bit. 241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 242 unsigned Offset, 243 uint64_t Address, 244 const void *Decoder); 245 246 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 247 // shifted left by 1 bit. 248 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 249 unsigned Insn, 250 uint64_t Address, 251 const void *Decoder); 252 253 static DecodeStatus DecodeMem(MCInst &Inst, 254 unsigned Insn, 255 uint64_t Address, 256 const void *Decoder); 257 258 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 261 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 262 unsigned Insn, 263 uint64_t Address, 264 const void *Decoder); 265 266 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 267 unsigned Insn, 268 uint64_t Address, 269 const void *Decoder); 270 271 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeSimm16(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 // Decode the immediate field of an LSA instruction which 286 // is off by one. 287 static DecodeStatus DecodeLSAImm(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeInsSize(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeExtSize(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 305 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 308 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 309 /// handle. 310 template <typename InsnType> 311 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 312 const void *Decoder); 313 314 template <typename InsnType> 315 static DecodeStatus 316 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 317 const void *Decoder); 318 319 template <typename InsnType> 320 static DecodeStatus 321 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 322 const void *Decoder); 323 324 template <typename InsnType> 325 static DecodeStatus 326 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 327 const void *Decoder); 328 329 template <typename InsnType> 330 static DecodeStatus 331 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 332 const void *Decoder); 333 334 template <typename InsnType> 335 static DecodeStatus 336 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 337 const void *Decoder); 338 339 template <typename InsnType> 340 static DecodeStatus 341 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 342 const void *Decoder); 343 344 namespace llvm { 345 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 346 TheMips64elTarget; 347 } 348 349 static MCDisassembler *createMipsDisassembler( 350 const Target &T, 351 const MCSubtargetInfo &STI, 352 MCContext &Ctx) { 353 return new MipsDisassembler(STI, Ctx, true); 354 } 355 356 static MCDisassembler *createMipselDisassembler( 357 const Target &T, 358 const MCSubtargetInfo &STI, 359 MCContext &Ctx) { 360 return new MipsDisassembler(STI, Ctx, false); 361 } 362 363 static MCDisassembler *createMips64Disassembler( 364 const Target &T, 365 const MCSubtargetInfo &STI, 366 MCContext &Ctx) { 367 return new Mips64Disassembler(STI, Ctx, true); 368 } 369 370 static MCDisassembler *createMips64elDisassembler( 371 const Target &T, 372 const MCSubtargetInfo &STI, 373 MCContext &Ctx) { 374 return new Mips64Disassembler(STI, Ctx, false); 375 } 376 377 extern "C" void LLVMInitializeMipsDisassembler() { 378 // Register the disassembler. 379 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 380 createMipsDisassembler); 381 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 382 createMipselDisassembler); 383 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 384 createMips64Disassembler); 385 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 386 createMips64elDisassembler); 387 } 388 389 #include "MipsGenDisassemblerTables.inc" 390 391 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 392 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); 393 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 394 return *(RegInfo->getRegClass(RC).begin() + RegNo); 395 } 396 397 template <typename InsnType> 398 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 399 const void *Decoder) { 400 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 401 // The size of the n field depends on the element size 402 // The register class also depends on this. 403 InsnType tmp = fieldFromInstruction(insn, 17, 5); 404 unsigned NSize = 0; 405 DecodeFN RegDecoder = nullptr; 406 if ((tmp & 0x18) == 0x00) { // INSVE_B 407 NSize = 4; 408 RegDecoder = DecodeMSA128BRegisterClass; 409 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 410 NSize = 3; 411 RegDecoder = DecodeMSA128HRegisterClass; 412 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 413 NSize = 2; 414 RegDecoder = DecodeMSA128WRegisterClass; 415 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 416 NSize = 1; 417 RegDecoder = DecodeMSA128DRegisterClass; 418 } else 419 llvm_unreachable("Invalid encoding"); 420 421 assert(NSize != 0 && RegDecoder != nullptr); 422 423 // $wd 424 tmp = fieldFromInstruction(insn, 6, 5); 425 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 426 return MCDisassembler::Fail; 427 // $wd_in 428 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 429 return MCDisassembler::Fail; 430 // $n 431 tmp = fieldFromInstruction(insn, 16, NSize); 432 MI.addOperand(MCOperand::CreateImm(tmp)); 433 // $ws 434 tmp = fieldFromInstruction(insn, 11, 5); 435 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 436 return MCDisassembler::Fail; 437 // $n2 438 MI.addOperand(MCOperand::CreateImm(0)); 439 440 return MCDisassembler::Success; 441 } 442 443 template <typename InsnType> 444 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 445 uint64_t Address, 446 const void *Decoder) { 447 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 448 // (otherwise we would have matched the ADDI instruction from the earlier 449 // ISA's instead). 450 // 451 // We have: 452 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 453 // BOVC if rs >= rt 454 // BEQZALC if rs == 0 && rt != 0 455 // BEQC if rs < rt && rs != 0 456 457 InsnType Rs = fieldFromInstruction(insn, 21, 5); 458 InsnType Rt = fieldFromInstruction(insn, 16, 5); 459 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; 460 bool HasRs = false; 461 462 if (Rs >= Rt) { 463 MI.setOpcode(Mips::BOVC); 464 HasRs = true; 465 } else if (Rs != 0 && Rs < Rt) { 466 MI.setOpcode(Mips::BEQC); 467 HasRs = true; 468 } else 469 MI.setOpcode(Mips::BEQZALC); 470 471 if (HasRs) 472 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 473 Rs))); 474 475 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 476 Rt))); 477 MI.addOperand(MCOperand::CreateImm(Imm)); 478 479 return MCDisassembler::Success; 480 } 481 482 template <typename InsnType> 483 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 484 uint64_t Address, 485 const void *Decoder) { 486 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 487 // (otherwise we would have matched the ADDI instruction from the earlier 488 // ISA's instead). 489 // 490 // We have: 491 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 492 // BNVC if rs >= rt 493 // BNEZALC if rs == 0 && rt != 0 494 // BNEC if rs < rt && rs != 0 495 496 InsnType Rs = fieldFromInstruction(insn, 21, 5); 497 InsnType Rt = fieldFromInstruction(insn, 16, 5); 498 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; 499 bool HasRs = false; 500 501 if (Rs >= Rt) { 502 MI.setOpcode(Mips::BNVC); 503 HasRs = true; 504 } else if (Rs != 0 && Rs < Rt) { 505 MI.setOpcode(Mips::BNEC); 506 HasRs = true; 507 } else 508 MI.setOpcode(Mips::BNEZALC); 509 510 if (HasRs) 511 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 512 Rs))); 513 514 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 515 Rt))); 516 MI.addOperand(MCOperand::CreateImm(Imm)); 517 518 return MCDisassembler::Success; 519 } 520 521 template <typename InsnType> 522 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 523 uint64_t Address, 524 const void *Decoder) { 525 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 526 // (otherwise we would have matched the BLEZL instruction from the earlier 527 // ISA's instead). 528 // 529 // We have: 530 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 531 // Invalid if rs == 0 532 // BLEZC if rs == 0 && rt != 0 533 // BGEZC if rs == rt && rt != 0 534 // BGEC if rs != rt && rs != 0 && rt != 0 535 536 InsnType Rs = fieldFromInstruction(insn, 21, 5); 537 InsnType Rt = fieldFromInstruction(insn, 16, 5); 538 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; 539 bool HasRs = false; 540 541 if (Rt == 0) 542 return MCDisassembler::Fail; 543 else if (Rs == 0) 544 MI.setOpcode(Mips::BLEZC); 545 else if (Rs == Rt) 546 MI.setOpcode(Mips::BGEZC); 547 else { 548 HasRs = true; 549 MI.setOpcode(Mips::BGEC); 550 } 551 552 if (HasRs) 553 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 554 Rs))); 555 556 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 557 Rt))); 558 559 MI.addOperand(MCOperand::CreateImm(Imm)); 560 561 return MCDisassembler::Success; 562 } 563 564 template <typename InsnType> 565 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 566 uint64_t Address, 567 const void *Decoder) { 568 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 569 // (otherwise we would have matched the BGTZL instruction from the earlier 570 // ISA's instead). 571 // 572 // We have: 573 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 574 // Invalid if rs == 0 575 // BGTZC if rs == 0 && rt != 0 576 // BLTZC if rs == rt && rt != 0 577 // BLTC if rs != rt && rs != 0 && rt != 0 578 579 InsnType Rs = fieldFromInstruction(insn, 21, 5); 580 InsnType Rt = fieldFromInstruction(insn, 16, 5); 581 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; 582 583 if (Rt == 0) 584 return MCDisassembler::Fail; 585 else if (Rs == 0) 586 MI.setOpcode(Mips::BGTZC); 587 else if (Rs == Rt) 588 MI.setOpcode(Mips::BLTZC); 589 else 590 return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet. 591 592 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 593 Rt))); 594 595 MI.addOperand(MCOperand::CreateImm(Imm)); 596 597 return MCDisassembler::Success; 598 } 599 600 template <typename InsnType> 601 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 602 uint64_t Address, 603 const void *Decoder) { 604 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 605 // (otherwise we would have matched the BGTZ instruction from the earlier 606 // ISA's instead). 607 // 608 // We have: 609 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 610 // BGTZ if rt == 0 611 // BGTZALC if rs == 0 && rt != 0 612 // BLTZALC if rs != 0 && rs == rt 613 // BLTUC if rs != 0 && rs != rt 614 615 InsnType Rs = fieldFromInstruction(insn, 21, 5); 616 InsnType Rt = fieldFromInstruction(insn, 16, 5); 617 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; 618 bool HasRs = false; 619 bool HasRt = false; 620 621 if (Rt == 0) { 622 MI.setOpcode(Mips::BGTZ); 623 HasRs = true; 624 } else if (Rs == 0) { 625 MI.setOpcode(Mips::BGTZALC); 626 HasRt = true; 627 } else if (Rs == Rt) { 628 MI.setOpcode(Mips::BLTZALC); 629 HasRs = true; 630 } else 631 return MCDisassembler::Fail; // BLTUC not implemented yet 632 633 if (HasRs) 634 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 635 Rs))); 636 637 if (HasRt) 638 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 639 Rt))); 640 641 MI.addOperand(MCOperand::CreateImm(Imm)); 642 643 return MCDisassembler::Success; 644 } 645 646 template <typename InsnType> 647 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 648 uint64_t Address, 649 const void *Decoder) { 650 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 651 // (otherwise we would have matched the BLEZL instruction from the earlier 652 // ISA's instead). 653 // 654 // We have: 655 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 656 // Invalid if rs == 0 657 // BLEZALC if rs == 0 && rt != 0 658 // BGEZALC if rs == rt && rt != 0 659 // BGEUC if rs != rt && rs != 0 && rt != 0 660 661 InsnType Rs = fieldFromInstruction(insn, 21, 5); 662 InsnType Rt = fieldFromInstruction(insn, 16, 5); 663 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; 664 bool HasRs = false; 665 666 if (Rt == 0) 667 return MCDisassembler::Fail; 668 else if (Rs == 0) 669 MI.setOpcode(Mips::BLEZALC); 670 else if (Rs == Rt) 671 MI.setOpcode(Mips::BGEZALC); 672 else { 673 HasRs = true; 674 MI.setOpcode(Mips::BGEUC); 675 } 676 677 if (HasRs) 678 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 679 Rs))); 680 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 681 Rt))); 682 683 MI.addOperand(MCOperand::CreateImm(Imm)); 684 685 return MCDisassembler::Success; 686 } 687 688 /// readInstruction - read four bytes from the MemoryObject 689 /// and return 32 bit word sorted according to the given endianess 690 static DecodeStatus readInstruction32(const MemoryObject ®ion, 691 uint64_t address, 692 uint64_t &size, 693 uint32_t &insn, 694 bool isBigEndian, 695 bool IsMicroMips) { 696 uint8_t Bytes[4]; 697 698 // We want to read exactly 4 Bytes of data. 699 if (region.readBytes(address, 4, Bytes) == -1) { 700 size = 0; 701 return MCDisassembler::Fail; 702 } 703 704 if (isBigEndian) { 705 // Encoded as a big-endian 32-bit word in the stream. 706 insn = (Bytes[3] << 0) | 707 (Bytes[2] << 8) | 708 (Bytes[1] << 16) | 709 (Bytes[0] << 24); 710 } 711 else { 712 // Encoded as a small-endian 32-bit word in the stream. 713 // Little-endian byte ordering: 714 // mips32r2: 4 | 3 | 2 | 1 715 // microMIPS: 2 | 1 | 4 | 3 716 if (IsMicroMips) { 717 insn = (Bytes[2] << 0) | 718 (Bytes[3] << 8) | 719 (Bytes[0] << 16) | 720 (Bytes[1] << 24); 721 } else { 722 insn = (Bytes[0] << 0) | 723 (Bytes[1] << 8) | 724 (Bytes[2] << 16) | 725 (Bytes[3] << 24); 726 } 727 } 728 729 return MCDisassembler::Success; 730 } 731 732 DecodeStatus 733 MipsDisassembler::getInstruction(MCInst &instr, 734 uint64_t &Size, 735 const MemoryObject &Region, 736 uint64_t Address, 737 raw_ostream &vStream, 738 raw_ostream &cStream) const { 739 uint32_t Insn; 740 741 DecodeStatus Result = readInstruction32(Region, Address, Size, 742 Insn, isBigEndian, IsMicroMips); 743 if (Result == MCDisassembler::Fail) 744 return MCDisassembler::Fail; 745 746 if (IsMicroMips) { 747 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n"); 748 // Calling the auto-generated decoder function. 749 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, 750 this, STI); 751 if (Result != MCDisassembler::Fail) { 752 Size = 4; 753 return Result; 754 } 755 return MCDisassembler::Fail; 756 } 757 758 if (hasCOP3()) { 759 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 760 Result = 761 decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI); 762 if (Result != MCDisassembler::Fail) { 763 Size = 4; 764 return Result; 765 } 766 } 767 768 if (hasMips32r6() && isGP64()) { 769 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 770 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, 771 Address, this, STI); 772 if (Result != MCDisassembler::Fail) { 773 Size = 4; 774 return Result; 775 } 776 } 777 778 if (hasMips32r6()) { 779 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 780 Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, 781 Address, this, STI); 782 if (Result != MCDisassembler::Fail) { 783 Size = 4; 784 return Result; 785 } 786 } 787 788 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 789 // Calling the auto-generated decoder function. 790 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, 791 this, STI); 792 if (Result != MCDisassembler::Fail) { 793 Size = 4; 794 return Result; 795 } 796 797 return MCDisassembler::Fail; 798 } 799 800 DecodeStatus 801 Mips64Disassembler::getInstruction(MCInst &instr, 802 uint64_t &Size, 803 const MemoryObject &Region, 804 uint64_t Address, 805 raw_ostream &vStream, 806 raw_ostream &cStream) const { 807 uint32_t Insn; 808 809 DecodeStatus Result = readInstruction32(Region, Address, Size, 810 Insn, isBigEndian, false); 811 if (Result == MCDisassembler::Fail) 812 return MCDisassembler::Fail; 813 814 // Calling the auto-generated decoder function. 815 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, 816 this, STI); 817 if (Result != MCDisassembler::Fail) { 818 Size = 4; 819 return Result; 820 } 821 // If we fail to decode in Mips64 decoder space we can try in Mips32 822 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, 823 this, STI); 824 if (Result != MCDisassembler::Fail) { 825 Size = 4; 826 return Result; 827 } 828 829 return MCDisassembler::Fail; 830 } 831 832 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 833 unsigned RegNo, 834 uint64_t Address, 835 const void *Decoder) { 836 837 return MCDisassembler::Fail; 838 839 } 840 841 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 842 unsigned RegNo, 843 uint64_t Address, 844 const void *Decoder) { 845 846 if (RegNo > 31) 847 return MCDisassembler::Fail; 848 849 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 850 Inst.addOperand(MCOperand::CreateReg(Reg)); 851 return MCDisassembler::Success; 852 } 853 854 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 855 unsigned RegNo, 856 uint64_t Address, 857 const void *Decoder) { 858 if (RegNo > 31) 859 return MCDisassembler::Fail; 860 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 861 Inst.addOperand(MCOperand::CreateReg(Reg)); 862 return MCDisassembler::Success; 863 } 864 865 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 866 unsigned RegNo, 867 uint64_t Address, 868 const void *Decoder) { 869 if (static_cast<const MipsDisassembler *>(Decoder)->isN64()) 870 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 871 872 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 873 } 874 875 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 876 unsigned RegNo, 877 uint64_t Address, 878 const void *Decoder) { 879 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 880 } 881 882 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 883 unsigned RegNo, 884 uint64_t Address, 885 const void *Decoder) { 886 if (RegNo > 31) 887 return MCDisassembler::Fail; 888 889 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 890 Inst.addOperand(MCOperand::CreateReg(Reg)); 891 return MCDisassembler::Success; 892 } 893 894 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 895 unsigned RegNo, 896 uint64_t Address, 897 const void *Decoder) { 898 if (RegNo > 31) 899 return MCDisassembler::Fail; 900 901 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 902 Inst.addOperand(MCOperand::CreateReg(Reg)); 903 return MCDisassembler::Success; 904 } 905 906 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst, 907 unsigned RegNo, 908 uint64_t Address, 909 const void *Decoder) { 910 if (RegNo > 31) 911 return MCDisassembler::Fail; 912 913 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo); 914 Inst.addOperand(MCOperand::CreateReg(Reg)); 915 return MCDisassembler::Success; 916 } 917 918 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 919 unsigned RegNo, 920 uint64_t Address, 921 const void *Decoder) { 922 if (RegNo > 31) 923 return MCDisassembler::Fail; 924 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 925 Inst.addOperand(MCOperand::CreateReg(Reg)); 926 return MCDisassembler::Success; 927 } 928 929 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 930 unsigned RegNo, 931 uint64_t Address, 932 const void *Decoder) { 933 if (RegNo > 7) 934 return MCDisassembler::Fail; 935 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 936 Inst.addOperand(MCOperand::CreateReg(Reg)); 937 return MCDisassembler::Success; 938 } 939 940 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 941 uint64_t Address, 942 const void *Decoder) { 943 if (RegNo > 31) 944 return MCDisassembler::Fail; 945 946 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 947 Inst.addOperand(MCOperand::CreateReg(Reg)); 948 return MCDisassembler::Success; 949 } 950 951 static DecodeStatus DecodeMem(MCInst &Inst, 952 unsigned Insn, 953 uint64_t Address, 954 const void *Decoder) { 955 int Offset = SignExtend32<16>(Insn & 0xffff); 956 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 957 unsigned Base = fieldFromInstruction(Insn, 21, 5); 958 959 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 960 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 961 962 if(Inst.getOpcode() == Mips::SC){ 963 Inst.addOperand(MCOperand::CreateReg(Reg)); 964 } 965 966 Inst.addOperand(MCOperand::CreateReg(Reg)); 967 Inst.addOperand(MCOperand::CreateReg(Base)); 968 Inst.addOperand(MCOperand::CreateImm(Offset)); 969 970 return MCDisassembler::Success; 971 } 972 973 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 974 uint64_t Address, const void *Decoder) { 975 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 976 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 977 unsigned Base = fieldFromInstruction(Insn, 11, 5); 978 979 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 980 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 981 982 Inst.addOperand(MCOperand::CreateReg(Reg)); 983 Inst.addOperand(MCOperand::CreateReg(Base)); 984 985 // The immediate field of an LD/ST instruction is scaled which means it must 986 // be multiplied (when decoding) by the size (in bytes) of the instructions' 987 // data format. 988 // .b - 1 byte 989 // .h - 2 bytes 990 // .w - 4 bytes 991 // .d - 8 bytes 992 switch(Inst.getOpcode()) 993 { 994 default: 995 assert (0 && "Unexpected instruction"); 996 return MCDisassembler::Fail; 997 break; 998 case Mips::LD_B: 999 case Mips::ST_B: 1000 Inst.addOperand(MCOperand::CreateImm(Offset)); 1001 break; 1002 case Mips::LD_H: 1003 case Mips::ST_H: 1004 Inst.addOperand(MCOperand::CreateImm(Offset << 1)); 1005 break; 1006 case Mips::LD_W: 1007 case Mips::ST_W: 1008 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1009 break; 1010 case Mips::LD_D: 1011 case Mips::ST_D: 1012 Inst.addOperand(MCOperand::CreateImm(Offset << 3)); 1013 break; 1014 } 1015 1016 return MCDisassembler::Success; 1017 } 1018 1019 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1020 unsigned Insn, 1021 uint64_t Address, 1022 const void *Decoder) { 1023 int Offset = SignExtend32<12>(Insn & 0x0fff); 1024 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1025 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1026 1027 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1028 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1029 1030 if (Inst.getOpcode() == Mips::SC_MM) 1031 Inst.addOperand(MCOperand::CreateReg(Reg)); 1032 1033 Inst.addOperand(MCOperand::CreateReg(Reg)); 1034 Inst.addOperand(MCOperand::CreateReg(Base)); 1035 Inst.addOperand(MCOperand::CreateImm(Offset)); 1036 1037 return MCDisassembler::Success; 1038 } 1039 1040 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1041 unsigned Insn, 1042 uint64_t Address, 1043 const void *Decoder) { 1044 int Offset = SignExtend32<16>(Insn & 0xffff); 1045 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1046 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1047 1048 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1049 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1050 1051 Inst.addOperand(MCOperand::CreateReg(Reg)); 1052 Inst.addOperand(MCOperand::CreateReg(Base)); 1053 Inst.addOperand(MCOperand::CreateImm(Offset)); 1054 1055 return MCDisassembler::Success; 1056 } 1057 1058 static DecodeStatus DecodeFMem(MCInst &Inst, 1059 unsigned Insn, 1060 uint64_t Address, 1061 const void *Decoder) { 1062 int Offset = SignExtend32<16>(Insn & 0xffff); 1063 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1064 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1065 1066 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1067 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1068 1069 Inst.addOperand(MCOperand::CreateReg(Reg)); 1070 Inst.addOperand(MCOperand::CreateReg(Base)); 1071 Inst.addOperand(MCOperand::CreateImm(Offset)); 1072 1073 return MCDisassembler::Success; 1074 } 1075 1076 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1077 unsigned Insn, 1078 uint64_t Address, 1079 const void *Decoder) { 1080 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1081 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1082 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1083 1084 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1085 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1086 1087 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1088 Inst.addOperand(MCOperand::CreateReg(Rt)); 1089 } 1090 1091 Inst.addOperand(MCOperand::CreateReg(Rt)); 1092 Inst.addOperand(MCOperand::CreateReg(Base)); 1093 Inst.addOperand(MCOperand::CreateImm(Offset)); 1094 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1099 unsigned RegNo, 1100 uint64_t Address, 1101 const void *Decoder) { 1102 // Currently only hardware register 29 is supported. 1103 if (RegNo != 29) 1104 return MCDisassembler::Fail; 1105 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); 1106 return MCDisassembler::Success; 1107 } 1108 1109 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1110 unsigned RegNo, 1111 uint64_t Address, 1112 const void *Decoder) { 1113 if (RegNo > 30 || RegNo %2) 1114 return MCDisassembler::Fail; 1115 1116 ; 1117 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1118 Inst.addOperand(MCOperand::CreateReg(Reg)); 1119 return MCDisassembler::Success; 1120 } 1121 1122 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1123 unsigned RegNo, 1124 uint64_t Address, 1125 const void *Decoder) { 1126 if (RegNo >= 4) 1127 return MCDisassembler::Fail; 1128 1129 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1130 Inst.addOperand(MCOperand::CreateReg(Reg)); 1131 return MCDisassembler::Success; 1132 } 1133 1134 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1135 unsigned RegNo, 1136 uint64_t Address, 1137 const void *Decoder) { 1138 if (RegNo >= 4) 1139 return MCDisassembler::Fail; 1140 1141 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1142 Inst.addOperand(MCOperand::CreateReg(Reg)); 1143 return MCDisassembler::Success; 1144 } 1145 1146 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1147 unsigned RegNo, 1148 uint64_t Address, 1149 const void *Decoder) { 1150 if (RegNo >= 4) 1151 return MCDisassembler::Fail; 1152 1153 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1154 Inst.addOperand(MCOperand::CreateReg(Reg)); 1155 return MCDisassembler::Success; 1156 } 1157 1158 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1159 unsigned RegNo, 1160 uint64_t Address, 1161 const void *Decoder) { 1162 if (RegNo > 31) 1163 return MCDisassembler::Fail; 1164 1165 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1166 Inst.addOperand(MCOperand::CreateReg(Reg)); 1167 return MCDisassembler::Success; 1168 } 1169 1170 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1171 unsigned RegNo, 1172 uint64_t Address, 1173 const void *Decoder) { 1174 if (RegNo > 31) 1175 return MCDisassembler::Fail; 1176 1177 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1178 Inst.addOperand(MCOperand::CreateReg(Reg)); 1179 return MCDisassembler::Success; 1180 } 1181 1182 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1183 unsigned RegNo, 1184 uint64_t Address, 1185 const void *Decoder) { 1186 if (RegNo > 31) 1187 return MCDisassembler::Fail; 1188 1189 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1190 Inst.addOperand(MCOperand::CreateReg(Reg)); 1191 return MCDisassembler::Success; 1192 } 1193 1194 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1195 unsigned RegNo, 1196 uint64_t Address, 1197 const void *Decoder) { 1198 if (RegNo > 31) 1199 return MCDisassembler::Fail; 1200 1201 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1202 Inst.addOperand(MCOperand::CreateReg(Reg)); 1203 return MCDisassembler::Success; 1204 } 1205 1206 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1207 unsigned RegNo, 1208 uint64_t Address, 1209 const void *Decoder) { 1210 if (RegNo > 7) 1211 return MCDisassembler::Fail; 1212 1213 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1214 Inst.addOperand(MCOperand::CreateReg(Reg)); 1215 return MCDisassembler::Success; 1216 } 1217 1218 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1219 unsigned RegNo, 1220 uint64_t Address, 1221 const void *Decoder) { 1222 if (RegNo > 31) 1223 return MCDisassembler::Fail; 1224 1225 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1226 Inst.addOperand(MCOperand::CreateReg(Reg)); 1227 return MCDisassembler::Success; 1228 } 1229 1230 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1231 unsigned Offset, 1232 uint64_t Address, 1233 const void *Decoder) { 1234 int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4; 1235 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1236 return MCDisassembler::Success; 1237 } 1238 1239 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1240 unsigned Insn, 1241 uint64_t Address, 1242 const void *Decoder) { 1243 1244 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1245 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1246 return MCDisassembler::Success; 1247 } 1248 1249 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1250 unsigned Offset, 1251 uint64_t Address, 1252 const void *Decoder) { 1253 int32_t BranchOffset = SignExtend32<21>(Offset) << 2; 1254 1255 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1256 return MCDisassembler::Success; 1257 } 1258 1259 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1260 unsigned Offset, 1261 uint64_t Address, 1262 const void *Decoder) { 1263 int32_t BranchOffset = SignExtend32<26>(Offset) << 2; 1264 1265 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1266 return MCDisassembler::Success; 1267 } 1268 1269 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1270 unsigned Offset, 1271 uint64_t Address, 1272 const void *Decoder) { 1273 int32_t BranchOffset = SignExtend32<16>(Offset) << 1; 1274 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1275 return MCDisassembler::Success; 1276 } 1277 1278 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1279 unsigned Insn, 1280 uint64_t Address, 1281 const void *Decoder) { 1282 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1283 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1284 return MCDisassembler::Success; 1285 } 1286 1287 static DecodeStatus DecodeSimm16(MCInst &Inst, 1288 unsigned Insn, 1289 uint64_t Address, 1290 const void *Decoder) { 1291 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); 1292 return MCDisassembler::Success; 1293 } 1294 1295 static DecodeStatus DecodeLSAImm(MCInst &Inst, 1296 unsigned Insn, 1297 uint64_t Address, 1298 const void *Decoder) { 1299 // We add one to the immediate field as it was encoded as 'imm - 1'. 1300 Inst.addOperand(MCOperand::CreateImm(Insn + 1)); 1301 return MCDisassembler::Success; 1302 } 1303 1304 static DecodeStatus DecodeInsSize(MCInst &Inst, 1305 unsigned Insn, 1306 uint64_t Address, 1307 const void *Decoder) { 1308 // First we need to grab the pos(lsb) from MCInst. 1309 int Pos = Inst.getOperand(2).getImm(); 1310 int Size = (int) Insn - Pos + 1; 1311 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1312 return MCDisassembler::Success; 1313 } 1314 1315 static DecodeStatus DecodeExtSize(MCInst &Inst, 1316 unsigned Insn, 1317 uint64_t Address, 1318 const void *Decoder) { 1319 int Size = (int) Insn + 1; 1320 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1321 return MCDisassembler::Success; 1322 } 1323 1324 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1325 uint64_t Address, const void *Decoder) { 1326 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2)); 1327 return MCDisassembler::Success; 1328 } 1329 1330 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1331 uint64_t Address, const void *Decoder) { 1332 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3)); 1333 return MCDisassembler::Success; 1334 } 1335