1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 43 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 44 bool hasMips32r6() const { 45 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 46 } 47 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 48 49 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 50 51 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 52 53 bool hasCOP3() const { 54 // Only present in MIPS-I and MIPS-II 55 return !hasMips32() && !hasMips3(); 56 } 57 58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 59 ArrayRef<uint8_t> Bytes, uint64_t Address, 60 raw_ostream &VStream, 61 raw_ostream &CStream) const override; 62 }; 63 64 } // end anonymous namespace 65 66 // Forward declare these because the autogenerated code will reference them. 67 // Definitions are further down. 68 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 69 unsigned RegNo, 70 uint64_t Address, 71 const void *Decoder); 72 73 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 74 unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 78 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 79 unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 83 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 84 unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 88 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 89 unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 93 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 94 unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 99 unsigned Insn, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 114 unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 133 unsigned Insn, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 143 unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 148 unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 158 unsigned RegNo, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 163 unsigned RegNo, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 168 unsigned RegNo, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 183 unsigned RegNo, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 193 unsigned Offset, 194 uint64_t Address, 195 const void *Decoder); 196 197 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 198 unsigned Insn, 199 uint64_t Address, 200 const void *Decoder); 201 202 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 203 unsigned Offset, 204 uint64_t Address, 205 const void *Decoder); 206 207 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 208 unsigned Offset, 209 uint64_t Address, 210 const void *Decoder); 211 212 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 213 // shifted left by 1 bit. 214 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 215 unsigned Offset, 216 uint64_t Address, 217 const void *Decoder); 218 219 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 220 // shifted left by 1 bit. 221 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 222 unsigned Offset, 223 uint64_t Address, 224 const void *Decoder); 225 226 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 227 // shifted left by 1 bit. 228 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 229 unsigned Offset, 230 uint64_t Address, 231 const void *Decoder); 232 233 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 234 // shifted left by 1 bit. 235 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 236 unsigned Offset, 237 uint64_t Address, 238 const void *Decoder); 239 240 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 241 // shifted left by 1 bit. 242 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 243 unsigned Insn, 244 uint64_t Address, 245 const void *Decoder); 246 247 static DecodeStatus DecodeMem(MCInst &Inst, 248 unsigned Insn, 249 uint64_t Address, 250 const void *Decoder); 251 252 static DecodeStatus DecodeMemEVA(MCInst &Inst, 253 unsigned Insn, 254 uint64_t Address, 255 const void *Decoder); 256 257 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 258 unsigned Insn, 259 uint64_t Address, 260 const void *Decoder); 261 262 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 263 unsigned Insn, 264 uint64_t Address, 265 const void *Decoder); 266 267 static DecodeStatus DecodeCacheOp(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 273 unsigned Insn, 274 uint64_t Address, 275 const void *Decoder); 276 277 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 278 unsigned Insn, 279 uint64_t Address, 280 const void *Decoder); 281 282 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 283 unsigned Insn, 284 uint64_t Address, 285 const void *Decoder); 286 287 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeSyncI(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeSynciR6(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 305 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 316 unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 321 unsigned Insn, 322 uint64_t Address, 323 const void *Decoder); 324 325 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 326 unsigned Insn, 327 uint64_t Address, 328 const void *Decoder); 329 330 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 331 unsigned Insn, 332 uint64_t Address, 333 const void *Decoder); 334 335 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 336 unsigned Insn, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 341 uint64_t Address, 342 const void *Decoder); 343 344 static DecodeStatus DecodeFMemMMR6(MCInst &Inst, unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 349 uint64_t Address, 350 const void *Decoder); 351 352 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 353 uint64_t Address, 354 const void *Decoder); 355 356 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 357 uint64_t Address, 358 const void *Decoder); 359 360 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 361 uint64_t Address, 362 const void *Decoder); 363 364 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 365 unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 370 unsigned Value, 371 uint64_t Address, 372 const void *Decoder); 373 374 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 375 unsigned Value, 376 uint64_t Address, 377 const void *Decoder); 378 379 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 380 unsigned Value, 381 uint64_t Address, 382 const void *Decoder); 383 384 template <unsigned Bits, int Offset, int Scale> 385 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 386 uint64_t Address, 387 const void *Decoder); 388 389 template <unsigned Bits, int Offset> 390 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 391 uint64_t Address, 392 const void *Decoder) { 393 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 394 Decoder); 395 } 396 397 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 398 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 399 uint64_t Address, 400 const void *Decoder); 401 402 static DecodeStatus DecodeInsSize(MCInst &Inst, 403 unsigned Insn, 404 uint64_t Address, 405 const void *Decoder); 406 407 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 408 uint64_t Address, const void *Decoder); 409 410 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 411 uint64_t Address, const void *Decoder); 412 413 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 414 uint64_t Address, const void *Decoder); 415 416 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 417 uint64_t Address, const void *Decoder); 418 419 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 420 uint64_t Address, const void *Decoder); 421 422 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 423 /// handle. 424 template <typename InsnType> 425 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 426 const void *Decoder); 427 428 template <typename InsnType> 429 static DecodeStatus 430 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 431 const void *Decoder); 432 433 template <typename InsnType> 434 static DecodeStatus 435 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 436 const void *Decoder); 437 438 template <typename InsnType> 439 static DecodeStatus 440 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 441 const void *Decoder); 442 443 template <typename InsnType> 444 static DecodeStatus 445 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 446 const void *Decoder); 447 448 template <typename InsnType> 449 static DecodeStatus 450 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 451 const void *Decoder); 452 453 template <typename InsnType> 454 static DecodeStatus 455 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 456 const void *Decoder); 457 458 template <typename InsnType> 459 static DecodeStatus 460 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 461 const void *Decoder); 462 463 template <typename InsnType> 464 static DecodeStatus 465 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 466 const void *Decoder); 467 468 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 469 uint64_t Address, 470 const void *Decoder); 471 472 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 473 uint64_t Address, 474 const void *Decoder); 475 476 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 477 uint64_t Address, 478 const void *Decoder); 479 480 namespace llvm { 481 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 482 TheMips64elTarget; 483 } 484 485 static MCDisassembler *createMipsDisassembler( 486 const Target &T, 487 const MCSubtargetInfo &STI, 488 MCContext &Ctx) { 489 return new MipsDisassembler(STI, Ctx, true); 490 } 491 492 static MCDisassembler *createMipselDisassembler( 493 const Target &T, 494 const MCSubtargetInfo &STI, 495 MCContext &Ctx) { 496 return new MipsDisassembler(STI, Ctx, false); 497 } 498 499 extern "C" void LLVMInitializeMipsDisassembler() { 500 // Register the disassembler. 501 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 502 createMipsDisassembler); 503 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 504 createMipselDisassembler); 505 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 506 createMipsDisassembler); 507 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 508 createMipselDisassembler); 509 } 510 511 #include "MipsGenDisassemblerTables.inc" 512 513 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 514 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 515 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 516 return *(RegInfo->getRegClass(RC).begin() + RegNo); 517 } 518 519 template <typename InsnType> 520 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 521 const void *Decoder) { 522 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 523 // The size of the n field depends on the element size 524 // The register class also depends on this. 525 InsnType tmp = fieldFromInstruction(insn, 17, 5); 526 unsigned NSize = 0; 527 DecodeFN RegDecoder = nullptr; 528 if ((tmp & 0x18) == 0x00) { // INSVE_B 529 NSize = 4; 530 RegDecoder = DecodeMSA128BRegisterClass; 531 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 532 NSize = 3; 533 RegDecoder = DecodeMSA128HRegisterClass; 534 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 535 NSize = 2; 536 RegDecoder = DecodeMSA128WRegisterClass; 537 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 538 NSize = 1; 539 RegDecoder = DecodeMSA128DRegisterClass; 540 } else 541 llvm_unreachable("Invalid encoding"); 542 543 assert(NSize != 0 && RegDecoder != nullptr); 544 545 // $wd 546 tmp = fieldFromInstruction(insn, 6, 5); 547 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 548 return MCDisassembler::Fail; 549 // $wd_in 550 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 551 return MCDisassembler::Fail; 552 // $n 553 tmp = fieldFromInstruction(insn, 16, NSize); 554 MI.addOperand(MCOperand::createImm(tmp)); 555 // $ws 556 tmp = fieldFromInstruction(insn, 11, 5); 557 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 558 return MCDisassembler::Fail; 559 // $n2 560 MI.addOperand(MCOperand::createImm(0)); 561 562 return MCDisassembler::Success; 563 } 564 565 template <typename InsnType> 566 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 567 uint64_t Address, 568 const void *Decoder) { 569 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 570 // (otherwise we would have matched the ADDI instruction from the earlier 571 // ISA's instead). 572 // 573 // We have: 574 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 575 // BOVC if rs >= rt 576 // BEQZALC if rs == 0 && rt != 0 577 // BEQC if rs < rt && rs != 0 578 579 InsnType Rs = fieldFromInstruction(insn, 21, 5); 580 InsnType Rt = fieldFromInstruction(insn, 16, 5); 581 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 582 bool HasRs = false; 583 584 if (Rs >= Rt) { 585 MI.setOpcode(Mips::BOVC); 586 HasRs = true; 587 } else if (Rs != 0 && Rs < Rt) { 588 MI.setOpcode(Mips::BEQC); 589 HasRs = true; 590 } else 591 MI.setOpcode(Mips::BEQZALC); 592 593 if (HasRs) 594 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 595 Rs))); 596 597 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 598 Rt))); 599 MI.addOperand(MCOperand::createImm(Imm)); 600 601 return MCDisassembler::Success; 602 } 603 604 template <typename InsnType> 605 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 606 uint64_t Address, 607 const void *Decoder) { 608 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 609 // (otherwise we would have matched the ADDI instruction from the earlier 610 // ISA's instead). 611 // 612 // We have: 613 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 614 // BNVC if rs >= rt 615 // BNEZALC if rs == 0 && rt != 0 616 // BNEC if rs < rt && rs != 0 617 618 InsnType Rs = fieldFromInstruction(insn, 21, 5); 619 InsnType Rt = fieldFromInstruction(insn, 16, 5); 620 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 621 bool HasRs = false; 622 623 if (Rs >= Rt) { 624 MI.setOpcode(Mips::BNVC); 625 HasRs = true; 626 } else if (Rs != 0 && Rs < Rt) { 627 MI.setOpcode(Mips::BNEC); 628 HasRs = true; 629 } else 630 MI.setOpcode(Mips::BNEZALC); 631 632 if (HasRs) 633 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 634 Rs))); 635 636 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 637 Rt))); 638 MI.addOperand(MCOperand::createImm(Imm)); 639 640 return MCDisassembler::Success; 641 } 642 643 template <typename InsnType> 644 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 645 uint64_t Address, 646 const void *Decoder) { 647 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 648 // (otherwise we would have matched the BLEZL instruction from the earlier 649 // ISA's instead). 650 // 651 // We have: 652 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 653 // Invalid if rs == 0 654 // BLEZC if rs == 0 && rt != 0 655 // BGEZC if rs == rt && rt != 0 656 // BGEC if rs != rt && rs != 0 && rt != 0 657 658 InsnType Rs = fieldFromInstruction(insn, 21, 5); 659 InsnType Rt = fieldFromInstruction(insn, 16, 5); 660 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 661 bool HasRs = false; 662 663 if (Rt == 0) 664 return MCDisassembler::Fail; 665 else if (Rs == 0) 666 MI.setOpcode(Mips::BLEZC); 667 else if (Rs == Rt) 668 MI.setOpcode(Mips::BGEZC); 669 else { 670 HasRs = true; 671 MI.setOpcode(Mips::BGEC); 672 } 673 674 if (HasRs) 675 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 676 Rs))); 677 678 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 679 Rt))); 680 681 MI.addOperand(MCOperand::createImm(Imm)); 682 683 return MCDisassembler::Success; 684 } 685 686 template <typename InsnType> 687 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 688 uint64_t Address, 689 const void *Decoder) { 690 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 691 // (otherwise we would have matched the BGTZL instruction from the earlier 692 // ISA's instead). 693 // 694 // We have: 695 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 696 // Invalid if rs == 0 697 // BGTZC if rs == 0 && rt != 0 698 // BLTZC if rs == rt && rt != 0 699 // BLTC if rs != rt && rs != 0 && rt != 0 700 701 bool HasRs = false; 702 703 InsnType Rs = fieldFromInstruction(insn, 21, 5); 704 InsnType Rt = fieldFromInstruction(insn, 16, 5); 705 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 706 707 if (Rt == 0) 708 return MCDisassembler::Fail; 709 else if (Rs == 0) 710 MI.setOpcode(Mips::BGTZC); 711 else if (Rs == Rt) 712 MI.setOpcode(Mips::BLTZC); 713 else { 714 MI.setOpcode(Mips::BLTC); 715 HasRs = true; 716 } 717 718 if (HasRs) 719 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 720 Rs))); 721 722 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 723 Rt))); 724 725 MI.addOperand(MCOperand::createImm(Imm)); 726 727 return MCDisassembler::Success; 728 } 729 730 template <typename InsnType> 731 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 732 uint64_t Address, 733 const void *Decoder) { 734 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 735 // (otherwise we would have matched the BGTZ instruction from the earlier 736 // ISA's instead). 737 // 738 // We have: 739 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 740 // BGTZ if rt == 0 741 // BGTZALC if rs == 0 && rt != 0 742 // BLTZALC if rs != 0 && rs == rt 743 // BLTUC if rs != 0 && rs != rt 744 745 InsnType Rs = fieldFromInstruction(insn, 21, 5); 746 InsnType Rt = fieldFromInstruction(insn, 16, 5); 747 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 748 bool HasRs = false; 749 bool HasRt = false; 750 751 if (Rt == 0) { 752 MI.setOpcode(Mips::BGTZ); 753 HasRs = true; 754 } else if (Rs == 0) { 755 MI.setOpcode(Mips::BGTZALC); 756 HasRt = true; 757 } else if (Rs == Rt) { 758 MI.setOpcode(Mips::BLTZALC); 759 HasRs = true; 760 } else { 761 MI.setOpcode(Mips::BLTUC); 762 HasRs = true; 763 HasRt = true; 764 } 765 766 if (HasRs) 767 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 768 Rs))); 769 770 if (HasRt) 771 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 772 Rt))); 773 774 MI.addOperand(MCOperand::createImm(Imm)); 775 776 return MCDisassembler::Success; 777 } 778 779 template <typename InsnType> 780 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 781 uint64_t Address, 782 const void *Decoder) { 783 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 784 // (otherwise we would have matched the BLEZL instruction from the earlier 785 // ISA's instead). 786 // 787 // We have: 788 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 789 // Invalid if rs == 0 790 // BLEZALC if rs == 0 && rt != 0 791 // BGEZALC if rs == rt && rt != 0 792 // BGEUC if rs != rt && rs != 0 && rt != 0 793 794 InsnType Rs = fieldFromInstruction(insn, 21, 5); 795 InsnType Rt = fieldFromInstruction(insn, 16, 5); 796 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 797 bool HasRs = false; 798 799 if (Rt == 0) 800 return MCDisassembler::Fail; 801 else if (Rs == 0) 802 MI.setOpcode(Mips::BLEZALC); 803 else if (Rs == Rt) 804 MI.setOpcode(Mips::BGEZALC); 805 else { 806 HasRs = true; 807 MI.setOpcode(Mips::BGEUC); 808 } 809 810 if (HasRs) 811 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 812 Rs))); 813 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 814 Rt))); 815 816 MI.addOperand(MCOperand::createImm(Imm)); 817 818 return MCDisassembler::Success; 819 } 820 821 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 822 /// according to the given endianess. 823 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 824 uint64_t &Size, uint32_t &Insn, 825 bool IsBigEndian) { 826 // We want to read exactly 2 Bytes of data. 827 if (Bytes.size() < 2) { 828 Size = 0; 829 return MCDisassembler::Fail; 830 } 831 832 if (IsBigEndian) { 833 Insn = (Bytes[0] << 8) | Bytes[1]; 834 } else { 835 Insn = (Bytes[1] << 8) | Bytes[0]; 836 } 837 838 return MCDisassembler::Success; 839 } 840 841 /// Read four bytes from the ArrayRef and return 32 bit word sorted 842 /// according to the given endianess 843 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 844 uint64_t &Size, uint32_t &Insn, 845 bool IsBigEndian, bool IsMicroMips) { 846 // We want to read exactly 4 Bytes of data. 847 if (Bytes.size() < 4) { 848 Size = 0; 849 return MCDisassembler::Fail; 850 } 851 852 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 853 // always precede the low 16 bits in the instruction stream (that is, they 854 // are placed at lower addresses in the instruction stream). 855 // 856 // microMIPS byte ordering: 857 // Big-endian: 0 | 1 | 2 | 3 858 // Little-endian: 1 | 0 | 3 | 2 859 860 if (IsBigEndian) { 861 // Encoded as a big-endian 32-bit word in the stream. 862 Insn = 863 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 864 } else { 865 if (IsMicroMips) { 866 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 867 (Bytes[1] << 24); 868 } else { 869 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 870 (Bytes[3] << 24); 871 } 872 } 873 874 return MCDisassembler::Success; 875 } 876 877 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 878 ArrayRef<uint8_t> Bytes, 879 uint64_t Address, 880 raw_ostream &VStream, 881 raw_ostream &CStream) const { 882 uint32_t Insn; 883 DecodeStatus Result; 884 885 if (IsMicroMips) { 886 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 887 if (Result == MCDisassembler::Fail) 888 return MCDisassembler::Fail; 889 890 if (hasMips32r6()) { 891 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 892 // Calling the auto-generated decoder function for microMIPS32R6 893 // (and microMIPS64R6) 16-bit instructions. 894 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 895 Address, this, STI); 896 if (Result != MCDisassembler::Fail) { 897 Size = 2; 898 return Result; 899 } 900 } 901 902 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 903 // Calling the auto-generated decoder function for microMIPS 16-bit 904 // instructions. 905 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 906 this, STI); 907 if (Result != MCDisassembler::Fail) { 908 Size = 2; 909 return Result; 910 } 911 912 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 913 if (Result == MCDisassembler::Fail) 914 return MCDisassembler::Fail; 915 916 if (hasMips32r6()) { 917 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 918 // Calling the auto-generated decoder function. 919 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 920 this, STI); 921 if (Result != MCDisassembler::Fail) { 922 Size = 4; 923 return Result; 924 } 925 } 926 927 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 928 // Calling the auto-generated decoder function. 929 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 930 this, STI); 931 if (Result != MCDisassembler::Fail) { 932 Size = 4; 933 return Result; 934 } 935 936 if (hasMips32r6() && isFP64()) { 937 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 938 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 939 Address, this, STI); 940 if (Result != MCDisassembler::Fail) { 941 Size = 4; 942 return Result; 943 } 944 } 945 946 // This is an invalid instruction. Let the disassembler move forward by the 947 // minimum instruction size. 948 Size = 2; 949 return MCDisassembler::Fail; 950 } 951 952 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 953 if (Result == MCDisassembler::Fail) { 954 Size = 4; 955 return MCDisassembler::Fail; 956 } 957 958 if (hasCOP3()) { 959 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 960 Result = 961 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 962 if (Result != MCDisassembler::Fail) { 963 Size = 4; 964 return Result; 965 } 966 } 967 968 if (hasMips32r6() && isGP64()) { 969 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 970 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 971 Address, this, STI); 972 if (Result != MCDisassembler::Fail) { 973 Size = 4; 974 return Result; 975 } 976 } 977 978 if (hasMips32r6()) { 979 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 980 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 981 Address, this, STI); 982 if (Result != MCDisassembler::Fail) { 983 Size = 4; 984 return Result; 985 } 986 } 987 988 if (hasCnMips()) { 989 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 990 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 991 Address, this, STI); 992 if (Result != MCDisassembler::Fail) { 993 Size = 4; 994 return Result; 995 } 996 } 997 998 if (isGP64()) { 999 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1000 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1001 Address, this, STI); 1002 if (Result != MCDisassembler::Fail) { 1003 Size = 4; 1004 return Result; 1005 } 1006 } 1007 1008 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1009 // Calling the auto-generated decoder function. 1010 Result = 1011 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1012 if (Result != MCDisassembler::Fail) { 1013 Size = 4; 1014 return Result; 1015 } 1016 1017 Size = 4; 1018 return MCDisassembler::Fail; 1019 } 1020 1021 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1022 unsigned RegNo, 1023 uint64_t Address, 1024 const void *Decoder) { 1025 1026 return MCDisassembler::Fail; 1027 1028 } 1029 1030 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1031 unsigned RegNo, 1032 uint64_t Address, 1033 const void *Decoder) { 1034 1035 if (RegNo > 31) 1036 return MCDisassembler::Fail; 1037 1038 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1039 Inst.addOperand(MCOperand::createReg(Reg)); 1040 return MCDisassembler::Success; 1041 } 1042 1043 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1044 unsigned RegNo, 1045 uint64_t Address, 1046 const void *Decoder) { 1047 if (RegNo > 7) 1048 return MCDisassembler::Fail; 1049 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1050 Inst.addOperand(MCOperand::createReg(Reg)); 1051 return MCDisassembler::Success; 1052 } 1053 1054 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1055 unsigned RegNo, 1056 uint64_t Address, 1057 const void *Decoder) { 1058 if (RegNo > 7) 1059 return MCDisassembler::Fail; 1060 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1061 Inst.addOperand(MCOperand::createReg(Reg)); 1062 return MCDisassembler::Success; 1063 } 1064 1065 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1066 unsigned RegNo, 1067 uint64_t Address, 1068 const void *Decoder) { 1069 if (RegNo > 7) 1070 return MCDisassembler::Fail; 1071 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1072 Inst.addOperand(MCOperand::createReg(Reg)); 1073 return MCDisassembler::Success; 1074 } 1075 1076 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1077 unsigned RegNo, 1078 uint64_t Address, 1079 const void *Decoder) { 1080 if (RegNo > 31) 1081 return MCDisassembler::Fail; 1082 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1083 Inst.addOperand(MCOperand::createReg(Reg)); 1084 return MCDisassembler::Success; 1085 } 1086 1087 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1088 unsigned RegNo, 1089 uint64_t Address, 1090 const void *Decoder) { 1091 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1092 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1093 1094 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1095 } 1096 1097 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1098 unsigned RegNo, 1099 uint64_t Address, 1100 const void *Decoder) { 1101 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1102 } 1103 1104 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1105 unsigned RegNo, 1106 uint64_t Address, 1107 const void *Decoder) { 1108 if (RegNo > 31) 1109 return MCDisassembler::Fail; 1110 1111 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1112 Inst.addOperand(MCOperand::createReg(Reg)); 1113 return MCDisassembler::Success; 1114 } 1115 1116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1117 unsigned RegNo, 1118 uint64_t Address, 1119 const void *Decoder) { 1120 if (RegNo > 31) 1121 return MCDisassembler::Fail; 1122 1123 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1124 Inst.addOperand(MCOperand::createReg(Reg)); 1125 return MCDisassembler::Success; 1126 } 1127 1128 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1129 unsigned RegNo, 1130 uint64_t Address, 1131 const void *Decoder) { 1132 if (RegNo > 31) 1133 return MCDisassembler::Fail; 1134 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1135 Inst.addOperand(MCOperand::createReg(Reg)); 1136 return MCDisassembler::Success; 1137 } 1138 1139 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1140 unsigned RegNo, 1141 uint64_t Address, 1142 const void *Decoder) { 1143 if (RegNo > 7) 1144 return MCDisassembler::Fail; 1145 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1146 Inst.addOperand(MCOperand::createReg(Reg)); 1147 return MCDisassembler::Success; 1148 } 1149 1150 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1151 uint64_t Address, 1152 const void *Decoder) { 1153 if (RegNo > 31) 1154 return MCDisassembler::Fail; 1155 1156 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1157 Inst.addOperand(MCOperand::createReg(Reg)); 1158 return MCDisassembler::Success; 1159 } 1160 1161 static DecodeStatus DecodeMem(MCInst &Inst, 1162 unsigned Insn, 1163 uint64_t Address, 1164 const void *Decoder) { 1165 int Offset = SignExtend32<16>(Insn & 0xffff); 1166 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1167 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1168 1169 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1170 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1171 1172 if (Inst.getOpcode() == Mips::SC || 1173 Inst.getOpcode() == Mips::SCD) 1174 Inst.addOperand(MCOperand::createReg(Reg)); 1175 1176 Inst.addOperand(MCOperand::createReg(Reg)); 1177 Inst.addOperand(MCOperand::createReg(Base)); 1178 Inst.addOperand(MCOperand::createImm(Offset)); 1179 1180 return MCDisassembler::Success; 1181 } 1182 1183 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1184 unsigned Insn, 1185 uint64_t Address, 1186 const void *Decoder) { 1187 int Offset = SignExtend32<9>(Insn >> 7); 1188 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1189 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1190 1191 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1192 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1193 1194 if (Inst.getOpcode() == Mips::SCE) 1195 Inst.addOperand(MCOperand::createReg(Reg)); 1196 1197 Inst.addOperand(MCOperand::createReg(Reg)); 1198 Inst.addOperand(MCOperand::createReg(Base)); 1199 Inst.addOperand(MCOperand::createImm(Offset)); 1200 1201 return MCDisassembler::Success; 1202 } 1203 1204 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1205 unsigned Insn, 1206 uint64_t Address, 1207 const void *Decoder) { 1208 int Offset = SignExtend32<9>(Insn & 0x1ff); 1209 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1210 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1211 1212 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1213 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1214 1215 Inst.addOperand(MCOperand::createReg(Reg)); 1216 Inst.addOperand(MCOperand::createReg(Base)); 1217 Inst.addOperand(MCOperand::createImm(Offset)); 1218 1219 return MCDisassembler::Success; 1220 } 1221 1222 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1223 unsigned Insn, 1224 uint64_t Address, 1225 const void *Decoder) { 1226 int Offset = SignExtend32<16>(Insn & 0xffff); 1227 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1228 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1229 1230 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1231 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1232 1233 Inst.addOperand(MCOperand::createReg(Reg)); 1234 Inst.addOperand(MCOperand::createReg(Base)); 1235 Inst.addOperand(MCOperand::createImm(Offset)); 1236 1237 return MCDisassembler::Success; 1238 } 1239 1240 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1241 unsigned Insn, 1242 uint64_t Address, 1243 const void *Decoder) { 1244 int Offset = SignExtend32<16>(Insn & 0xffff); 1245 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1246 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1247 1248 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1249 1250 Inst.addOperand(MCOperand::createReg(Base)); 1251 Inst.addOperand(MCOperand::createImm(Offset)); 1252 Inst.addOperand(MCOperand::createImm(Hint)); 1253 1254 return MCDisassembler::Success; 1255 } 1256 1257 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1258 unsigned Insn, 1259 uint64_t Address, 1260 const void *Decoder) { 1261 int Offset = SignExtend32<12>(Insn & 0xfff); 1262 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1263 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1264 1265 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1266 1267 Inst.addOperand(MCOperand::createReg(Base)); 1268 Inst.addOperand(MCOperand::createImm(Offset)); 1269 Inst.addOperand(MCOperand::createImm(Hint)); 1270 1271 return MCDisassembler::Success; 1272 } 1273 1274 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1275 unsigned Insn, 1276 uint64_t Address, 1277 const void *Decoder) { 1278 int Offset = SignExtend32<9>(Insn & 0x1ff); 1279 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1280 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1281 1282 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1283 1284 Inst.addOperand(MCOperand::createReg(Base)); 1285 Inst.addOperand(MCOperand::createImm(Offset)); 1286 Inst.addOperand(MCOperand::createImm(Hint)); 1287 1288 return MCDisassembler::Success; 1289 } 1290 1291 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1292 unsigned Insn, 1293 uint64_t Address, 1294 const void *Decoder) { 1295 int Offset = SignExtend32<9>(Insn >> 7); 1296 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1297 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1298 1299 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1300 1301 Inst.addOperand(MCOperand::createReg(Base)); 1302 Inst.addOperand(MCOperand::createImm(Offset)); 1303 Inst.addOperand(MCOperand::createImm(Hint)); 1304 1305 return MCDisassembler::Success; 1306 } 1307 1308 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1309 unsigned Insn, 1310 uint64_t Address, 1311 const void *Decoder) { 1312 int Offset = SignExtend32<9>(Insn & 0x1ff); 1313 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1314 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1315 1316 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1317 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1318 1319 Inst.addOperand(MCOperand::createReg(Reg)); 1320 Inst.addOperand(MCOperand::createReg(Base)); 1321 Inst.addOperand(MCOperand::createImm(Offset)); 1322 1323 return MCDisassembler::Success; 1324 } 1325 1326 static DecodeStatus DecodeSyncI(MCInst &Inst, 1327 unsigned Insn, 1328 uint64_t Address, 1329 const void *Decoder) { 1330 int Offset = SignExtend32<16>(Insn & 0xffff); 1331 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1332 1333 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1334 1335 Inst.addOperand(MCOperand::createReg(Base)); 1336 Inst.addOperand(MCOperand::createImm(Offset)); 1337 1338 return MCDisassembler::Success; 1339 } 1340 1341 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1342 unsigned Insn, 1343 uint64_t Address, 1344 const void *Decoder) { 1345 int Immediate = SignExtend32<16>(Insn & 0xffff); 1346 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1347 1348 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1349 1350 Inst.addOperand(MCOperand::createReg(Base)); 1351 Inst.addOperand(MCOperand::createImm(Immediate)); 1352 1353 return MCDisassembler::Success; 1354 } 1355 1356 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1357 uint64_t Address, const void *Decoder) { 1358 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1359 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1360 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1361 1362 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1363 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1364 1365 Inst.addOperand(MCOperand::createReg(Reg)); 1366 Inst.addOperand(MCOperand::createReg(Base)); 1367 1368 // The immediate field of an LD/ST instruction is scaled which means it must 1369 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1370 // data format. 1371 // .b - 1 byte 1372 // .h - 2 bytes 1373 // .w - 4 bytes 1374 // .d - 8 bytes 1375 switch(Inst.getOpcode()) 1376 { 1377 default: 1378 assert (0 && "Unexpected instruction"); 1379 return MCDisassembler::Fail; 1380 break; 1381 case Mips::LD_B: 1382 case Mips::ST_B: 1383 Inst.addOperand(MCOperand::createImm(Offset)); 1384 break; 1385 case Mips::LD_H: 1386 case Mips::ST_H: 1387 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1388 break; 1389 case Mips::LD_W: 1390 case Mips::ST_W: 1391 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1392 break; 1393 case Mips::LD_D: 1394 case Mips::ST_D: 1395 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1396 break; 1397 } 1398 1399 return MCDisassembler::Success; 1400 } 1401 1402 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1403 unsigned Insn, 1404 uint64_t Address, 1405 const void *Decoder) { 1406 unsigned Offset = Insn & 0xf; 1407 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1408 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1409 1410 switch (Inst.getOpcode()) { 1411 case Mips::LBU16_MM: 1412 case Mips::LHU16_MM: 1413 case Mips::LW16_MM: 1414 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1415 == MCDisassembler::Fail) 1416 return MCDisassembler::Fail; 1417 break; 1418 case Mips::SB16_MM: 1419 case Mips::SB16_MMR6: 1420 case Mips::SH16_MM: 1421 case Mips::SH16_MMR6: 1422 case Mips::SW16_MM: 1423 case Mips::SW16_MMR6: 1424 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1425 == MCDisassembler::Fail) 1426 return MCDisassembler::Fail; 1427 break; 1428 } 1429 1430 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1431 == MCDisassembler::Fail) 1432 return MCDisassembler::Fail; 1433 1434 switch (Inst.getOpcode()) { 1435 case Mips::LBU16_MM: 1436 if (Offset == 0xf) 1437 Inst.addOperand(MCOperand::createImm(-1)); 1438 else 1439 Inst.addOperand(MCOperand::createImm(Offset)); 1440 break; 1441 case Mips::SB16_MM: 1442 case Mips::SB16_MMR6: 1443 Inst.addOperand(MCOperand::createImm(Offset)); 1444 break; 1445 case Mips::LHU16_MM: 1446 case Mips::SH16_MM: 1447 case Mips::SH16_MMR6: 1448 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1449 break; 1450 case Mips::LW16_MM: 1451 case Mips::SW16_MM: 1452 case Mips::SW16_MMR6: 1453 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1454 break; 1455 } 1456 1457 return MCDisassembler::Success; 1458 } 1459 1460 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1461 unsigned Insn, 1462 uint64_t Address, 1463 const void *Decoder) { 1464 unsigned Offset = Insn & 0x1F; 1465 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1466 1467 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1468 1469 Inst.addOperand(MCOperand::createReg(Reg)); 1470 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1471 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1472 1473 return MCDisassembler::Success; 1474 } 1475 1476 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1477 unsigned Insn, 1478 uint64_t Address, 1479 const void *Decoder) { 1480 unsigned Offset = Insn & 0x7F; 1481 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1482 1483 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1484 1485 Inst.addOperand(MCOperand::createReg(Reg)); 1486 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1487 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1488 1489 return MCDisassembler::Success; 1490 } 1491 1492 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1493 unsigned Insn, 1494 uint64_t Address, 1495 const void *Decoder) { 1496 int Offset; 1497 switch (Inst.getOpcode()) { 1498 case Mips::LWM16_MMR6: 1499 case Mips::SWM16_MMR6: 1500 Offset = fieldFromInstruction(Insn, 4, 4); 1501 break; 1502 default: 1503 Offset = SignExtend32<4>(Insn & 0xf); 1504 break; 1505 } 1506 1507 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1508 == MCDisassembler::Fail) 1509 return MCDisassembler::Fail; 1510 1511 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1512 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1513 1514 return MCDisassembler::Success; 1515 } 1516 1517 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1518 unsigned Insn, 1519 uint64_t Address, 1520 const void *Decoder) { 1521 int Offset = SignExtend32<9>(Insn & 0x1ff); 1522 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1523 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1524 1525 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1526 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1527 1528 if (Inst.getOpcode() == Mips::SCE_MM) 1529 Inst.addOperand(MCOperand::createReg(Reg)); 1530 1531 Inst.addOperand(MCOperand::createReg(Reg)); 1532 Inst.addOperand(MCOperand::createReg(Base)); 1533 Inst.addOperand(MCOperand::createImm(Offset)); 1534 1535 return MCDisassembler::Success; 1536 } 1537 1538 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1539 unsigned Insn, 1540 uint64_t Address, 1541 const void *Decoder) { 1542 int Offset = SignExtend32<12>(Insn & 0x0fff); 1543 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1544 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1545 1546 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1547 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1548 1549 switch (Inst.getOpcode()) { 1550 case Mips::SWM32_MM: 1551 case Mips::LWM32_MM: 1552 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1553 == MCDisassembler::Fail) 1554 return MCDisassembler::Fail; 1555 Inst.addOperand(MCOperand::createReg(Base)); 1556 Inst.addOperand(MCOperand::createImm(Offset)); 1557 break; 1558 case Mips::SC_MM: 1559 Inst.addOperand(MCOperand::createReg(Reg)); 1560 // fallthrough 1561 default: 1562 Inst.addOperand(MCOperand::createReg(Reg)); 1563 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1564 Inst.addOperand(MCOperand::createReg(Reg+1)); 1565 1566 Inst.addOperand(MCOperand::createReg(Base)); 1567 Inst.addOperand(MCOperand::createImm(Offset)); 1568 } 1569 1570 return MCDisassembler::Success; 1571 } 1572 1573 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1574 unsigned Insn, 1575 uint64_t Address, 1576 const void *Decoder) { 1577 int Offset = SignExtend32<16>(Insn & 0xffff); 1578 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1579 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1580 1581 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1582 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1583 1584 Inst.addOperand(MCOperand::createReg(Reg)); 1585 Inst.addOperand(MCOperand::createReg(Base)); 1586 Inst.addOperand(MCOperand::createImm(Offset)); 1587 1588 return MCDisassembler::Success; 1589 } 1590 1591 static DecodeStatus DecodeFMem(MCInst &Inst, 1592 unsigned Insn, 1593 uint64_t Address, 1594 const void *Decoder) { 1595 int Offset = SignExtend32<16>(Insn & 0xffff); 1596 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1597 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1598 1599 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1600 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1601 1602 Inst.addOperand(MCOperand::createReg(Reg)); 1603 Inst.addOperand(MCOperand::createReg(Base)); 1604 Inst.addOperand(MCOperand::createImm(Offset)); 1605 1606 return MCDisassembler::Success; 1607 } 1608 1609 static DecodeStatus DecodeFMemMMR6(MCInst &Inst, unsigned Insn, 1610 uint64_t Address, const void *Decoder) { 1611 int Offset = SignExtend32<16>(Insn & 0xffff); 1612 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1613 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1614 1615 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1616 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1617 1618 Inst.addOperand(MCOperand::createReg(Reg)); 1619 Inst.addOperand(MCOperand::createReg(Base)); 1620 Inst.addOperand(MCOperand::createImm(Offset)); 1621 1622 return MCDisassembler::Success; 1623 } 1624 1625 static DecodeStatus DecodeFMem2(MCInst &Inst, 1626 unsigned Insn, 1627 uint64_t Address, 1628 const void *Decoder) { 1629 int Offset = SignExtend32<16>(Insn & 0xffff); 1630 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1631 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1632 1633 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1634 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1635 1636 Inst.addOperand(MCOperand::createReg(Reg)); 1637 Inst.addOperand(MCOperand::createReg(Base)); 1638 Inst.addOperand(MCOperand::createImm(Offset)); 1639 1640 return MCDisassembler::Success; 1641 } 1642 1643 static DecodeStatus DecodeFMem3(MCInst &Inst, 1644 unsigned Insn, 1645 uint64_t Address, 1646 const void *Decoder) { 1647 int Offset = SignExtend32<16>(Insn & 0xffff); 1648 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1649 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1650 1651 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1652 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1653 1654 Inst.addOperand(MCOperand::createReg(Reg)); 1655 Inst.addOperand(MCOperand::createReg(Base)); 1656 Inst.addOperand(MCOperand::createImm(Offset)); 1657 1658 return MCDisassembler::Success; 1659 } 1660 1661 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1662 unsigned Insn, 1663 uint64_t Address, 1664 const void *Decoder) { 1665 int Offset = SignExtend32<11>(Insn & 0x07ff); 1666 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1667 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1668 1669 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1670 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1671 1672 Inst.addOperand(MCOperand::createReg(Reg)); 1673 Inst.addOperand(MCOperand::createReg(Base)); 1674 Inst.addOperand(MCOperand::createImm(Offset)); 1675 1676 return MCDisassembler::Success; 1677 } 1678 1679 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 1680 uint64_t Address, const void *Decoder) { 1681 int Offset = SignExtend32<11>(Insn & 0x07ff); 1682 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1683 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1684 1685 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1686 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1687 1688 Inst.addOperand(MCOperand::createReg(Reg)); 1689 Inst.addOperand(MCOperand::createReg(Base)); 1690 Inst.addOperand(MCOperand::createImm(Offset)); 1691 1692 return MCDisassembler::Success; 1693 } 1694 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1695 unsigned Insn, 1696 uint64_t Address, 1697 const void *Decoder) { 1698 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1699 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1700 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1701 1702 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1703 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1704 1705 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1706 Inst.addOperand(MCOperand::createReg(Rt)); 1707 } 1708 1709 Inst.addOperand(MCOperand::createReg(Rt)); 1710 Inst.addOperand(MCOperand::createReg(Base)); 1711 Inst.addOperand(MCOperand::createImm(Offset)); 1712 1713 return MCDisassembler::Success; 1714 } 1715 1716 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1717 unsigned RegNo, 1718 uint64_t Address, 1719 const void *Decoder) { 1720 // Currently only hardware register 29 is supported. 1721 if (RegNo != 29) 1722 return MCDisassembler::Fail; 1723 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1724 return MCDisassembler::Success; 1725 } 1726 1727 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1728 unsigned RegNo, 1729 uint64_t Address, 1730 const void *Decoder) { 1731 if (RegNo > 30 || RegNo %2) 1732 return MCDisassembler::Fail; 1733 1734 ; 1735 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1736 Inst.addOperand(MCOperand::createReg(Reg)); 1737 return MCDisassembler::Success; 1738 } 1739 1740 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1741 unsigned RegNo, 1742 uint64_t Address, 1743 const void *Decoder) { 1744 if (RegNo >= 4) 1745 return MCDisassembler::Fail; 1746 1747 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1748 Inst.addOperand(MCOperand::createReg(Reg)); 1749 return MCDisassembler::Success; 1750 } 1751 1752 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1753 unsigned RegNo, 1754 uint64_t Address, 1755 const void *Decoder) { 1756 if (RegNo >= 4) 1757 return MCDisassembler::Fail; 1758 1759 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1760 Inst.addOperand(MCOperand::createReg(Reg)); 1761 return MCDisassembler::Success; 1762 } 1763 1764 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1765 unsigned RegNo, 1766 uint64_t Address, 1767 const void *Decoder) { 1768 if (RegNo >= 4) 1769 return MCDisassembler::Fail; 1770 1771 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1772 Inst.addOperand(MCOperand::createReg(Reg)); 1773 return MCDisassembler::Success; 1774 } 1775 1776 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1777 unsigned RegNo, 1778 uint64_t Address, 1779 const void *Decoder) { 1780 if (RegNo > 31) 1781 return MCDisassembler::Fail; 1782 1783 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1784 Inst.addOperand(MCOperand::createReg(Reg)); 1785 return MCDisassembler::Success; 1786 } 1787 1788 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1789 unsigned RegNo, 1790 uint64_t Address, 1791 const void *Decoder) { 1792 if (RegNo > 31) 1793 return MCDisassembler::Fail; 1794 1795 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1796 Inst.addOperand(MCOperand::createReg(Reg)); 1797 return MCDisassembler::Success; 1798 } 1799 1800 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1801 unsigned RegNo, 1802 uint64_t Address, 1803 const void *Decoder) { 1804 if (RegNo > 31) 1805 return MCDisassembler::Fail; 1806 1807 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1808 Inst.addOperand(MCOperand::createReg(Reg)); 1809 return MCDisassembler::Success; 1810 } 1811 1812 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1813 unsigned RegNo, 1814 uint64_t Address, 1815 const void *Decoder) { 1816 if (RegNo > 31) 1817 return MCDisassembler::Fail; 1818 1819 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1820 Inst.addOperand(MCOperand::createReg(Reg)); 1821 return MCDisassembler::Success; 1822 } 1823 1824 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1825 unsigned RegNo, 1826 uint64_t Address, 1827 const void *Decoder) { 1828 if (RegNo > 7) 1829 return MCDisassembler::Fail; 1830 1831 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1832 Inst.addOperand(MCOperand::createReg(Reg)); 1833 return MCDisassembler::Success; 1834 } 1835 1836 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 1837 unsigned RegNo, 1838 uint64_t Address, 1839 const void *Decoder) { 1840 if (RegNo > 31) 1841 return MCDisassembler::Fail; 1842 1843 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 1844 Inst.addOperand(MCOperand::createReg(Reg)); 1845 return MCDisassembler::Success; 1846 } 1847 1848 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1849 unsigned RegNo, 1850 uint64_t Address, 1851 const void *Decoder) { 1852 if (RegNo > 31) 1853 return MCDisassembler::Fail; 1854 1855 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1856 Inst.addOperand(MCOperand::createReg(Reg)); 1857 return MCDisassembler::Success; 1858 } 1859 1860 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1861 unsigned Offset, 1862 uint64_t Address, 1863 const void *Decoder) { 1864 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1865 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1866 return MCDisassembler::Success; 1867 } 1868 1869 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1870 unsigned Insn, 1871 uint64_t Address, 1872 const void *Decoder) { 1873 1874 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1875 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1876 return MCDisassembler::Success; 1877 } 1878 1879 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1880 unsigned Offset, 1881 uint64_t Address, 1882 const void *Decoder) { 1883 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1884 1885 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1886 return MCDisassembler::Success; 1887 } 1888 1889 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1890 unsigned Offset, 1891 uint64_t Address, 1892 const void *Decoder) { 1893 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1894 1895 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1896 return MCDisassembler::Success; 1897 } 1898 1899 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1900 unsigned Offset, 1901 uint64_t Address, 1902 const void *Decoder) { 1903 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1904 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1905 return MCDisassembler::Success; 1906 } 1907 1908 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1909 unsigned Offset, 1910 uint64_t Address, 1911 const void *Decoder) { 1912 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1913 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1914 return MCDisassembler::Success; 1915 } 1916 1917 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1918 unsigned Offset, 1919 uint64_t Address, 1920 const void *Decoder) { 1921 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1922 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1923 return MCDisassembler::Success; 1924 } 1925 1926 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 1927 unsigned Offset, 1928 uint64_t Address, 1929 const void *Decoder) { 1930 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 1931 1932 Inst.addOperand(MCOperand::createImm(BranchOffset)); 1933 return MCDisassembler::Success; 1934 } 1935 1936 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1937 unsigned Insn, 1938 uint64_t Address, 1939 const void *Decoder) { 1940 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1941 Inst.addOperand(MCOperand::createImm(JumpOffset)); 1942 return MCDisassembler::Success; 1943 } 1944 1945 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1946 unsigned Value, 1947 uint64_t Address, 1948 const void *Decoder) { 1949 if (Value == 0) 1950 Inst.addOperand(MCOperand::createImm(1)); 1951 else if (Value == 0x7) 1952 Inst.addOperand(MCOperand::createImm(-1)); 1953 else 1954 Inst.addOperand(MCOperand::createImm(Value << 2)); 1955 return MCDisassembler::Success; 1956 } 1957 1958 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 1959 unsigned Value, 1960 uint64_t Address, 1961 const void *Decoder) { 1962 if (Value == 0x7F) 1963 Inst.addOperand(MCOperand::createImm(-1)); 1964 else 1965 Inst.addOperand(MCOperand::createImm(Value)); 1966 return MCDisassembler::Success; 1967 } 1968 1969 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 1970 unsigned Value, 1971 uint64_t Address, 1972 const void *Decoder) { 1973 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 1974 return MCDisassembler::Success; 1975 } 1976 1977 template <unsigned Bits, int Offset, int Scale> 1978 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1979 uint64_t Address, 1980 const void *Decoder) { 1981 Value &= ((1 << Bits) - 1); 1982 Value *= Scale; 1983 Inst.addOperand(MCOperand::createImm(Value + Offset)); 1984 return MCDisassembler::Success; 1985 } 1986 1987 template <unsigned Bits, int Offset, int ScaleBy> 1988 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 1989 uint64_t Address, 1990 const void *Decoder) { 1991 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 1992 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 1993 return MCDisassembler::Success; 1994 } 1995 1996 static DecodeStatus DecodeInsSize(MCInst &Inst, 1997 unsigned Insn, 1998 uint64_t Address, 1999 const void *Decoder) { 2000 // First we need to grab the pos(lsb) from MCInst. 2001 int Pos = Inst.getOperand(2).getImm(); 2002 int Size = (int) Insn - Pos + 1; 2003 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2004 return MCDisassembler::Success; 2005 } 2006 2007 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2008 uint64_t Address, const void *Decoder) { 2009 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2010 return MCDisassembler::Success; 2011 } 2012 2013 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2014 uint64_t Address, const void *Decoder) { 2015 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2016 return MCDisassembler::Success; 2017 } 2018 2019 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2020 uint64_t Address, const void *Decoder) { 2021 int32_t DecodedValue; 2022 switch (Insn) { 2023 case 0: DecodedValue = 256; break; 2024 case 1: DecodedValue = 257; break; 2025 case 510: DecodedValue = -258; break; 2026 case 511: DecodedValue = -257; break; 2027 default: DecodedValue = SignExtend32<9>(Insn); break; 2028 } 2029 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2030 return MCDisassembler::Success; 2031 } 2032 2033 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2034 uint64_t Address, const void *Decoder) { 2035 // Insn must be >= 0, since it is unsigned that condition is always true. 2036 assert(Insn < 16); 2037 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2038 255, 32768, 65535}; 2039 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2040 return MCDisassembler::Success; 2041 } 2042 2043 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2044 unsigned Insn, 2045 uint64_t Address, 2046 const void *Decoder) { 2047 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2048 Mips::S6, Mips::S7, Mips::FP}; 2049 unsigned RegNum; 2050 2051 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2052 2053 // Empty register lists are not allowed. 2054 if (RegLst == 0) 2055 return MCDisassembler::Fail; 2056 2057 RegNum = RegLst & 0xf; 2058 2059 // RegLst values 10-15, and 26-31 are reserved. 2060 if (RegNum > 9) 2061 return MCDisassembler::Fail; 2062 2063 for (unsigned i = 0; i < RegNum; i++) 2064 Inst.addOperand(MCOperand::createReg(Regs[i])); 2065 2066 if (RegLst & 0x10) 2067 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2068 2069 return MCDisassembler::Success; 2070 } 2071 2072 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2073 uint64_t Address, 2074 const void *Decoder) { 2075 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2076 unsigned RegLst; 2077 switch(Inst.getOpcode()) { 2078 default: 2079 RegLst = fieldFromInstruction(Insn, 4, 2); 2080 break; 2081 case Mips::LWM16_MMR6: 2082 case Mips::SWM16_MMR6: 2083 RegLst = fieldFromInstruction(Insn, 8, 2); 2084 break; 2085 } 2086 unsigned RegNum = RegLst & 0x3; 2087 2088 for (unsigned i = 0; i <= RegNum; i++) 2089 Inst.addOperand(MCOperand::createReg(Regs[i])); 2090 2091 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2092 2093 return MCDisassembler::Success; 2094 } 2095 2096 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2097 uint64_t Address, const void *Decoder) { 2098 2099 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2100 2101 switch (RegPair) { 2102 default: 2103 return MCDisassembler::Fail; 2104 case 0: 2105 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2106 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2107 break; 2108 case 1: 2109 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2110 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2111 break; 2112 case 2: 2113 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2114 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2115 break; 2116 case 3: 2117 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2118 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2119 break; 2120 case 4: 2121 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2122 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2123 break; 2124 case 5: 2125 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2126 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2127 break; 2128 case 6: 2129 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2130 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2131 break; 2132 case 7: 2133 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2134 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2135 break; 2136 } 2137 2138 return MCDisassembler::Success; 2139 } 2140 2141 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2142 uint64_t Address, const void *Decoder) { 2143 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2144 return MCDisassembler::Success; 2145 } 2146 2147 template <typename InsnType> 2148 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2149 uint64_t Address, 2150 const void *Decoder) { 2151 // We have: 2152 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2153 // Invalid if rt == 0 2154 // BGTZALC_MMR6 if rs == 0 && rt != 0 2155 // BLTZALC_MMR6 if rs != 0 && rs == rt 2156 // BLTUC_MMR6 if rs != 0 && rs != rt 2157 2158 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2159 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2160 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2161 bool HasRs = false; 2162 bool HasRt = false; 2163 2164 if (Rt == 0) 2165 return MCDisassembler::Fail; 2166 else if (Rs == 0) { 2167 MI.setOpcode(Mips::BGTZALC_MMR6); 2168 HasRt = true; 2169 } 2170 else if (Rs == Rt) { 2171 MI.setOpcode(Mips::BLTZALC_MMR6); 2172 HasRs = true; 2173 } 2174 else { 2175 MI.setOpcode(Mips::BLTUC_MMR6); 2176 HasRs = true; 2177 HasRt = true; 2178 } 2179 2180 if (HasRs) 2181 MI.addOperand( 2182 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2183 2184 if (HasRt) 2185 MI.addOperand( 2186 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2187 2188 MI.addOperand(MCOperand::createImm(Imm)); 2189 2190 return MCDisassembler::Success; 2191 } 2192 2193 template <typename InsnType> 2194 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2195 uint64_t Address, 2196 const void *Decoder) { 2197 // We have: 2198 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2199 // Invalid if rs == 0 2200 // BLEZALC_MMR6 if rs == 0 && rt != 0 2201 // BGEZALC_MMR6 if rs == rt && rt != 0 2202 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2203 2204 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2205 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2206 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; 2207 bool HasRs = false; 2208 2209 if (Rt == 0) 2210 return MCDisassembler::Fail; 2211 else if (Rs == 0) 2212 MI.setOpcode(Mips::BLEZALC_MMR6); 2213 else if (Rs == Rt) 2214 MI.setOpcode(Mips::BGEZALC_MMR6); 2215 else { 2216 HasRs = true; 2217 MI.setOpcode(Mips::BGEUC_MMR6); 2218 } 2219 2220 if (HasRs) 2221 MI.addOperand( 2222 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2223 MI.addOperand( 2224 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2225 2226 MI.addOperand(MCOperand::createImm(Imm)); 2227 2228 return MCDisassembler::Success; 2229 } 2230