1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/MipsMCTargetDesc.h" 15 #include "Mips.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCOP3() const { 67 // Only present in MIPS-I and MIPS-II 68 return !hasMips32() && !hasMips3(); 69 } 70 71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 72 ArrayRef<uint8_t> Bytes, uint64_t Address, 73 raw_ostream &VStream, 74 raw_ostream &CStream) const override; 75 }; 76 77 } // end anonymous namespace 78 79 // Forward declare these because the autogenerated code will reference them. 80 // Definitions are further down. 81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 102 unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 112 unsigned Insn, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 132 unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 146 unsigned Insn, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 201 unsigned RegNo, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 206 unsigned Offset, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 216 unsigned Insn, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 226 unsigned Offset, 227 uint64_t Address, 228 const void *Decoder); 229 230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 231 unsigned Offset, 232 uint64_t Address, 233 const void *Decoder); 234 235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 236 // shifted left by 1 bit. 237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 238 unsigned Offset, 239 uint64_t Address, 240 const void *Decoder); 241 242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 243 // shifted left by 1 bit. 244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 245 unsigned Offset, 246 uint64_t Address, 247 const void *Decoder); 248 249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 250 // shifted left by 1 bit. 251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 252 unsigned Offset, 253 uint64_t Address, 254 const void *Decoder); 255 256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 257 // shifted left by 1 bit. 258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 259 unsigned Offset, 260 uint64_t Address, 261 const void *Decoder); 262 263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 264 // shifted left by 1 bit. 265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeMem(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeMemEVA(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 286 const void *Decoder); 287 288 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 289 unsigned Insn, 290 uint64_t Address, 291 const void *Decoder); 292 293 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 294 unsigned Insn, 295 uint64_t Address, 296 const void *Decoder); 297 298 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 299 unsigned Insn, 300 uint64_t Address, 301 const void *Decoder); 302 303 static DecodeStatus DecodeSyncI(MCInst &Inst, 304 unsigned Insn, 305 uint64_t Address, 306 const void *Decoder); 307 308 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, 309 unsigned Insn, 310 uint64_t Address, 311 const void *Decoder); 312 313 static DecodeStatus DecodeSynciR6(MCInst &Inst, 314 unsigned Insn, 315 uint64_t Address, 316 const void *Decoder); 317 318 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 321 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 322 unsigned Insn, 323 uint64_t Address, 324 const void *Decoder); 325 326 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 327 unsigned Insn, 328 uint64_t Address, 329 const void *Decoder); 330 331 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 332 unsigned Insn, 333 uint64_t Address, 334 const void *Decoder); 335 336 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 337 unsigned Insn, 338 uint64_t Address, 339 const void *Decoder); 340 341 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 342 unsigned Insn, 343 uint64_t Address, 344 const void *Decoder); 345 346 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 347 unsigned Insn, 348 uint64_t Address, 349 const void *Decoder); 350 351 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 352 unsigned Insn, 353 uint64_t Address, 354 const void *Decoder); 355 356 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 357 uint64_t Address, 358 const void *Decoder); 359 360 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 361 uint64_t Address, 362 const void *Decoder); 363 364 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 365 const void *Decoder); 366 367 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 368 const void *Decoder); 369 370 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 373 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 374 uint64_t Address, 375 const void *Decoder); 376 377 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 378 unsigned Insn, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 383 unsigned Value, 384 uint64_t Address, 385 const void *Decoder); 386 387 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 388 unsigned Value, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 393 unsigned Value, 394 uint64_t Address, 395 const void *Decoder); 396 397 template <unsigned Bits, int Offset, int Scale> 398 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 399 uint64_t Address, 400 const void *Decoder); 401 402 template <unsigned Bits, int Offset> 403 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 404 uint64_t Address, 405 const void *Decoder) { 406 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 407 Decoder); 408 } 409 410 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 411 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 412 uint64_t Address, 413 const void *Decoder); 414 415 static DecodeStatus DecodeInsSize(MCInst &Inst, 416 unsigned Insn, 417 uint64_t Address, 418 const void *Decoder); 419 420 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 421 uint64_t Address, const void *Decoder); 422 423 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 424 uint64_t Address, const void *Decoder); 425 426 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void *Decoder); 428 429 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 430 uint64_t Address, const void *Decoder); 431 432 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 433 uint64_t Address, const void *Decoder); 434 435 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 436 /// handle. 437 template <typename InsnType> 438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 439 const void *Decoder); 440 441 template <typename InsnType> 442 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 443 const void *Decoder); 444 445 template <typename InsnType> 446 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 447 const void *Decoder); 448 449 template <typename InsnType> 450 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 451 const void *Decoder); 452 453 template <typename InsnType> 454 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 455 const void *Decoder); 456 457 template <typename InsnType> 458 static DecodeStatus 459 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 460 const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus 464 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 465 const void *Decoder); 466 467 template <typename InsnType> 468 static DecodeStatus 469 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 470 const void *Decoder); 471 472 template <typename InsnType> 473 static DecodeStatus 474 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 475 const void *Decoder); 476 477 template <typename InsnType> 478 static DecodeStatus 479 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 480 const void *Decoder); 481 482 template <typename InsnType> 483 static DecodeStatus 484 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 485 const void *Decoder); 486 487 template <typename InsnType> 488 static DecodeStatus 489 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 490 const void *Decoder); 491 492 template <typename InsnType> 493 static DecodeStatus 494 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 495 const void *Decoder); 496 497 template <typename InsnType> 498 static DecodeStatus 499 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 500 const void *Decoder); 501 502 template <typename InsnType> 503 static DecodeStatus 504 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 505 const void *Decoder); 506 507 template <typename InsnType> 508 static DecodeStatus 509 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 510 const void *Decoder); 511 512 template <typename InsnType> 513 static DecodeStatus 514 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 515 const void *Decoder); 516 517 template <typename InsnType> 518 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 519 const void *Decoder); 520 521 template <typename InsnType> 522 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 523 const void *Decoder); 524 525 template <typename InsnType> 526 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 527 const void *Decoder); 528 529 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 530 uint64_t Address, 531 const void *Decoder); 532 533 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 534 uint64_t Address, 535 const void *Decoder); 536 537 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 538 uint64_t Address, 539 const void *Decoder); 540 541 namespace llvm { 542 543 Target &getTheMipselTarget(); 544 Target &getTheMipsTarget(); 545 Target &getTheMips64Target(); 546 Target &getTheMips64elTarget(); 547 548 } // end namespace llvm 549 550 static MCDisassembler *createMipsDisassembler( 551 const Target &T, 552 const MCSubtargetInfo &STI, 553 MCContext &Ctx) { 554 return new MipsDisassembler(STI, Ctx, true); 555 } 556 557 static MCDisassembler *createMipselDisassembler( 558 const Target &T, 559 const MCSubtargetInfo &STI, 560 MCContext &Ctx) { 561 return new MipsDisassembler(STI, Ctx, false); 562 } 563 564 extern "C" void LLVMInitializeMipsDisassembler() { 565 // Register the disassembler. 566 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 567 createMipsDisassembler); 568 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 569 createMipselDisassembler); 570 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 571 createMipsDisassembler); 572 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 573 createMipselDisassembler); 574 } 575 576 #include "MipsGenDisassemblerTables.inc" 577 578 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 579 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 580 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 581 return *(RegInfo->getRegClass(RC).begin() + RegNo); 582 } 583 584 template <typename InsnType> 585 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 586 const void *Decoder) { 587 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 588 589 // The size of the n field depends on the element size 590 // The register class also depends on this. 591 InsnType tmp = fieldFromInstruction(insn, 17, 5); 592 unsigned NSize = 0; 593 DecodeFN RegDecoder = nullptr; 594 if ((tmp & 0x18) == 0x00) { // INSVE_B 595 NSize = 4; 596 RegDecoder = DecodeMSA128BRegisterClass; 597 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 598 NSize = 3; 599 RegDecoder = DecodeMSA128HRegisterClass; 600 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 601 NSize = 2; 602 RegDecoder = DecodeMSA128WRegisterClass; 603 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 604 NSize = 1; 605 RegDecoder = DecodeMSA128DRegisterClass; 606 } else 607 llvm_unreachable("Invalid encoding"); 608 609 assert(NSize != 0 && RegDecoder != nullptr); 610 611 // $wd 612 tmp = fieldFromInstruction(insn, 6, 5); 613 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 614 return MCDisassembler::Fail; 615 // $wd_in 616 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 617 return MCDisassembler::Fail; 618 // $n 619 tmp = fieldFromInstruction(insn, 16, NSize); 620 MI.addOperand(MCOperand::createImm(tmp)); 621 // $ws 622 tmp = fieldFromInstruction(insn, 11, 5); 623 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 624 return MCDisassembler::Fail; 625 // $n2 626 MI.addOperand(MCOperand::createImm(0)); 627 628 return MCDisassembler::Success; 629 } 630 631 template <typename InsnType> 632 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 633 const void *Decoder) { 634 InsnType Rs = fieldFromInstruction(insn, 16, 5); 635 InsnType Imm = fieldFromInstruction(insn, 0, 16); 636 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 637 Rs))); 638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 639 Rs))); 640 MI.addOperand(MCOperand::createImm(Imm)); 641 642 return MCDisassembler::Success; 643 } 644 645 template <typename InsnType> 646 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 647 const void *Decoder) { 648 InsnType Rs = fieldFromInstruction(insn, 21, 5); 649 InsnType Imm = fieldFromInstruction(insn, 0, 16); 650 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 651 Rs))); 652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 653 Rs))); 654 MI.addOperand(MCOperand::createImm(Imm)); 655 656 return MCDisassembler::Success; 657 } 658 659 template <typename InsnType> 660 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 661 uint64_t Address, 662 const void *Decoder) { 663 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 664 // (otherwise we would have matched the ADDI instruction from the earlier 665 // ISA's instead). 666 // 667 // We have: 668 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 669 // BOVC if rs >= rt 670 // BEQZALC if rs == 0 && rt != 0 671 // BEQC if rs < rt && rs != 0 672 673 InsnType Rs = fieldFromInstruction(insn, 21, 5); 674 InsnType Rt = fieldFromInstruction(insn, 16, 5); 675 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 676 bool HasRs = false; 677 678 if (Rs >= Rt) { 679 MI.setOpcode(Mips::BOVC); 680 HasRs = true; 681 } else if (Rs != 0 && Rs < Rt) { 682 MI.setOpcode(Mips::BEQC); 683 HasRs = true; 684 } else 685 MI.setOpcode(Mips::BEQZALC); 686 687 if (HasRs) 688 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 689 Rs))); 690 691 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 692 Rt))); 693 MI.addOperand(MCOperand::createImm(Imm)); 694 695 return MCDisassembler::Success; 696 } 697 698 template <typename InsnType> 699 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 700 uint64_t Address, 701 const void *Decoder) { 702 InsnType Rt = fieldFromInstruction(insn, 21, 5); 703 InsnType Rs = fieldFromInstruction(insn, 16, 5); 704 int64_t Imm = 0; 705 706 if (Rs >= Rt) { 707 MI.setOpcode(Mips::BOVC_MMR6); 708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 709 Rt))); 710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 711 Rs))); 712 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 713 } else if (Rs != 0 && Rs < Rt) { 714 MI.setOpcode(Mips::BEQC_MMR6); 715 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 716 Rs))); 717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 718 Rt))); 719 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 720 } else { 721 MI.setOpcode(Mips::BEQZALC_MMR6); 722 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 723 Rt))); 724 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 725 } 726 727 MI.addOperand(MCOperand::createImm(Imm)); 728 729 return MCDisassembler::Success; 730 } 731 732 template <typename InsnType> 733 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 734 uint64_t Address, 735 const void *Decoder) { 736 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 737 // (otherwise we would have matched the ADDI instruction from the earlier 738 // ISA's instead). 739 // 740 // We have: 741 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 742 // BNVC if rs >= rt 743 // BNEZALC if rs == 0 && rt != 0 744 // BNEC if rs < rt && rs != 0 745 746 InsnType Rs = fieldFromInstruction(insn, 21, 5); 747 InsnType Rt = fieldFromInstruction(insn, 16, 5); 748 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 749 bool HasRs = false; 750 751 if (Rs >= Rt) { 752 MI.setOpcode(Mips::BNVC); 753 HasRs = true; 754 } else if (Rs != 0 && Rs < Rt) { 755 MI.setOpcode(Mips::BNEC); 756 HasRs = true; 757 } else 758 MI.setOpcode(Mips::BNEZALC); 759 760 if (HasRs) 761 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 762 Rs))); 763 764 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 765 Rt))); 766 MI.addOperand(MCOperand::createImm(Imm)); 767 768 return MCDisassembler::Success; 769 } 770 771 template <typename InsnType> 772 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 773 uint64_t Address, 774 const void *Decoder) { 775 InsnType Rt = fieldFromInstruction(insn, 21, 5); 776 InsnType Rs = fieldFromInstruction(insn, 16, 5); 777 int64_t Imm = 0; 778 779 if (Rs >= Rt) { 780 MI.setOpcode(Mips::BNVC_MMR6); 781 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 782 Rt))); 783 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 784 Rs))); 785 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 786 } else if (Rs != 0 && Rs < Rt) { 787 MI.setOpcode(Mips::BNEC_MMR6); 788 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 789 Rs))); 790 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 791 Rt))); 792 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 793 } else { 794 MI.setOpcode(Mips::BNEZALC_MMR6); 795 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 796 Rt))); 797 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 798 } 799 800 MI.addOperand(MCOperand::createImm(Imm)); 801 802 return MCDisassembler::Success; 803 } 804 805 template <typename InsnType> 806 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 807 uint64_t Address, 808 const void *Decoder) { 809 // We have: 810 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 811 // Invalid if rt == 0 812 // BGTZC_MMR6 if rs == 0 && rt != 0 813 // BLTZC_MMR6 if rs == rt && rt != 0 814 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 815 816 InsnType Rt = fieldFromInstruction(insn, 21, 5); 817 InsnType Rs = fieldFromInstruction(insn, 16, 5); 818 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 819 bool HasRs = false; 820 821 if (Rt == 0) 822 return MCDisassembler::Fail; 823 else if (Rs == 0) 824 MI.setOpcode(Mips::BGTZC_MMR6); 825 else if (Rs == Rt) 826 MI.setOpcode(Mips::BLTZC_MMR6); 827 else { 828 MI.setOpcode(Mips::BLTC_MMR6); 829 HasRs = true; 830 } 831 832 if (HasRs) 833 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 834 Rs))); 835 836 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 837 Rt))); 838 839 MI.addOperand(MCOperand::createImm(Imm)); 840 841 return MCDisassembler::Success; 842 } 843 844 template <typename InsnType> 845 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 846 uint64_t Address, 847 const void *Decoder) { 848 // We have: 849 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 850 // Invalid if rt == 0 851 // BLEZC_MMR6 if rs == 0 && rt != 0 852 // BGEZC_MMR6 if rs == rt && rt != 0 853 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 854 855 InsnType Rt = fieldFromInstruction(insn, 21, 5); 856 InsnType Rs = fieldFromInstruction(insn, 16, 5); 857 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 858 bool HasRs = false; 859 860 if (Rt == 0) 861 return MCDisassembler::Fail; 862 else if (Rs == 0) 863 MI.setOpcode(Mips::BLEZC_MMR6); 864 else if (Rs == Rt) 865 MI.setOpcode(Mips::BGEZC_MMR6); 866 else { 867 HasRs = true; 868 MI.setOpcode(Mips::BGEC_MMR6); 869 } 870 871 if (HasRs) 872 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 873 Rs))); 874 875 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 876 Rt))); 877 878 MI.addOperand(MCOperand::createImm(Imm)); 879 880 return MCDisassembler::Success; 881 } 882 883 template <typename InsnType> 884 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 885 uint64_t Address, 886 const void *Decoder) { 887 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 888 // (otherwise we would have matched the BLEZL instruction from the earlier 889 // ISA's instead). 890 // 891 // We have: 892 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 893 // Invalid if rs == 0 894 // BLEZC if rs == 0 && rt != 0 895 // BGEZC if rs == rt && rt != 0 896 // BGEC if rs != rt && rs != 0 && rt != 0 897 898 InsnType Rs = fieldFromInstruction(insn, 21, 5); 899 InsnType Rt = fieldFromInstruction(insn, 16, 5); 900 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 901 bool HasRs = false; 902 903 if (Rt == 0) 904 return MCDisassembler::Fail; 905 else if (Rs == 0) 906 MI.setOpcode(Mips::BLEZC); 907 else if (Rs == Rt) 908 MI.setOpcode(Mips::BGEZC); 909 else { 910 HasRs = true; 911 MI.setOpcode(Mips::BGEC); 912 } 913 914 if (HasRs) 915 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 916 Rs))); 917 918 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 919 Rt))); 920 921 MI.addOperand(MCOperand::createImm(Imm)); 922 923 return MCDisassembler::Success; 924 } 925 926 template <typename InsnType> 927 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 928 uint64_t Address, 929 const void *Decoder) { 930 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 931 // (otherwise we would have matched the BGTZL instruction from the earlier 932 // ISA's instead). 933 // 934 // We have: 935 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 936 // Invalid if rs == 0 937 // BGTZC if rs == 0 && rt != 0 938 // BLTZC if rs == rt && rt != 0 939 // BLTC if rs != rt && rs != 0 && rt != 0 940 941 bool HasRs = false; 942 943 InsnType Rs = fieldFromInstruction(insn, 21, 5); 944 InsnType Rt = fieldFromInstruction(insn, 16, 5); 945 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 946 947 if (Rt == 0) 948 return MCDisassembler::Fail; 949 else if (Rs == 0) 950 MI.setOpcode(Mips::BGTZC); 951 else if (Rs == Rt) 952 MI.setOpcode(Mips::BLTZC); 953 else { 954 MI.setOpcode(Mips::BLTC); 955 HasRs = true; 956 } 957 958 if (HasRs) 959 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 960 Rs))); 961 962 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 963 Rt))); 964 965 MI.addOperand(MCOperand::createImm(Imm)); 966 967 return MCDisassembler::Success; 968 } 969 970 template <typename InsnType> 971 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 972 uint64_t Address, 973 const void *Decoder) { 974 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 975 // (otherwise we would have matched the BGTZ instruction from the earlier 976 // ISA's instead). 977 // 978 // We have: 979 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 980 // BGTZ if rt == 0 981 // BGTZALC if rs == 0 && rt != 0 982 // BLTZALC if rs != 0 && rs == rt 983 // BLTUC if rs != 0 && rs != rt 984 985 InsnType Rs = fieldFromInstruction(insn, 21, 5); 986 InsnType Rt = fieldFromInstruction(insn, 16, 5); 987 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 988 bool HasRs = false; 989 bool HasRt = false; 990 991 if (Rt == 0) { 992 MI.setOpcode(Mips::BGTZ); 993 HasRs = true; 994 } else if (Rs == 0) { 995 MI.setOpcode(Mips::BGTZALC); 996 HasRt = true; 997 } else if (Rs == Rt) { 998 MI.setOpcode(Mips::BLTZALC); 999 HasRs = true; 1000 } else { 1001 MI.setOpcode(Mips::BLTUC); 1002 HasRs = true; 1003 HasRt = true; 1004 } 1005 1006 if (HasRs) 1007 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1008 Rs))); 1009 1010 if (HasRt) 1011 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1012 Rt))); 1013 1014 MI.addOperand(MCOperand::createImm(Imm)); 1015 1016 return MCDisassembler::Success; 1017 } 1018 1019 template <typename InsnType> 1020 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1021 uint64_t Address, 1022 const void *Decoder) { 1023 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1024 // (otherwise we would have matched the BLEZL instruction from the earlier 1025 // ISA's instead). 1026 // 1027 // We have: 1028 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1029 // Invalid if rs == 0 1030 // BLEZALC if rs == 0 && rt != 0 1031 // BGEZALC if rs == rt && rt != 0 1032 // BGEUC if rs != rt && rs != 0 && rt != 0 1033 1034 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1035 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1036 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1037 bool HasRs = false; 1038 1039 if (Rt == 0) 1040 return MCDisassembler::Fail; 1041 else if (Rs == 0) 1042 MI.setOpcode(Mips::BLEZALC); 1043 else if (Rs == Rt) 1044 MI.setOpcode(Mips::BGEZALC); 1045 else { 1046 HasRs = true; 1047 MI.setOpcode(Mips::BGEUC); 1048 } 1049 1050 if (HasRs) 1051 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1052 Rs))); 1053 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1054 Rt))); 1055 1056 MI.addOperand(MCOperand::createImm(Imm)); 1057 1058 return MCDisassembler::Success; 1059 } 1060 1061 // Override the generated disassembler to produce DEXT all the time. This is 1062 // for feature / behaviour parity with binutils. 1063 template <typename InsnType> 1064 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1065 const void *Decoder) { 1066 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1067 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1068 unsigned Size = 0; 1069 unsigned Pos = 0; 1070 1071 switch (MI.getOpcode()) { 1072 case Mips::DEXT: 1073 Pos = Lsb; 1074 Size = Msbd + 1; 1075 break; 1076 case Mips::DEXTM: 1077 Pos = Lsb; 1078 Size = Msbd + 1 + 32; 1079 break; 1080 case Mips::DEXTU: 1081 Pos = Lsb + 32; 1082 Size = Msbd + 1; 1083 break; 1084 default: 1085 llvm_unreachable("Unknown DEXT instruction!"); 1086 } 1087 1088 MI.setOpcode(Mips::DEXT); 1089 1090 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1091 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1092 1093 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1094 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1095 MI.addOperand(MCOperand::createImm(Pos)); 1096 MI.addOperand(MCOperand::createImm(Size)); 1097 1098 return MCDisassembler::Success; 1099 } 1100 1101 // Override the generated disassembler to produce DINS all the time. This is 1102 // for feature / behaviour parity with binutils. 1103 template <typename InsnType> 1104 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1105 const void *Decoder) { 1106 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1107 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1108 unsigned Size = 0; 1109 unsigned Pos = 0; 1110 1111 switch (MI.getOpcode()) { 1112 case Mips::DINS: 1113 Pos = Lsb; 1114 Size = Msbd + 1 - Pos; 1115 break; 1116 case Mips::DINSM: 1117 Pos = Lsb; 1118 Size = Msbd + 33 - Pos; 1119 break; 1120 case Mips::DINSU: 1121 Pos = Lsb + 32; 1122 // mbsd = pos + size - 33 1123 // mbsd - pos + 33 = size 1124 Size = Msbd + 33 - Pos; 1125 break; 1126 default: 1127 llvm_unreachable("Unknown DINS instruction!"); 1128 } 1129 1130 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1131 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1132 1133 MI.setOpcode(Mips::DINS); 1134 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1135 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1136 MI.addOperand(MCOperand::createImm(Pos)); 1137 MI.addOperand(MCOperand::createImm(Size)); 1138 1139 return MCDisassembler::Success; 1140 } 1141 1142 // Auto-generated decoder wouldn't add the third operand for CRC32*. 1143 template <typename InsnType> 1144 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 1145 const void *Decoder) { 1146 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1147 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1148 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1149 Rt))); 1150 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1151 Rs))); 1152 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1153 Rt))); 1154 return MCDisassembler::Success; 1155 } 1156 1157 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1158 /// according to the given endianness. 1159 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1160 uint64_t &Size, uint32_t &Insn, 1161 bool IsBigEndian) { 1162 // We want to read exactly 2 Bytes of data. 1163 if (Bytes.size() < 2) { 1164 Size = 0; 1165 return MCDisassembler::Fail; 1166 } 1167 1168 if (IsBigEndian) { 1169 Insn = (Bytes[0] << 8) | Bytes[1]; 1170 } else { 1171 Insn = (Bytes[1] << 8) | Bytes[0]; 1172 } 1173 1174 return MCDisassembler::Success; 1175 } 1176 1177 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1178 /// according to the given endianness. 1179 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1180 uint64_t &Size, uint32_t &Insn, 1181 bool IsBigEndian, bool IsMicroMips) { 1182 // We want to read exactly 4 Bytes of data. 1183 if (Bytes.size() < 4) { 1184 Size = 0; 1185 return MCDisassembler::Fail; 1186 } 1187 1188 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1189 // always precede the low 16 bits in the instruction stream (that is, they 1190 // are placed at lower addresses in the instruction stream). 1191 // 1192 // microMIPS byte ordering: 1193 // Big-endian: 0 | 1 | 2 | 3 1194 // Little-endian: 1 | 0 | 3 | 2 1195 1196 if (IsBigEndian) { 1197 // Encoded as a big-endian 32-bit word in the stream. 1198 Insn = 1199 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1200 } else { 1201 if (IsMicroMips) { 1202 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1203 (Bytes[1] << 24); 1204 } else { 1205 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1206 (Bytes[3] << 24); 1207 } 1208 } 1209 1210 return MCDisassembler::Success; 1211 } 1212 1213 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1214 ArrayRef<uint8_t> Bytes, 1215 uint64_t Address, 1216 raw_ostream &VStream, 1217 raw_ostream &CStream) const { 1218 uint32_t Insn; 1219 DecodeStatus Result; 1220 Size = 0; 1221 1222 if (IsMicroMips) { 1223 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1224 if (Result == MCDisassembler::Fail) 1225 return MCDisassembler::Fail; 1226 1227 if (hasMips32r6()) { 1228 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1229 // Calling the auto-generated decoder function for microMIPS32R6 1230 // 16-bit instructions. 1231 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1232 Address, this, STI); 1233 if (Result != MCDisassembler::Fail) { 1234 Size = 2; 1235 return Result; 1236 } 1237 } 1238 1239 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1240 // Calling the auto-generated decoder function for microMIPS 16-bit 1241 // instructions. 1242 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1243 this, STI); 1244 if (Result != MCDisassembler::Fail) { 1245 Size = 2; 1246 return Result; 1247 } 1248 1249 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1250 if (Result == MCDisassembler::Fail) 1251 return MCDisassembler::Fail; 1252 1253 if (hasMips32r6()) { 1254 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1255 // Calling the auto-generated decoder function. 1256 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1257 this, STI); 1258 if (Result != MCDisassembler::Fail) { 1259 Size = 4; 1260 return Result; 1261 } 1262 } 1263 1264 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1265 // Calling the auto-generated decoder function. 1266 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1267 this, STI); 1268 if (Result != MCDisassembler::Fail) { 1269 Size = 4; 1270 return Result; 1271 } 1272 1273 if (isFP64()) { 1274 DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1275 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1276 Address, this, STI); 1277 if (Result != MCDisassembler::Fail) { 1278 Size = 4; 1279 return Result; 1280 } 1281 } 1282 1283 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1284 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1285 // could form a valid instruction. The two bytes we rejected as an 1286 // instruction could have actually beeen an inline constant pool that is 1287 // unconditionally branched over. 1288 Size = 2; 1289 return MCDisassembler::Fail; 1290 } 1291 1292 // Attempt to read the instruction so that we can attempt to decode it. If 1293 // the buffer is not 4 bytes long, let the higher level logic figure out 1294 // what to do with a size of zero and MCDisassembler::Fail. 1295 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1296 if (Result == MCDisassembler::Fail) 1297 return MCDisassembler::Fail; 1298 1299 // The only instruction size for standard encoded MIPS. 1300 Size = 4; 1301 1302 if (hasCOP3()) { 1303 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1304 Result = 1305 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1306 if (Result != MCDisassembler::Fail) 1307 return Result; 1308 } 1309 1310 if (hasMips32r6() && isGP64()) { 1311 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1312 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1313 Address, this, STI); 1314 if (Result != MCDisassembler::Fail) 1315 return Result; 1316 } 1317 1318 if (hasMips32r6() && isPTR64()) { 1319 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1320 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1321 Address, this, STI); 1322 if (Result != MCDisassembler::Fail) 1323 return Result; 1324 } 1325 1326 if (hasMips32r6()) { 1327 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1328 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1329 Address, this, STI); 1330 if (Result != MCDisassembler::Fail) 1331 return Result; 1332 } 1333 1334 if (hasMips2() && isPTR64()) { 1335 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1336 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1337 Address, this, STI); 1338 if (Result != MCDisassembler::Fail) 1339 return Result; 1340 } 1341 1342 if (hasCnMips()) { 1343 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1344 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1345 Address, this, STI); 1346 if (Result != MCDisassembler::Fail) 1347 return Result; 1348 } 1349 1350 if (isGP64()) { 1351 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1352 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1353 Address, this, STI); 1354 if (Result != MCDisassembler::Fail) 1355 return Result; 1356 } 1357 1358 if (isFP64()) { 1359 DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1360 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1361 Address, this, STI); 1362 if (Result != MCDisassembler::Fail) 1363 return Result; 1364 } 1365 1366 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1367 // Calling the auto-generated decoder function. 1368 Result = 1369 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1370 if (Result != MCDisassembler::Fail) 1371 return Result; 1372 1373 return MCDisassembler::Fail; 1374 } 1375 1376 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1377 unsigned RegNo, 1378 uint64_t Address, 1379 const void *Decoder) { 1380 return MCDisassembler::Fail; 1381 } 1382 1383 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1384 unsigned RegNo, 1385 uint64_t Address, 1386 const void *Decoder) { 1387 if (RegNo > 31) 1388 return MCDisassembler::Fail; 1389 1390 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1391 Inst.addOperand(MCOperand::createReg(Reg)); 1392 return MCDisassembler::Success; 1393 } 1394 1395 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1396 unsigned RegNo, 1397 uint64_t Address, 1398 const void *Decoder) { 1399 if (RegNo > 7) 1400 return MCDisassembler::Fail; 1401 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1402 Inst.addOperand(MCOperand::createReg(Reg)); 1403 return MCDisassembler::Success; 1404 } 1405 1406 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1407 unsigned RegNo, 1408 uint64_t Address, 1409 const void *Decoder) { 1410 if (RegNo > 7) 1411 return MCDisassembler::Fail; 1412 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1413 Inst.addOperand(MCOperand::createReg(Reg)); 1414 return MCDisassembler::Success; 1415 } 1416 1417 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1418 unsigned RegNo, 1419 uint64_t Address, 1420 const void *Decoder) { 1421 if (RegNo > 7) 1422 return MCDisassembler::Fail; 1423 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1424 Inst.addOperand(MCOperand::createReg(Reg)); 1425 return MCDisassembler::Success; 1426 } 1427 1428 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1429 unsigned RegNo, 1430 uint64_t Address, 1431 const void *Decoder) { 1432 if (RegNo > 31) 1433 return MCDisassembler::Fail; 1434 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1435 Inst.addOperand(MCOperand::createReg(Reg)); 1436 return MCDisassembler::Success; 1437 } 1438 1439 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1440 unsigned RegNo, 1441 uint64_t Address, 1442 const void *Decoder) { 1443 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1444 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1445 1446 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1447 } 1448 1449 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1450 unsigned RegNo, 1451 uint64_t Address, 1452 const void *Decoder) { 1453 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1454 } 1455 1456 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1457 unsigned RegNo, 1458 uint64_t Address, 1459 const void *Decoder) { 1460 if (RegNo > 31) 1461 return MCDisassembler::Fail; 1462 1463 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1464 Inst.addOperand(MCOperand::createReg(Reg)); 1465 return MCDisassembler::Success; 1466 } 1467 1468 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1469 unsigned RegNo, 1470 uint64_t Address, 1471 const void *Decoder) { 1472 if (RegNo > 31) 1473 return MCDisassembler::Fail; 1474 1475 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1476 Inst.addOperand(MCOperand::createReg(Reg)); 1477 return MCDisassembler::Success; 1478 } 1479 1480 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1481 unsigned RegNo, 1482 uint64_t Address, 1483 const void *Decoder) { 1484 if (RegNo > 31) 1485 return MCDisassembler::Fail; 1486 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1487 Inst.addOperand(MCOperand::createReg(Reg)); 1488 return MCDisassembler::Success; 1489 } 1490 1491 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1492 unsigned RegNo, 1493 uint64_t Address, 1494 const void *Decoder) { 1495 if (RegNo > 7) 1496 return MCDisassembler::Fail; 1497 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1498 Inst.addOperand(MCOperand::createReg(Reg)); 1499 return MCDisassembler::Success; 1500 } 1501 1502 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1503 uint64_t Address, 1504 const void *Decoder) { 1505 if (RegNo > 31) 1506 return MCDisassembler::Fail; 1507 1508 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1509 Inst.addOperand(MCOperand::createReg(Reg)); 1510 return MCDisassembler::Success; 1511 } 1512 1513 static DecodeStatus DecodeMem(MCInst &Inst, 1514 unsigned Insn, 1515 uint64_t Address, 1516 const void *Decoder) { 1517 int Offset = SignExtend32<16>(Insn & 0xffff); 1518 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1519 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1520 1521 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1522 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1523 1524 if (Inst.getOpcode() == Mips::SC || 1525 Inst.getOpcode() == Mips::SCD) 1526 Inst.addOperand(MCOperand::createReg(Reg)); 1527 1528 Inst.addOperand(MCOperand::createReg(Reg)); 1529 Inst.addOperand(MCOperand::createReg(Base)); 1530 Inst.addOperand(MCOperand::createImm(Offset)); 1531 1532 return MCDisassembler::Success; 1533 } 1534 1535 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1536 unsigned Insn, 1537 uint64_t Address, 1538 const void *Decoder) { 1539 int Offset = SignExtend32<9>(Insn >> 7); 1540 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1541 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1542 1543 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1544 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1545 1546 if (Inst.getOpcode() == Mips::SCE) 1547 Inst.addOperand(MCOperand::createReg(Reg)); 1548 1549 Inst.addOperand(MCOperand::createReg(Reg)); 1550 Inst.addOperand(MCOperand::createReg(Base)); 1551 Inst.addOperand(MCOperand::createImm(Offset)); 1552 1553 return MCDisassembler::Success; 1554 } 1555 1556 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1557 unsigned Insn, 1558 uint64_t Address, 1559 const void *Decoder) { 1560 int Offset = SignExtend32<16>(Insn & 0xffff); 1561 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1562 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1563 1564 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1565 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1566 1567 Inst.addOperand(MCOperand::createReg(Reg)); 1568 Inst.addOperand(MCOperand::createReg(Base)); 1569 Inst.addOperand(MCOperand::createImm(Offset)); 1570 1571 return MCDisassembler::Success; 1572 } 1573 1574 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1575 unsigned Insn, 1576 uint64_t Address, 1577 const void *Decoder) { 1578 int Offset = SignExtend32<16>(Insn & 0xffff); 1579 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1580 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1581 1582 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1583 1584 Inst.addOperand(MCOperand::createReg(Base)); 1585 Inst.addOperand(MCOperand::createImm(Offset)); 1586 Inst.addOperand(MCOperand::createImm(Hint)); 1587 1588 return MCDisassembler::Success; 1589 } 1590 1591 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1592 unsigned Insn, 1593 uint64_t Address, 1594 const void *Decoder) { 1595 int Offset = SignExtend32<12>(Insn & 0xfff); 1596 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1597 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1598 1599 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1600 1601 Inst.addOperand(MCOperand::createReg(Base)); 1602 Inst.addOperand(MCOperand::createImm(Offset)); 1603 Inst.addOperand(MCOperand::createImm(Hint)); 1604 1605 return MCDisassembler::Success; 1606 } 1607 1608 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1609 unsigned Insn, 1610 uint64_t Address, 1611 const void *Decoder) { 1612 int Offset = SignExtend32<9>(Insn & 0x1ff); 1613 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1614 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1615 1616 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1617 1618 Inst.addOperand(MCOperand::createReg(Base)); 1619 Inst.addOperand(MCOperand::createImm(Offset)); 1620 Inst.addOperand(MCOperand::createImm(Hint)); 1621 1622 return MCDisassembler::Success; 1623 } 1624 1625 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1626 unsigned Insn, 1627 uint64_t Address, 1628 const void *Decoder) { 1629 int Offset = SignExtend32<9>(Insn >> 7); 1630 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1631 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1632 1633 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1634 1635 Inst.addOperand(MCOperand::createReg(Base)); 1636 Inst.addOperand(MCOperand::createImm(Offset)); 1637 Inst.addOperand(MCOperand::createImm(Hint)); 1638 1639 return MCDisassembler::Success; 1640 } 1641 1642 static DecodeStatus DecodeSyncI(MCInst &Inst, 1643 unsigned Insn, 1644 uint64_t Address, 1645 const void *Decoder) { 1646 int Offset = SignExtend32<16>(Insn & 0xffff); 1647 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1648 1649 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1650 1651 Inst.addOperand(MCOperand::createReg(Base)); 1652 Inst.addOperand(MCOperand::createImm(Offset)); 1653 1654 return MCDisassembler::Success; 1655 } 1656 1657 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 1658 uint64_t Address, const void *Decoder) { 1659 int Offset = SignExtend32<16>(Insn & 0xffff); 1660 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1661 1662 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1663 1664 Inst.addOperand(MCOperand::createReg(Base)); 1665 Inst.addOperand(MCOperand::createImm(Offset)); 1666 1667 return MCDisassembler::Success; 1668 } 1669 1670 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1671 unsigned Insn, 1672 uint64_t Address, 1673 const void *Decoder) { 1674 int Immediate = SignExtend32<16>(Insn & 0xffff); 1675 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1676 1677 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1678 1679 Inst.addOperand(MCOperand::createReg(Base)); 1680 Inst.addOperand(MCOperand::createImm(Immediate)); 1681 1682 return MCDisassembler::Success; 1683 } 1684 1685 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1686 uint64_t Address, const void *Decoder) { 1687 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1688 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1689 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1690 1691 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1692 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1693 1694 Inst.addOperand(MCOperand::createReg(Reg)); 1695 Inst.addOperand(MCOperand::createReg(Base)); 1696 1697 // The immediate field of an LD/ST instruction is scaled which means it must 1698 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1699 // data format. 1700 // .b - 1 byte 1701 // .h - 2 bytes 1702 // .w - 4 bytes 1703 // .d - 8 bytes 1704 switch(Inst.getOpcode()) 1705 { 1706 default: 1707 assert(false && "Unexpected instruction"); 1708 return MCDisassembler::Fail; 1709 break; 1710 case Mips::LD_B: 1711 case Mips::ST_B: 1712 Inst.addOperand(MCOperand::createImm(Offset)); 1713 break; 1714 case Mips::LD_H: 1715 case Mips::ST_H: 1716 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1717 break; 1718 case Mips::LD_W: 1719 case Mips::ST_W: 1720 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1721 break; 1722 case Mips::LD_D: 1723 case Mips::ST_D: 1724 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1725 break; 1726 } 1727 1728 return MCDisassembler::Success; 1729 } 1730 1731 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1732 unsigned Insn, 1733 uint64_t Address, 1734 const void *Decoder) { 1735 unsigned Offset = Insn & 0xf; 1736 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1737 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1738 1739 switch (Inst.getOpcode()) { 1740 case Mips::LBU16_MM: 1741 case Mips::LHU16_MM: 1742 case Mips::LW16_MM: 1743 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1744 == MCDisassembler::Fail) 1745 return MCDisassembler::Fail; 1746 break; 1747 case Mips::SB16_MM: 1748 case Mips::SB16_MMR6: 1749 case Mips::SH16_MM: 1750 case Mips::SH16_MMR6: 1751 case Mips::SW16_MM: 1752 case Mips::SW16_MMR6: 1753 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1754 == MCDisassembler::Fail) 1755 return MCDisassembler::Fail; 1756 break; 1757 } 1758 1759 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1760 == MCDisassembler::Fail) 1761 return MCDisassembler::Fail; 1762 1763 switch (Inst.getOpcode()) { 1764 case Mips::LBU16_MM: 1765 if (Offset == 0xf) 1766 Inst.addOperand(MCOperand::createImm(-1)); 1767 else 1768 Inst.addOperand(MCOperand::createImm(Offset)); 1769 break; 1770 case Mips::SB16_MM: 1771 case Mips::SB16_MMR6: 1772 Inst.addOperand(MCOperand::createImm(Offset)); 1773 break; 1774 case Mips::LHU16_MM: 1775 case Mips::SH16_MM: 1776 case Mips::SH16_MMR6: 1777 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1778 break; 1779 case Mips::LW16_MM: 1780 case Mips::SW16_MM: 1781 case Mips::SW16_MMR6: 1782 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1783 break; 1784 } 1785 1786 return MCDisassembler::Success; 1787 } 1788 1789 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1790 unsigned Insn, 1791 uint64_t Address, 1792 const void *Decoder) { 1793 unsigned Offset = Insn & 0x1F; 1794 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1795 1796 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1797 1798 Inst.addOperand(MCOperand::createReg(Reg)); 1799 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1800 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1801 1802 return MCDisassembler::Success; 1803 } 1804 1805 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1806 unsigned Insn, 1807 uint64_t Address, 1808 const void *Decoder) { 1809 unsigned Offset = Insn & 0x7F; 1810 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1811 1812 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1813 1814 Inst.addOperand(MCOperand::createReg(Reg)); 1815 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1816 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1817 1818 return MCDisassembler::Success; 1819 } 1820 1821 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1822 unsigned Insn, 1823 uint64_t Address, 1824 const void *Decoder) { 1825 int Offset; 1826 switch (Inst.getOpcode()) { 1827 case Mips::LWM16_MMR6: 1828 case Mips::SWM16_MMR6: 1829 Offset = fieldFromInstruction(Insn, 4, 4); 1830 break; 1831 default: 1832 Offset = SignExtend32<4>(Insn & 0xf); 1833 break; 1834 } 1835 1836 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1837 == MCDisassembler::Fail) 1838 return MCDisassembler::Fail; 1839 1840 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1841 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1842 1843 return MCDisassembler::Success; 1844 } 1845 1846 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1847 unsigned Insn, 1848 uint64_t Address, 1849 const void *Decoder) { 1850 int Offset = SignExtend32<9>(Insn & 0x1ff); 1851 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1852 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1853 1854 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1855 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1856 1857 if (Inst.getOpcode() == Mips::SCE_MM) 1858 Inst.addOperand(MCOperand::createReg(Reg)); 1859 1860 Inst.addOperand(MCOperand::createReg(Reg)); 1861 Inst.addOperand(MCOperand::createReg(Base)); 1862 Inst.addOperand(MCOperand::createImm(Offset)); 1863 1864 return MCDisassembler::Success; 1865 } 1866 1867 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1868 unsigned Insn, 1869 uint64_t Address, 1870 const void *Decoder) { 1871 int Offset = SignExtend32<12>(Insn & 0x0fff); 1872 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1873 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1874 1875 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1876 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1877 1878 switch (Inst.getOpcode()) { 1879 case Mips::SWM32_MM: 1880 case Mips::LWM32_MM: 1881 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1882 == MCDisassembler::Fail) 1883 return MCDisassembler::Fail; 1884 Inst.addOperand(MCOperand::createReg(Base)); 1885 Inst.addOperand(MCOperand::createImm(Offset)); 1886 break; 1887 case Mips::SC_MM: 1888 Inst.addOperand(MCOperand::createReg(Reg)); 1889 LLVM_FALLTHROUGH; 1890 default: 1891 Inst.addOperand(MCOperand::createReg(Reg)); 1892 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1893 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1894 Inst.addOperand(MCOperand::createReg(Reg+1)); 1895 1896 Inst.addOperand(MCOperand::createReg(Base)); 1897 Inst.addOperand(MCOperand::createImm(Offset)); 1898 } 1899 1900 return MCDisassembler::Success; 1901 } 1902 1903 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1904 unsigned Insn, 1905 uint64_t Address, 1906 const void *Decoder) { 1907 int Offset = SignExtend32<16>(Insn & 0xffff); 1908 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1909 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1910 1911 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1912 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1913 1914 Inst.addOperand(MCOperand::createReg(Reg)); 1915 Inst.addOperand(MCOperand::createReg(Base)); 1916 Inst.addOperand(MCOperand::createImm(Offset)); 1917 1918 return MCDisassembler::Success; 1919 } 1920 1921 static DecodeStatus DecodeFMem(MCInst &Inst, 1922 unsigned Insn, 1923 uint64_t Address, 1924 const void *Decoder) { 1925 int Offset = SignExtend32<16>(Insn & 0xffff); 1926 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1927 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1928 1929 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1930 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1931 1932 Inst.addOperand(MCOperand::createReg(Reg)); 1933 Inst.addOperand(MCOperand::createReg(Base)); 1934 Inst.addOperand(MCOperand::createImm(Offset)); 1935 1936 return MCDisassembler::Success; 1937 } 1938 1939 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1940 uint64_t Address, const void *Decoder) { 1941 // This function is the same as DecodeFMem but with the Reg and Base fields 1942 // swapped according to microMIPS spec. 1943 int Offset = SignExtend32<16>(Insn & 0xffff); 1944 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1945 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1946 1947 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1948 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1949 1950 Inst.addOperand(MCOperand::createReg(Reg)); 1951 Inst.addOperand(MCOperand::createReg(Base)); 1952 Inst.addOperand(MCOperand::createImm(Offset)); 1953 1954 return MCDisassembler::Success; 1955 } 1956 1957 static DecodeStatus DecodeFMem2(MCInst &Inst, 1958 unsigned Insn, 1959 uint64_t Address, 1960 const void *Decoder) { 1961 int Offset = SignExtend32<16>(Insn & 0xffff); 1962 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1963 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1964 1965 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1966 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1967 1968 Inst.addOperand(MCOperand::createReg(Reg)); 1969 Inst.addOperand(MCOperand::createReg(Base)); 1970 Inst.addOperand(MCOperand::createImm(Offset)); 1971 1972 return MCDisassembler::Success; 1973 } 1974 1975 static DecodeStatus DecodeFMem3(MCInst &Inst, 1976 unsigned Insn, 1977 uint64_t Address, 1978 const void *Decoder) { 1979 int Offset = SignExtend32<16>(Insn & 0xffff); 1980 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1981 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1982 1983 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1984 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1985 1986 Inst.addOperand(MCOperand::createReg(Reg)); 1987 Inst.addOperand(MCOperand::createReg(Base)); 1988 Inst.addOperand(MCOperand::createImm(Offset)); 1989 1990 return MCDisassembler::Success; 1991 } 1992 1993 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1994 unsigned Insn, 1995 uint64_t Address, 1996 const void *Decoder) { 1997 int Offset = SignExtend32<11>(Insn & 0x07ff); 1998 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1999 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2000 2001 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2002 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2003 2004 Inst.addOperand(MCOperand::createReg(Reg)); 2005 Inst.addOperand(MCOperand::createReg(Base)); 2006 Inst.addOperand(MCOperand::createImm(Offset)); 2007 2008 return MCDisassembler::Success; 2009 } 2010 2011 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2012 uint64_t Address, const void *Decoder) { 2013 int Offset = SignExtend32<11>(Insn & 0x07ff); 2014 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2015 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2016 2017 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2018 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2019 2020 Inst.addOperand(MCOperand::createReg(Reg)); 2021 Inst.addOperand(MCOperand::createReg(Base)); 2022 Inst.addOperand(MCOperand::createImm(Offset)); 2023 2024 return MCDisassembler::Success; 2025 } 2026 2027 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2028 unsigned Insn, 2029 uint64_t Address, 2030 const void *Decoder) { 2031 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2032 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2033 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2034 2035 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2036 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2037 2038 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2039 Inst.addOperand(MCOperand::createReg(Rt)); 2040 } 2041 2042 Inst.addOperand(MCOperand::createReg(Rt)); 2043 Inst.addOperand(MCOperand::createReg(Base)); 2044 Inst.addOperand(MCOperand::createImm(Offset)); 2045 2046 return MCDisassembler::Success; 2047 } 2048 2049 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2050 unsigned RegNo, 2051 uint64_t Address, 2052 const void *Decoder) { 2053 // Currently only hardware register 29 is supported. 2054 if (RegNo != 29) 2055 return MCDisassembler::Fail; 2056 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2057 return MCDisassembler::Success; 2058 } 2059 2060 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2061 unsigned RegNo, 2062 uint64_t Address, 2063 const void *Decoder) { 2064 if (RegNo > 30 || RegNo %2) 2065 return MCDisassembler::Fail; 2066 2067 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2068 Inst.addOperand(MCOperand::createReg(Reg)); 2069 return MCDisassembler::Success; 2070 } 2071 2072 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2073 unsigned RegNo, 2074 uint64_t Address, 2075 const void *Decoder) { 2076 if (RegNo >= 4) 2077 return MCDisassembler::Fail; 2078 2079 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2080 Inst.addOperand(MCOperand::createReg(Reg)); 2081 return MCDisassembler::Success; 2082 } 2083 2084 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2085 unsigned RegNo, 2086 uint64_t Address, 2087 const void *Decoder) { 2088 if (RegNo >= 4) 2089 return MCDisassembler::Fail; 2090 2091 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2092 Inst.addOperand(MCOperand::createReg(Reg)); 2093 return MCDisassembler::Success; 2094 } 2095 2096 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2097 unsigned RegNo, 2098 uint64_t Address, 2099 const void *Decoder) { 2100 if (RegNo >= 4) 2101 return MCDisassembler::Fail; 2102 2103 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2104 Inst.addOperand(MCOperand::createReg(Reg)); 2105 return MCDisassembler::Success; 2106 } 2107 2108 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2109 unsigned RegNo, 2110 uint64_t Address, 2111 const void *Decoder) { 2112 if (RegNo > 31) 2113 return MCDisassembler::Fail; 2114 2115 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2116 Inst.addOperand(MCOperand::createReg(Reg)); 2117 return MCDisassembler::Success; 2118 } 2119 2120 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2121 unsigned RegNo, 2122 uint64_t Address, 2123 const void *Decoder) { 2124 if (RegNo > 31) 2125 return MCDisassembler::Fail; 2126 2127 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2128 Inst.addOperand(MCOperand::createReg(Reg)); 2129 return MCDisassembler::Success; 2130 } 2131 2132 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2133 unsigned RegNo, 2134 uint64_t Address, 2135 const void *Decoder) { 2136 if (RegNo > 31) 2137 return MCDisassembler::Fail; 2138 2139 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2140 Inst.addOperand(MCOperand::createReg(Reg)); 2141 return MCDisassembler::Success; 2142 } 2143 2144 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2145 unsigned RegNo, 2146 uint64_t Address, 2147 const void *Decoder) { 2148 if (RegNo > 31) 2149 return MCDisassembler::Fail; 2150 2151 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2152 Inst.addOperand(MCOperand::createReg(Reg)); 2153 return MCDisassembler::Success; 2154 } 2155 2156 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2157 unsigned RegNo, 2158 uint64_t Address, 2159 const void *Decoder) { 2160 if (RegNo > 7) 2161 return MCDisassembler::Fail; 2162 2163 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2164 Inst.addOperand(MCOperand::createReg(Reg)); 2165 return MCDisassembler::Success; 2166 } 2167 2168 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2169 unsigned RegNo, 2170 uint64_t Address, 2171 const void *Decoder) { 2172 if (RegNo > 31) 2173 return MCDisassembler::Fail; 2174 2175 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2176 Inst.addOperand(MCOperand::createReg(Reg)); 2177 return MCDisassembler::Success; 2178 } 2179 2180 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2181 unsigned RegNo, 2182 uint64_t Address, 2183 const void *Decoder) { 2184 if (RegNo > 31) 2185 return MCDisassembler::Fail; 2186 2187 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2188 Inst.addOperand(MCOperand::createReg(Reg)); 2189 return MCDisassembler::Success; 2190 } 2191 2192 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2193 unsigned Offset, 2194 uint64_t Address, 2195 const void *Decoder) { 2196 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2197 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2198 return MCDisassembler::Success; 2199 } 2200 2201 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2202 unsigned Offset, 2203 uint64_t Address, 2204 const void *Decoder) { 2205 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2206 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2207 return MCDisassembler::Success; 2208 } 2209 2210 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2211 unsigned Insn, 2212 uint64_t Address, 2213 const void *Decoder) { 2214 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2215 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2216 return MCDisassembler::Success; 2217 } 2218 2219 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2220 unsigned Offset, 2221 uint64_t Address, 2222 const void *Decoder) { 2223 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2224 2225 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2226 return MCDisassembler::Success; 2227 } 2228 2229 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2230 unsigned Offset, 2231 uint64_t Address, 2232 const void *Decoder) { 2233 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2234 2235 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2236 return MCDisassembler::Success; 2237 } 2238 2239 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2240 unsigned Offset, 2241 uint64_t Address, 2242 const void *Decoder) { 2243 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2244 2245 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2246 return MCDisassembler::Success; 2247 } 2248 2249 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2250 unsigned Offset, 2251 uint64_t Address, 2252 const void *Decoder) { 2253 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2254 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2255 return MCDisassembler::Success; 2256 } 2257 2258 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2259 unsigned Offset, 2260 uint64_t Address, 2261 const void *Decoder) { 2262 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2263 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2264 return MCDisassembler::Success; 2265 } 2266 2267 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2268 unsigned Offset, 2269 uint64_t Address, 2270 const void *Decoder) { 2271 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2272 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2273 return MCDisassembler::Success; 2274 } 2275 2276 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2277 unsigned Offset, 2278 uint64_t Address, 2279 const void *Decoder) { 2280 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2281 2282 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2283 return MCDisassembler::Success; 2284 } 2285 2286 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2287 unsigned Insn, 2288 uint64_t Address, 2289 const void *Decoder) { 2290 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2291 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2292 return MCDisassembler::Success; 2293 } 2294 2295 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2296 unsigned Value, 2297 uint64_t Address, 2298 const void *Decoder) { 2299 if (Value == 0) 2300 Inst.addOperand(MCOperand::createImm(1)); 2301 else if (Value == 0x7) 2302 Inst.addOperand(MCOperand::createImm(-1)); 2303 else 2304 Inst.addOperand(MCOperand::createImm(Value << 2)); 2305 return MCDisassembler::Success; 2306 } 2307 2308 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2309 unsigned Value, 2310 uint64_t Address, 2311 const void *Decoder) { 2312 if (Value == 0x7F) 2313 Inst.addOperand(MCOperand::createImm(-1)); 2314 else 2315 Inst.addOperand(MCOperand::createImm(Value)); 2316 return MCDisassembler::Success; 2317 } 2318 2319 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2320 unsigned Value, 2321 uint64_t Address, 2322 const void *Decoder) { 2323 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2324 return MCDisassembler::Success; 2325 } 2326 2327 template <unsigned Bits, int Offset, int Scale> 2328 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2329 uint64_t Address, 2330 const void *Decoder) { 2331 Value &= ((1 << Bits) - 1); 2332 Value *= Scale; 2333 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2334 return MCDisassembler::Success; 2335 } 2336 2337 template <unsigned Bits, int Offset, int ScaleBy> 2338 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2339 uint64_t Address, 2340 const void *Decoder) { 2341 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2342 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2343 return MCDisassembler::Success; 2344 } 2345 2346 static DecodeStatus DecodeInsSize(MCInst &Inst, 2347 unsigned Insn, 2348 uint64_t Address, 2349 const void *Decoder) { 2350 // First we need to grab the pos(lsb) from MCInst. 2351 // This function only handles the 32 bit variants of ins, as dins 2352 // variants are handled differently. 2353 int Pos = Inst.getOperand(2).getImm(); 2354 int Size = (int) Insn - Pos + 1; 2355 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2356 return MCDisassembler::Success; 2357 } 2358 2359 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2360 uint64_t Address, const void *Decoder) { 2361 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2362 return MCDisassembler::Success; 2363 } 2364 2365 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2366 uint64_t Address, const void *Decoder) { 2367 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2368 return MCDisassembler::Success; 2369 } 2370 2371 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2372 uint64_t Address, const void *Decoder) { 2373 int32_t DecodedValue; 2374 switch (Insn) { 2375 case 0: DecodedValue = 256; break; 2376 case 1: DecodedValue = 257; break; 2377 case 510: DecodedValue = -258; break; 2378 case 511: DecodedValue = -257; break; 2379 default: DecodedValue = SignExtend32<9>(Insn); break; 2380 } 2381 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2382 return MCDisassembler::Success; 2383 } 2384 2385 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2386 uint64_t Address, const void *Decoder) { 2387 // Insn must be >= 0, since it is unsigned that condition is always true. 2388 assert(Insn < 16); 2389 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2390 255, 32768, 65535}; 2391 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2392 return MCDisassembler::Success; 2393 } 2394 2395 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2396 unsigned Insn, 2397 uint64_t Address, 2398 const void *Decoder) { 2399 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2400 Mips::S6, Mips::S7, Mips::FP}; 2401 unsigned RegNum; 2402 2403 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2404 2405 // Empty register lists are not allowed. 2406 if (RegLst == 0) 2407 return MCDisassembler::Fail; 2408 2409 RegNum = RegLst & 0xf; 2410 2411 // RegLst values 10-15, and 26-31 are reserved. 2412 if (RegNum > 9) 2413 return MCDisassembler::Fail; 2414 2415 for (unsigned i = 0; i < RegNum; i++) 2416 Inst.addOperand(MCOperand::createReg(Regs[i])); 2417 2418 if (RegLst & 0x10) 2419 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2420 2421 return MCDisassembler::Success; 2422 } 2423 2424 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2425 uint64_t Address, 2426 const void *Decoder) { 2427 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2428 unsigned RegLst; 2429 switch(Inst.getOpcode()) { 2430 default: 2431 RegLst = fieldFromInstruction(Insn, 4, 2); 2432 break; 2433 case Mips::LWM16_MMR6: 2434 case Mips::SWM16_MMR6: 2435 RegLst = fieldFromInstruction(Insn, 8, 2); 2436 break; 2437 } 2438 unsigned RegNum = RegLst & 0x3; 2439 2440 for (unsigned i = 0; i <= RegNum; i++) 2441 Inst.addOperand(MCOperand::createReg(Regs[i])); 2442 2443 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2444 2445 return MCDisassembler::Success; 2446 } 2447 2448 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2449 uint64_t Address, const void *Decoder) { 2450 switch (RegPair) { 2451 default: 2452 return MCDisassembler::Fail; 2453 case 0: 2454 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2455 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2456 break; 2457 case 1: 2458 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2459 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2460 break; 2461 case 2: 2462 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2463 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2464 break; 2465 case 3: 2466 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2467 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2468 break; 2469 case 4: 2470 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2471 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2472 break; 2473 case 5: 2474 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2475 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2476 break; 2477 case 6: 2478 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2479 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2480 break; 2481 case 7: 2482 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2483 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2484 break; 2485 } 2486 2487 return MCDisassembler::Success; 2488 } 2489 2490 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2491 uint64_t Address, const void *Decoder) { 2492 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2493 return MCDisassembler::Success; 2494 } 2495 2496 template <typename InsnType> 2497 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2498 uint64_t Address, 2499 const void *Decoder) { 2500 // We have: 2501 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2502 // Invalid if rt == 0 2503 // BGTZALC_MMR6 if rs == 0 && rt != 0 2504 // BLTZALC_MMR6 if rs != 0 && rs == rt 2505 // BLTUC_MMR6 if rs != 0 && rs != rt 2506 2507 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2508 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2509 InsnType Imm = 0; 2510 bool HasRs = false; 2511 bool HasRt = false; 2512 2513 if (Rt == 0) 2514 return MCDisassembler::Fail; 2515 else if (Rs == 0) { 2516 MI.setOpcode(Mips::BGTZALC_MMR6); 2517 HasRt = true; 2518 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2519 } 2520 else if (Rs == Rt) { 2521 MI.setOpcode(Mips::BLTZALC_MMR6); 2522 HasRs = true; 2523 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2524 } 2525 else { 2526 MI.setOpcode(Mips::BLTUC_MMR6); 2527 HasRs = true; 2528 HasRt = true; 2529 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2530 } 2531 2532 if (HasRs) 2533 MI.addOperand( 2534 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2535 2536 if (HasRt) 2537 MI.addOperand( 2538 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2539 2540 MI.addOperand(MCOperand::createImm(Imm)); 2541 2542 return MCDisassembler::Success; 2543 } 2544 2545 template <typename InsnType> 2546 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2547 uint64_t Address, 2548 const void *Decoder) { 2549 // We have: 2550 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2551 // Invalid if rt == 0 2552 // BLEZALC_MMR6 if rs == 0 && rt != 0 2553 // BGEZALC_MMR6 if rs == rt && rt != 0 2554 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2555 2556 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2557 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2558 InsnType Imm = 0; 2559 bool HasRs = false; 2560 2561 if (Rt == 0) 2562 return MCDisassembler::Fail; 2563 else if (Rs == 0) { 2564 MI.setOpcode(Mips::BLEZALC_MMR6); 2565 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2566 } 2567 else if (Rs == Rt) { 2568 MI.setOpcode(Mips::BGEZALC_MMR6); 2569 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2570 } 2571 else { 2572 HasRs = true; 2573 MI.setOpcode(Mips::BGEUC_MMR6); 2574 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2575 } 2576 2577 if (HasRs) 2578 MI.addOperand( 2579 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2580 MI.addOperand( 2581 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2582 2583 MI.addOperand(MCOperand::createImm(Imm)); 2584 2585 return MCDisassembler::Success; 2586 } 2587