1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 class MipsDisassembler : public MCDisassembler { 34 bool IsMicroMips; 35 bool IsBigEndian; 36 public: 37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 40 IsBigEndian(IsBigEndian) {} 41 42 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 43 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 44 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 45 bool hasMips32r6() const { 46 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 47 } 48 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 49 50 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 51 52 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 53 54 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 55 56 bool hasCOP3() const { 57 // Only present in MIPS-I and MIPS-II 58 return !hasMips32() && !hasMips3(); 59 } 60 61 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 62 ArrayRef<uint8_t> Bytes, uint64_t Address, 63 raw_ostream &VStream, 64 raw_ostream &CStream) const override; 65 }; 66 67 } // end anonymous namespace 68 69 // Forward declare these because the autogenerated code will reference them. 70 // Definitions are further down. 71 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 72 unsigned RegNo, 73 uint64_t Address, 74 const void *Decoder); 75 76 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 77 unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 81 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 102 unsigned Insn, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 112 unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 136 unsigned Insn, 137 uint64_t Address, 138 const void *Decoder); 139 140 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 141 unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 146 unsigned RegNo, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 196 unsigned Offset, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 201 unsigned Offset, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 216 unsigned Offset, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 226 // shifted left by 1 bit. 227 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 233 // shifted left by 1 bit. 234 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 235 unsigned Offset, 236 uint64_t Address, 237 const void *Decoder); 238 239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 240 // shifted left by 1 bit. 241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 242 unsigned Offset, 243 uint64_t Address, 244 const void *Decoder); 245 246 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 247 // shifted left by 1 bit. 248 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 249 unsigned Offset, 250 uint64_t Address, 251 const void *Decoder); 252 253 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 254 // shifted left by 1 bit. 255 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 256 unsigned Insn, 257 uint64_t Address, 258 const void *Decoder); 259 260 static DecodeStatus DecodeMem(MCInst &Inst, 261 unsigned Insn, 262 uint64_t Address, 263 const void *Decoder); 264 265 static DecodeStatus DecodeMemEVA(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeCacheOp(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 286 unsigned Insn, 287 uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 291 unsigned Insn, 292 uint64_t Address, 293 const void *Decoder); 294 295 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 296 unsigned Insn, 297 uint64_t Address, 298 const void *Decoder); 299 300 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 301 unsigned Insn, 302 uint64_t Address, 303 const void *Decoder); 304 305 static DecodeStatus DecodeSyncI(MCInst &Inst, 306 unsigned Insn, 307 uint64_t Address, 308 const void *Decoder); 309 310 static DecodeStatus DecodeSynciR6(MCInst &Inst, 311 unsigned Insn, 312 uint64_t Address, 313 const void *Decoder); 314 315 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 318 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 319 unsigned Insn, 320 uint64_t Address, 321 const void *Decoder); 322 323 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 324 unsigned Insn, 325 uint64_t Address, 326 const void *Decoder); 327 328 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 329 unsigned Insn, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 334 unsigned Insn, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 339 unsigned Insn, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 344 unsigned Insn, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 349 unsigned Insn, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 354 uint64_t Address, 355 const void *Decoder); 356 357 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 358 uint64_t Address, 359 const void *Decoder); 360 361 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 370 uint64_t Address, 371 const void *Decoder); 372 373 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 374 uint64_t Address, 375 const void *Decoder); 376 377 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 378 unsigned Insn, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 383 unsigned Value, 384 uint64_t Address, 385 const void *Decoder); 386 387 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 388 unsigned Value, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 393 unsigned Value, 394 uint64_t Address, 395 const void *Decoder); 396 397 template <unsigned Bits, int Offset, int Scale> 398 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 399 uint64_t Address, 400 const void *Decoder); 401 402 template <unsigned Bits, int Offset> 403 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 404 uint64_t Address, 405 const void *Decoder) { 406 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 407 Decoder); 408 } 409 410 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 411 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 412 uint64_t Address, 413 const void *Decoder); 414 415 static DecodeStatus DecodeInsSize(MCInst &Inst, 416 unsigned Insn, 417 uint64_t Address, 418 const void *Decoder); 419 420 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 421 uint64_t Address, const void *Decoder); 422 423 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 424 uint64_t Address, const void *Decoder); 425 426 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void *Decoder); 428 429 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 430 uint64_t Address, const void *Decoder); 431 432 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 433 uint64_t Address, const void *Decoder); 434 435 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 436 /// handle. 437 template <typename InsnType> 438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 439 const void *Decoder); 440 441 template <typename InsnType> 442 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 443 const void *Decoder); 444 445 template <typename InsnType> 446 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 447 const void *Decoder); 448 449 template <typename InsnType> 450 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 451 const void *Decoder); 452 453 template <typename InsnType> 454 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 455 const void *Decoder); 456 457 template <typename InsnType> 458 static DecodeStatus 459 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 460 const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus 464 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 465 const void *Decoder); 466 467 template <typename InsnType> 468 static DecodeStatus 469 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 470 const void *Decoder); 471 472 template <typename InsnType> 473 static DecodeStatus 474 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 475 const void *Decoder); 476 477 template <typename InsnType> 478 static DecodeStatus 479 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 480 const void *Decoder); 481 482 template <typename InsnType> 483 static DecodeStatus 484 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 485 const void *Decoder); 486 487 template <typename InsnType> 488 static DecodeStatus 489 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 490 const void *Decoder); 491 492 template <typename InsnType> 493 static DecodeStatus 494 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 495 const void *Decoder); 496 497 template <typename InsnType> 498 static DecodeStatus 499 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 500 const void *Decoder); 501 502 template <typename InsnType> 503 static DecodeStatus 504 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 505 const void *Decoder); 506 507 template <typename InsnType> 508 static DecodeStatus 509 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 510 const void *Decoder); 511 512 template <typename InsnType> 513 static DecodeStatus 514 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 515 const void *Decoder); 516 517 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 518 uint64_t Address, 519 const void *Decoder); 520 521 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 522 uint64_t Address, 523 const void *Decoder); 524 525 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 526 uint64_t Address, 527 const void *Decoder); 528 529 namespace llvm { 530 Target &getTheMipselTarget(); 531 Target &getTheMipsTarget(); 532 Target &getTheMips64Target(); 533 Target &getTheMips64elTarget(); 534 } 535 536 static MCDisassembler *createMipsDisassembler( 537 const Target &T, 538 const MCSubtargetInfo &STI, 539 MCContext &Ctx) { 540 return new MipsDisassembler(STI, Ctx, true); 541 } 542 543 static MCDisassembler *createMipselDisassembler( 544 const Target &T, 545 const MCSubtargetInfo &STI, 546 MCContext &Ctx) { 547 return new MipsDisassembler(STI, Ctx, false); 548 } 549 550 extern "C" void LLVMInitializeMipsDisassembler() { 551 // Register the disassembler. 552 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 553 createMipsDisassembler); 554 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 555 createMipselDisassembler); 556 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 557 createMipsDisassembler); 558 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 559 createMipselDisassembler); 560 } 561 562 #include "MipsGenDisassemblerTables.inc" 563 564 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 565 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 566 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 567 return *(RegInfo->getRegClass(RC).begin() + RegNo); 568 } 569 570 template <typename InsnType> 571 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 572 const void *Decoder) { 573 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 574 // The size of the n field depends on the element size 575 // The register class also depends on this. 576 InsnType tmp = fieldFromInstruction(insn, 17, 5); 577 unsigned NSize = 0; 578 DecodeFN RegDecoder = nullptr; 579 if ((tmp & 0x18) == 0x00) { // INSVE_B 580 NSize = 4; 581 RegDecoder = DecodeMSA128BRegisterClass; 582 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 583 NSize = 3; 584 RegDecoder = DecodeMSA128HRegisterClass; 585 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 586 NSize = 2; 587 RegDecoder = DecodeMSA128WRegisterClass; 588 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 589 NSize = 1; 590 RegDecoder = DecodeMSA128DRegisterClass; 591 } else 592 llvm_unreachable("Invalid encoding"); 593 594 assert(NSize != 0 && RegDecoder != nullptr); 595 596 // $wd 597 tmp = fieldFromInstruction(insn, 6, 5); 598 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 599 return MCDisassembler::Fail; 600 // $wd_in 601 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 602 return MCDisassembler::Fail; 603 // $n 604 tmp = fieldFromInstruction(insn, 16, NSize); 605 MI.addOperand(MCOperand::createImm(tmp)); 606 // $ws 607 tmp = fieldFromInstruction(insn, 11, 5); 608 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 609 return MCDisassembler::Fail; 610 // $n2 611 MI.addOperand(MCOperand::createImm(0)); 612 613 return MCDisassembler::Success; 614 } 615 616 template <typename InsnType> 617 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 618 const void *Decoder) { 619 InsnType Rs = fieldFromInstruction(insn, 16, 5); 620 InsnType Imm = fieldFromInstruction(insn, 0, 16); 621 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 622 Rs))); 623 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 624 Rs))); 625 MI.addOperand(MCOperand::createImm(Imm)); 626 627 return MCDisassembler::Success; 628 } 629 630 template <typename InsnType> 631 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 632 const void *Decoder) { 633 InsnType Rs = fieldFromInstruction(insn, 21, 5); 634 InsnType Imm = fieldFromInstruction(insn, 0, 16); 635 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 636 Rs))); 637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 638 Rs))); 639 MI.addOperand(MCOperand::createImm(Imm)); 640 641 return MCDisassembler::Success; 642 } 643 644 template <typename InsnType> 645 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 646 uint64_t Address, 647 const void *Decoder) { 648 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 649 // (otherwise we would have matched the ADDI instruction from the earlier 650 // ISA's instead). 651 // 652 // We have: 653 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 654 // BOVC if rs >= rt 655 // BEQZALC if rs == 0 && rt != 0 656 // BEQC if rs < rt && rs != 0 657 658 InsnType Rs = fieldFromInstruction(insn, 21, 5); 659 InsnType Rt = fieldFromInstruction(insn, 16, 5); 660 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 661 bool HasRs = false; 662 663 if (Rs >= Rt) { 664 MI.setOpcode(Mips::BOVC); 665 HasRs = true; 666 } else if (Rs != 0 && Rs < Rt) { 667 MI.setOpcode(Mips::BEQC); 668 HasRs = true; 669 } else 670 MI.setOpcode(Mips::BEQZALC); 671 672 if (HasRs) 673 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 674 Rs))); 675 676 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 677 Rt))); 678 MI.addOperand(MCOperand::createImm(Imm)); 679 680 return MCDisassembler::Success; 681 } 682 683 template <typename InsnType> 684 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 685 uint64_t Address, 686 const void *Decoder) { 687 InsnType Rt = fieldFromInstruction(insn, 21, 5); 688 InsnType Rs = fieldFromInstruction(insn, 16, 5); 689 int64_t Imm = 0; 690 691 if (Rs >= Rt) { 692 MI.setOpcode(Mips::BOVC_MMR6); 693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 694 Rt))); 695 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 696 Rs))); 697 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 698 } else if (Rs != 0 && Rs < Rt) { 699 MI.setOpcode(Mips::BEQC_MMR6); 700 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 701 Rs))); 702 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 703 Rt))); 704 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 705 } else { 706 MI.setOpcode(Mips::BEQZALC_MMR6); 707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 708 Rt))); 709 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 710 } 711 712 MI.addOperand(MCOperand::createImm(Imm)); 713 714 return MCDisassembler::Success; 715 } 716 717 template <typename InsnType> 718 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 719 uint64_t Address, 720 const void *Decoder) { 721 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 722 // (otherwise we would have matched the ADDI instruction from the earlier 723 // ISA's instead). 724 // 725 // We have: 726 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 727 // BNVC if rs >= rt 728 // BNEZALC if rs == 0 && rt != 0 729 // BNEC if rs < rt && rs != 0 730 731 InsnType Rs = fieldFromInstruction(insn, 21, 5); 732 InsnType Rt = fieldFromInstruction(insn, 16, 5); 733 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 734 bool HasRs = false; 735 736 if (Rs >= Rt) { 737 MI.setOpcode(Mips::BNVC); 738 HasRs = true; 739 } else if (Rs != 0 && Rs < Rt) { 740 MI.setOpcode(Mips::BNEC); 741 HasRs = true; 742 } else 743 MI.setOpcode(Mips::BNEZALC); 744 745 if (HasRs) 746 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 747 Rs))); 748 749 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 750 Rt))); 751 MI.addOperand(MCOperand::createImm(Imm)); 752 753 return MCDisassembler::Success; 754 } 755 756 template <typename InsnType> 757 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 758 uint64_t Address, 759 const void *Decoder) { 760 InsnType Rt = fieldFromInstruction(insn, 21, 5); 761 InsnType Rs = fieldFromInstruction(insn, 16, 5); 762 int64_t Imm = 0; 763 764 if (Rs >= Rt) { 765 MI.setOpcode(Mips::BNVC_MMR6); 766 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 767 Rt))); 768 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 769 Rs))); 770 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 771 } else if (Rs != 0 && Rs < Rt) { 772 MI.setOpcode(Mips::BNEC_MMR6); 773 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 774 Rs))); 775 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 776 Rt))); 777 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 778 } else { 779 MI.setOpcode(Mips::BNEZALC_MMR6); 780 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 781 Rt))); 782 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 783 } 784 785 MI.addOperand(MCOperand::createImm(Imm)); 786 787 return MCDisassembler::Success; 788 } 789 790 template <typename InsnType> 791 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 792 uint64_t Address, 793 const void *Decoder) { 794 // We have: 795 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 796 // Invalid if rt == 0 797 // BGTZC_MMR6 if rs == 0 && rt != 0 798 // BLTZC_MMR6 if rs == rt && rt != 0 799 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 800 801 InsnType Rt = fieldFromInstruction(insn, 21, 5); 802 InsnType Rs = fieldFromInstruction(insn, 16, 5); 803 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 804 bool HasRs = false; 805 806 if (Rt == 0) 807 return MCDisassembler::Fail; 808 else if (Rs == 0) 809 MI.setOpcode(Mips::BGTZC_MMR6); 810 else if (Rs == Rt) 811 MI.setOpcode(Mips::BLTZC_MMR6); 812 else { 813 MI.setOpcode(Mips::BLTC_MMR6); 814 HasRs = true; 815 } 816 817 if (HasRs) 818 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 819 Rs))); 820 821 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 822 Rt))); 823 824 MI.addOperand(MCOperand::createImm(Imm)); 825 826 return MCDisassembler::Success; 827 } 828 829 template <typename InsnType> 830 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 831 uint64_t Address, 832 const void *Decoder) { 833 // We have: 834 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 835 // Invalid if rt == 0 836 // BLEZC_MMR6 if rs == 0 && rt != 0 837 // BGEZC_MMR6 if rs == rt && rt != 0 838 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 839 840 InsnType Rt = fieldFromInstruction(insn, 21, 5); 841 InsnType Rs = fieldFromInstruction(insn, 16, 5); 842 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 843 bool HasRs = false; 844 845 if (Rt == 0) 846 return MCDisassembler::Fail; 847 else if (Rs == 0) 848 MI.setOpcode(Mips::BLEZC_MMR6); 849 else if (Rs == Rt) 850 MI.setOpcode(Mips::BGEZC_MMR6); 851 else { 852 HasRs = true; 853 MI.setOpcode(Mips::BGEC_MMR6); 854 } 855 856 if (HasRs) 857 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 858 Rs))); 859 860 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 861 Rt))); 862 863 MI.addOperand(MCOperand::createImm(Imm)); 864 865 return MCDisassembler::Success; 866 } 867 868 template <typename InsnType> 869 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 870 uint64_t Address, 871 const void *Decoder) { 872 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 873 // (otherwise we would have matched the BLEZL instruction from the earlier 874 // ISA's instead). 875 // 876 // We have: 877 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 878 // Invalid if rs == 0 879 // BLEZC if rs == 0 && rt != 0 880 // BGEZC if rs == rt && rt != 0 881 // BGEC if rs != rt && rs != 0 && rt != 0 882 883 InsnType Rs = fieldFromInstruction(insn, 21, 5); 884 InsnType Rt = fieldFromInstruction(insn, 16, 5); 885 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 886 bool HasRs = false; 887 888 if (Rt == 0) 889 return MCDisassembler::Fail; 890 else if (Rs == 0) 891 MI.setOpcode(Mips::BLEZC); 892 else if (Rs == Rt) 893 MI.setOpcode(Mips::BGEZC); 894 else { 895 HasRs = true; 896 MI.setOpcode(Mips::BGEC); 897 } 898 899 if (HasRs) 900 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 901 Rs))); 902 903 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 904 Rt))); 905 906 MI.addOperand(MCOperand::createImm(Imm)); 907 908 return MCDisassembler::Success; 909 } 910 911 template <typename InsnType> 912 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 913 uint64_t Address, 914 const void *Decoder) { 915 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 916 // (otherwise we would have matched the BGTZL instruction from the earlier 917 // ISA's instead). 918 // 919 // We have: 920 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 921 // Invalid if rs == 0 922 // BGTZC if rs == 0 && rt != 0 923 // BLTZC if rs == rt && rt != 0 924 // BLTC if rs != rt && rs != 0 && rt != 0 925 926 bool HasRs = false; 927 928 InsnType Rs = fieldFromInstruction(insn, 21, 5); 929 InsnType Rt = fieldFromInstruction(insn, 16, 5); 930 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 931 932 if (Rt == 0) 933 return MCDisassembler::Fail; 934 else if (Rs == 0) 935 MI.setOpcode(Mips::BGTZC); 936 else if (Rs == Rt) 937 MI.setOpcode(Mips::BLTZC); 938 else { 939 MI.setOpcode(Mips::BLTC); 940 HasRs = true; 941 } 942 943 if (HasRs) 944 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 945 Rs))); 946 947 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 948 Rt))); 949 950 MI.addOperand(MCOperand::createImm(Imm)); 951 952 return MCDisassembler::Success; 953 } 954 955 template <typename InsnType> 956 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 957 uint64_t Address, 958 const void *Decoder) { 959 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 960 // (otherwise we would have matched the BGTZ instruction from the earlier 961 // ISA's instead). 962 // 963 // We have: 964 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 965 // BGTZ if rt == 0 966 // BGTZALC if rs == 0 && rt != 0 967 // BLTZALC if rs != 0 && rs == rt 968 // BLTUC if rs != 0 && rs != rt 969 970 InsnType Rs = fieldFromInstruction(insn, 21, 5); 971 InsnType Rt = fieldFromInstruction(insn, 16, 5); 972 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 973 bool HasRs = false; 974 bool HasRt = false; 975 976 if (Rt == 0) { 977 MI.setOpcode(Mips::BGTZ); 978 HasRs = true; 979 } else if (Rs == 0) { 980 MI.setOpcode(Mips::BGTZALC); 981 HasRt = true; 982 } else if (Rs == Rt) { 983 MI.setOpcode(Mips::BLTZALC); 984 HasRs = true; 985 } else { 986 MI.setOpcode(Mips::BLTUC); 987 HasRs = true; 988 HasRt = true; 989 } 990 991 if (HasRs) 992 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 993 Rs))); 994 995 if (HasRt) 996 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 997 Rt))); 998 999 MI.addOperand(MCOperand::createImm(Imm)); 1000 1001 return MCDisassembler::Success; 1002 } 1003 1004 template <typename InsnType> 1005 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1006 uint64_t Address, 1007 const void *Decoder) { 1008 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1009 // (otherwise we would have matched the BLEZL instruction from the earlier 1010 // ISA's instead). 1011 // 1012 // We have: 1013 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1014 // Invalid if rs == 0 1015 // BLEZALC if rs == 0 && rt != 0 1016 // BGEZALC if rs == rt && rt != 0 1017 // BGEUC if rs != rt && rs != 0 && rt != 0 1018 1019 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1020 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1021 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1022 bool HasRs = false; 1023 1024 if (Rt == 0) 1025 return MCDisassembler::Fail; 1026 else if (Rs == 0) 1027 MI.setOpcode(Mips::BLEZALC); 1028 else if (Rs == Rt) 1029 MI.setOpcode(Mips::BGEZALC); 1030 else { 1031 HasRs = true; 1032 MI.setOpcode(Mips::BGEUC); 1033 } 1034 1035 if (HasRs) 1036 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1037 Rs))); 1038 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1039 Rt))); 1040 1041 MI.addOperand(MCOperand::createImm(Imm)); 1042 1043 return MCDisassembler::Success; 1044 } 1045 1046 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1047 /// according to the given endianness. 1048 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1049 uint64_t &Size, uint32_t &Insn, 1050 bool IsBigEndian) { 1051 // We want to read exactly 2 Bytes of data. 1052 if (Bytes.size() < 2) { 1053 Size = 0; 1054 return MCDisassembler::Fail; 1055 } 1056 1057 if (IsBigEndian) { 1058 Insn = (Bytes[0] << 8) | Bytes[1]; 1059 } else { 1060 Insn = (Bytes[1] << 8) | Bytes[0]; 1061 } 1062 1063 return MCDisassembler::Success; 1064 } 1065 1066 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1067 /// according to the given endianness. 1068 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1069 uint64_t &Size, uint32_t &Insn, 1070 bool IsBigEndian, bool IsMicroMips) { 1071 // We want to read exactly 4 Bytes of data. 1072 if (Bytes.size() < 4) { 1073 Size = 0; 1074 return MCDisassembler::Fail; 1075 } 1076 1077 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1078 // always precede the low 16 bits in the instruction stream (that is, they 1079 // are placed at lower addresses in the instruction stream). 1080 // 1081 // microMIPS byte ordering: 1082 // Big-endian: 0 | 1 | 2 | 3 1083 // Little-endian: 1 | 0 | 3 | 2 1084 1085 if (IsBigEndian) { 1086 // Encoded as a big-endian 32-bit word in the stream. 1087 Insn = 1088 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1089 } else { 1090 if (IsMicroMips) { 1091 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1092 (Bytes[1] << 24); 1093 } else { 1094 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1095 (Bytes[3] << 24); 1096 } 1097 } 1098 1099 return MCDisassembler::Success; 1100 } 1101 1102 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1103 ArrayRef<uint8_t> Bytes, 1104 uint64_t Address, 1105 raw_ostream &VStream, 1106 raw_ostream &CStream) const { 1107 uint32_t Insn; 1108 DecodeStatus Result; 1109 1110 if (IsMicroMips) { 1111 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1112 if (Result == MCDisassembler::Fail) 1113 return MCDisassembler::Fail; 1114 1115 if (hasMips32r6()) { 1116 DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1117 // Calling the auto-generated decoder function for microMIPS32R6 1118 // (and microMIPS64R6) 16-bit instructions. 1119 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1120 Address, this, STI); 1121 if (Result != MCDisassembler::Fail) { 1122 Size = 2; 1123 return Result; 1124 } 1125 } 1126 1127 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1128 // Calling the auto-generated decoder function for microMIPS 16-bit 1129 // instructions. 1130 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1131 this, STI); 1132 if (Result != MCDisassembler::Fail) { 1133 Size = 2; 1134 return Result; 1135 } 1136 1137 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1138 if (Result == MCDisassembler::Fail) 1139 return MCDisassembler::Fail; 1140 1141 if (hasMips32r6()) { 1142 DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1143 // Calling the auto-generated decoder function. 1144 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1145 this, STI); 1146 if (Result != MCDisassembler::Fail) { 1147 Size = 4; 1148 return Result; 1149 } 1150 } 1151 1152 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1153 // Calling the auto-generated decoder function. 1154 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1155 this, STI); 1156 if (Result != MCDisassembler::Fail) { 1157 Size = 4; 1158 return Result; 1159 } 1160 1161 if (hasMips32r6() && isFP64()) { 1162 DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); 1163 Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, 1164 Address, this, STI); 1165 if (Result != MCDisassembler::Fail) { 1166 Size = 4; 1167 return Result; 1168 } 1169 } 1170 1171 // This is an invalid instruction. Let the disassembler move forward by the 1172 // minimum instruction size. 1173 Size = 2; 1174 return MCDisassembler::Fail; 1175 } 1176 1177 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1178 if (Result == MCDisassembler::Fail) { 1179 Size = 4; 1180 return MCDisassembler::Fail; 1181 } 1182 1183 if (hasCOP3()) { 1184 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1185 Result = 1186 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1187 if (Result != MCDisassembler::Fail) { 1188 Size = 4; 1189 return Result; 1190 } 1191 } 1192 1193 if (hasMips32r6() && isGP64()) { 1194 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1195 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1196 Address, this, STI); 1197 if (Result != MCDisassembler::Fail) { 1198 Size = 4; 1199 return Result; 1200 } 1201 } 1202 1203 if (hasMips32r6() && isPTR64()) { 1204 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1205 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1206 Address, this, STI); 1207 if (Result != MCDisassembler::Fail) { 1208 Size = 4; 1209 return Result; 1210 } 1211 } 1212 1213 if (hasMips32r6()) { 1214 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1215 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1216 Address, this, STI); 1217 if (Result != MCDisassembler::Fail) { 1218 Size = 4; 1219 return Result; 1220 } 1221 } 1222 1223 if (hasMips2() && isPTR64()) { 1224 DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1225 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1226 Address, this, STI); 1227 if (Result != MCDisassembler::Fail) { 1228 Size = 4; 1229 return Result; 1230 } 1231 } 1232 1233 if (hasCnMips()) { 1234 DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1235 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1236 Address, this, STI); 1237 if (Result != MCDisassembler::Fail) { 1238 Size = 4; 1239 return Result; 1240 } 1241 } 1242 1243 if (isGP64()) { 1244 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1245 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1246 Address, this, STI); 1247 if (Result != MCDisassembler::Fail) { 1248 Size = 4; 1249 return Result; 1250 } 1251 } 1252 1253 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1254 // Calling the auto-generated decoder function. 1255 Result = 1256 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1257 if (Result != MCDisassembler::Fail) { 1258 Size = 4; 1259 return Result; 1260 } 1261 1262 Size = 4; 1263 return MCDisassembler::Fail; 1264 } 1265 1266 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1267 unsigned RegNo, 1268 uint64_t Address, 1269 const void *Decoder) { 1270 1271 return MCDisassembler::Fail; 1272 1273 } 1274 1275 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1276 unsigned RegNo, 1277 uint64_t Address, 1278 const void *Decoder) { 1279 1280 if (RegNo > 31) 1281 return MCDisassembler::Fail; 1282 1283 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1284 Inst.addOperand(MCOperand::createReg(Reg)); 1285 return MCDisassembler::Success; 1286 } 1287 1288 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1289 unsigned RegNo, 1290 uint64_t Address, 1291 const void *Decoder) { 1292 if (RegNo > 7) 1293 return MCDisassembler::Fail; 1294 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1295 Inst.addOperand(MCOperand::createReg(Reg)); 1296 return MCDisassembler::Success; 1297 } 1298 1299 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1300 unsigned RegNo, 1301 uint64_t Address, 1302 const void *Decoder) { 1303 if (RegNo > 7) 1304 return MCDisassembler::Fail; 1305 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1306 Inst.addOperand(MCOperand::createReg(Reg)); 1307 return MCDisassembler::Success; 1308 } 1309 1310 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1311 unsigned RegNo, 1312 uint64_t Address, 1313 const void *Decoder) { 1314 if (RegNo > 7) 1315 return MCDisassembler::Fail; 1316 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1317 Inst.addOperand(MCOperand::createReg(Reg)); 1318 return MCDisassembler::Success; 1319 } 1320 1321 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1322 unsigned RegNo, 1323 uint64_t Address, 1324 const void *Decoder) { 1325 if (RegNo > 31) 1326 return MCDisassembler::Fail; 1327 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1328 Inst.addOperand(MCOperand::createReg(Reg)); 1329 return MCDisassembler::Success; 1330 } 1331 1332 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1333 unsigned RegNo, 1334 uint64_t Address, 1335 const void *Decoder) { 1336 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1337 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1338 1339 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1340 } 1341 1342 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1343 unsigned RegNo, 1344 uint64_t Address, 1345 const void *Decoder) { 1346 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1347 } 1348 1349 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1350 unsigned RegNo, 1351 uint64_t Address, 1352 const void *Decoder) { 1353 if (RegNo > 31) 1354 return MCDisassembler::Fail; 1355 1356 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1357 Inst.addOperand(MCOperand::createReg(Reg)); 1358 return MCDisassembler::Success; 1359 } 1360 1361 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1362 unsigned RegNo, 1363 uint64_t Address, 1364 const void *Decoder) { 1365 if (RegNo > 31) 1366 return MCDisassembler::Fail; 1367 1368 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1369 Inst.addOperand(MCOperand::createReg(Reg)); 1370 return MCDisassembler::Success; 1371 } 1372 1373 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1374 unsigned RegNo, 1375 uint64_t Address, 1376 const void *Decoder) { 1377 if (RegNo > 31) 1378 return MCDisassembler::Fail; 1379 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1380 Inst.addOperand(MCOperand::createReg(Reg)); 1381 return MCDisassembler::Success; 1382 } 1383 1384 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1385 unsigned RegNo, 1386 uint64_t Address, 1387 const void *Decoder) { 1388 if (RegNo > 7) 1389 return MCDisassembler::Fail; 1390 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1391 Inst.addOperand(MCOperand::createReg(Reg)); 1392 return MCDisassembler::Success; 1393 } 1394 1395 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1396 uint64_t Address, 1397 const void *Decoder) { 1398 if (RegNo > 31) 1399 return MCDisassembler::Fail; 1400 1401 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1402 Inst.addOperand(MCOperand::createReg(Reg)); 1403 return MCDisassembler::Success; 1404 } 1405 1406 static DecodeStatus DecodeMem(MCInst &Inst, 1407 unsigned Insn, 1408 uint64_t Address, 1409 const void *Decoder) { 1410 int Offset = SignExtend32<16>(Insn & 0xffff); 1411 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1412 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1413 1414 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1415 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1416 1417 if (Inst.getOpcode() == Mips::SC || 1418 Inst.getOpcode() == Mips::SCD) 1419 Inst.addOperand(MCOperand::createReg(Reg)); 1420 1421 Inst.addOperand(MCOperand::createReg(Reg)); 1422 Inst.addOperand(MCOperand::createReg(Base)); 1423 Inst.addOperand(MCOperand::createImm(Offset)); 1424 1425 return MCDisassembler::Success; 1426 } 1427 1428 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1429 unsigned Insn, 1430 uint64_t Address, 1431 const void *Decoder) { 1432 int Offset = SignExtend32<9>(Insn >> 7); 1433 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1434 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1435 1436 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1437 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1438 1439 if (Inst.getOpcode() == Mips::SCE) 1440 Inst.addOperand(MCOperand::createReg(Reg)); 1441 1442 Inst.addOperand(MCOperand::createReg(Reg)); 1443 Inst.addOperand(MCOperand::createReg(Base)); 1444 Inst.addOperand(MCOperand::createImm(Offset)); 1445 1446 return MCDisassembler::Success; 1447 } 1448 1449 static DecodeStatus DecodeLoadByte9(MCInst &Inst, 1450 unsigned Insn, 1451 uint64_t Address, 1452 const void *Decoder) { 1453 int Offset = SignExtend32<9>(Insn & 0x1ff); 1454 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1455 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1456 1457 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1458 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1459 1460 Inst.addOperand(MCOperand::createReg(Reg)); 1461 Inst.addOperand(MCOperand::createReg(Base)); 1462 Inst.addOperand(MCOperand::createImm(Offset)); 1463 1464 return MCDisassembler::Success; 1465 } 1466 1467 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1468 unsigned Insn, 1469 uint64_t Address, 1470 const void *Decoder) { 1471 int Offset = SignExtend32<16>(Insn & 0xffff); 1472 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1473 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1474 1475 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1476 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1477 1478 Inst.addOperand(MCOperand::createReg(Reg)); 1479 Inst.addOperand(MCOperand::createReg(Base)); 1480 Inst.addOperand(MCOperand::createImm(Offset)); 1481 1482 return MCDisassembler::Success; 1483 } 1484 1485 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1486 unsigned Insn, 1487 uint64_t Address, 1488 const void *Decoder) { 1489 int Offset = SignExtend32<16>(Insn & 0xffff); 1490 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1491 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1492 1493 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1494 1495 Inst.addOperand(MCOperand::createReg(Base)); 1496 Inst.addOperand(MCOperand::createImm(Offset)); 1497 Inst.addOperand(MCOperand::createImm(Hint)); 1498 1499 return MCDisassembler::Success; 1500 } 1501 1502 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1503 unsigned Insn, 1504 uint64_t Address, 1505 const void *Decoder) { 1506 int Offset = SignExtend32<12>(Insn & 0xfff); 1507 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1508 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1509 1510 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1511 1512 Inst.addOperand(MCOperand::createReg(Base)); 1513 Inst.addOperand(MCOperand::createImm(Offset)); 1514 Inst.addOperand(MCOperand::createImm(Hint)); 1515 1516 return MCDisassembler::Success; 1517 } 1518 1519 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1520 unsigned Insn, 1521 uint64_t Address, 1522 const void *Decoder) { 1523 int Offset = SignExtend32<9>(Insn & 0x1ff); 1524 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1525 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1526 1527 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1528 1529 Inst.addOperand(MCOperand::createReg(Base)); 1530 Inst.addOperand(MCOperand::createImm(Offset)); 1531 Inst.addOperand(MCOperand::createImm(Hint)); 1532 1533 return MCDisassembler::Success; 1534 } 1535 1536 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1537 unsigned Insn, 1538 uint64_t Address, 1539 const void *Decoder) { 1540 int Offset = SignExtend32<9>(Insn >> 7); 1541 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1542 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1543 1544 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1545 1546 Inst.addOperand(MCOperand::createReg(Base)); 1547 Inst.addOperand(MCOperand::createImm(Offset)); 1548 Inst.addOperand(MCOperand::createImm(Hint)); 1549 1550 return MCDisassembler::Success; 1551 } 1552 1553 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, 1554 unsigned Insn, 1555 uint64_t Address, 1556 const void *Decoder) { 1557 int Offset = SignExtend32<9>(Insn & 0x1ff); 1558 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1559 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1560 1561 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1562 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1563 1564 Inst.addOperand(MCOperand::createReg(Reg)); 1565 Inst.addOperand(MCOperand::createReg(Base)); 1566 Inst.addOperand(MCOperand::createImm(Offset)); 1567 1568 return MCDisassembler::Success; 1569 } 1570 1571 static DecodeStatus DecodeSyncI(MCInst &Inst, 1572 unsigned Insn, 1573 uint64_t Address, 1574 const void *Decoder) { 1575 int Offset = SignExtend32<16>(Insn & 0xffff); 1576 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1577 1578 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1579 1580 Inst.addOperand(MCOperand::createReg(Base)); 1581 Inst.addOperand(MCOperand::createImm(Offset)); 1582 1583 return MCDisassembler::Success; 1584 } 1585 1586 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1587 unsigned Insn, 1588 uint64_t Address, 1589 const void *Decoder) { 1590 int Immediate = SignExtend32<16>(Insn & 0xffff); 1591 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1592 1593 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1594 1595 Inst.addOperand(MCOperand::createReg(Base)); 1596 Inst.addOperand(MCOperand::createImm(Immediate)); 1597 1598 return MCDisassembler::Success; 1599 } 1600 1601 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1602 uint64_t Address, const void *Decoder) { 1603 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1604 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1605 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1606 1607 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1608 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1609 1610 Inst.addOperand(MCOperand::createReg(Reg)); 1611 Inst.addOperand(MCOperand::createReg(Base)); 1612 1613 // The immediate field of an LD/ST instruction is scaled which means it must 1614 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1615 // data format. 1616 // .b - 1 byte 1617 // .h - 2 bytes 1618 // .w - 4 bytes 1619 // .d - 8 bytes 1620 switch(Inst.getOpcode()) 1621 { 1622 default: 1623 assert (0 && "Unexpected instruction"); 1624 return MCDisassembler::Fail; 1625 break; 1626 case Mips::LD_B: 1627 case Mips::ST_B: 1628 Inst.addOperand(MCOperand::createImm(Offset)); 1629 break; 1630 case Mips::LD_H: 1631 case Mips::ST_H: 1632 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1633 break; 1634 case Mips::LD_W: 1635 case Mips::ST_W: 1636 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1637 break; 1638 case Mips::LD_D: 1639 case Mips::ST_D: 1640 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1641 break; 1642 } 1643 1644 return MCDisassembler::Success; 1645 } 1646 1647 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1648 unsigned Insn, 1649 uint64_t Address, 1650 const void *Decoder) { 1651 unsigned Offset = Insn & 0xf; 1652 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1653 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1654 1655 switch (Inst.getOpcode()) { 1656 case Mips::LBU16_MM: 1657 case Mips::LHU16_MM: 1658 case Mips::LW16_MM: 1659 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1660 == MCDisassembler::Fail) 1661 return MCDisassembler::Fail; 1662 break; 1663 case Mips::SB16_MM: 1664 case Mips::SB16_MMR6: 1665 case Mips::SH16_MM: 1666 case Mips::SH16_MMR6: 1667 case Mips::SW16_MM: 1668 case Mips::SW16_MMR6: 1669 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1670 == MCDisassembler::Fail) 1671 return MCDisassembler::Fail; 1672 break; 1673 } 1674 1675 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1676 == MCDisassembler::Fail) 1677 return MCDisassembler::Fail; 1678 1679 switch (Inst.getOpcode()) { 1680 case Mips::LBU16_MM: 1681 if (Offset == 0xf) 1682 Inst.addOperand(MCOperand::createImm(-1)); 1683 else 1684 Inst.addOperand(MCOperand::createImm(Offset)); 1685 break; 1686 case Mips::SB16_MM: 1687 case Mips::SB16_MMR6: 1688 Inst.addOperand(MCOperand::createImm(Offset)); 1689 break; 1690 case Mips::LHU16_MM: 1691 case Mips::SH16_MM: 1692 case Mips::SH16_MMR6: 1693 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1694 break; 1695 case Mips::LW16_MM: 1696 case Mips::SW16_MM: 1697 case Mips::SW16_MMR6: 1698 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1699 break; 1700 } 1701 1702 return MCDisassembler::Success; 1703 } 1704 1705 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1706 unsigned Insn, 1707 uint64_t Address, 1708 const void *Decoder) { 1709 unsigned Offset = Insn & 0x1F; 1710 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1711 1712 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1713 1714 Inst.addOperand(MCOperand::createReg(Reg)); 1715 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1716 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1717 1718 return MCDisassembler::Success; 1719 } 1720 1721 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1722 unsigned Insn, 1723 uint64_t Address, 1724 const void *Decoder) { 1725 unsigned Offset = Insn & 0x7F; 1726 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1727 1728 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1729 1730 Inst.addOperand(MCOperand::createReg(Reg)); 1731 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1732 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1733 1734 return MCDisassembler::Success; 1735 } 1736 1737 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1738 unsigned Insn, 1739 uint64_t Address, 1740 const void *Decoder) { 1741 int Offset; 1742 switch (Inst.getOpcode()) { 1743 case Mips::LWM16_MMR6: 1744 case Mips::SWM16_MMR6: 1745 Offset = fieldFromInstruction(Insn, 4, 4); 1746 break; 1747 default: 1748 Offset = SignExtend32<4>(Insn & 0xf); 1749 break; 1750 } 1751 1752 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1753 == MCDisassembler::Fail) 1754 return MCDisassembler::Fail; 1755 1756 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1757 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1758 1759 return MCDisassembler::Success; 1760 } 1761 1762 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1763 unsigned Insn, 1764 uint64_t Address, 1765 const void *Decoder) { 1766 int Offset = SignExtend32<9>(Insn & 0x1ff); 1767 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1768 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1769 1770 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1771 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1772 1773 if (Inst.getOpcode() == Mips::SCE_MM) 1774 Inst.addOperand(MCOperand::createReg(Reg)); 1775 1776 Inst.addOperand(MCOperand::createReg(Reg)); 1777 Inst.addOperand(MCOperand::createReg(Base)); 1778 Inst.addOperand(MCOperand::createImm(Offset)); 1779 1780 return MCDisassembler::Success; 1781 } 1782 1783 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1784 unsigned Insn, 1785 uint64_t Address, 1786 const void *Decoder) { 1787 int Offset = SignExtend32<12>(Insn & 0x0fff); 1788 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1789 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1790 1791 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1792 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1793 1794 switch (Inst.getOpcode()) { 1795 case Mips::SWM32_MM: 1796 case Mips::LWM32_MM: 1797 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1798 == MCDisassembler::Fail) 1799 return MCDisassembler::Fail; 1800 Inst.addOperand(MCOperand::createReg(Base)); 1801 Inst.addOperand(MCOperand::createImm(Offset)); 1802 break; 1803 case Mips::SC_MM: 1804 Inst.addOperand(MCOperand::createReg(Reg)); 1805 LLVM_FALLTHROUGH; 1806 default: 1807 Inst.addOperand(MCOperand::createReg(Reg)); 1808 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1809 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1810 Inst.addOperand(MCOperand::createReg(Reg+1)); 1811 1812 Inst.addOperand(MCOperand::createReg(Base)); 1813 Inst.addOperand(MCOperand::createImm(Offset)); 1814 } 1815 1816 return MCDisassembler::Success; 1817 } 1818 1819 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1820 unsigned Insn, 1821 uint64_t Address, 1822 const void *Decoder) { 1823 int Offset = SignExtend32<16>(Insn & 0xffff); 1824 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1825 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1826 1827 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1828 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1829 1830 Inst.addOperand(MCOperand::createReg(Reg)); 1831 Inst.addOperand(MCOperand::createReg(Base)); 1832 Inst.addOperand(MCOperand::createImm(Offset)); 1833 1834 return MCDisassembler::Success; 1835 } 1836 1837 static DecodeStatus DecodeFMem(MCInst &Inst, 1838 unsigned Insn, 1839 uint64_t Address, 1840 const void *Decoder) { 1841 int Offset = SignExtend32<16>(Insn & 0xffff); 1842 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1843 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1844 1845 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1846 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1847 1848 Inst.addOperand(MCOperand::createReg(Reg)); 1849 Inst.addOperand(MCOperand::createReg(Base)); 1850 Inst.addOperand(MCOperand::createImm(Offset)); 1851 1852 return MCDisassembler::Success; 1853 } 1854 1855 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1856 uint64_t Address, const void *Decoder) { 1857 // This function is the same as DecodeFMem but with the Reg and Base fields 1858 // swapped according to microMIPS spec. 1859 int Offset = SignExtend32<16>(Insn & 0xffff); 1860 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1861 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1862 1863 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1864 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1865 1866 Inst.addOperand(MCOperand::createReg(Reg)); 1867 Inst.addOperand(MCOperand::createReg(Base)); 1868 Inst.addOperand(MCOperand::createImm(Offset)); 1869 1870 return MCDisassembler::Success; 1871 } 1872 1873 static DecodeStatus DecodeFMem2(MCInst &Inst, 1874 unsigned Insn, 1875 uint64_t Address, 1876 const void *Decoder) { 1877 int Offset = SignExtend32<16>(Insn & 0xffff); 1878 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1879 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1880 1881 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1882 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1883 1884 Inst.addOperand(MCOperand::createReg(Reg)); 1885 Inst.addOperand(MCOperand::createReg(Base)); 1886 Inst.addOperand(MCOperand::createImm(Offset)); 1887 1888 return MCDisassembler::Success; 1889 } 1890 1891 static DecodeStatus DecodeFMem3(MCInst &Inst, 1892 unsigned Insn, 1893 uint64_t Address, 1894 const void *Decoder) { 1895 int Offset = SignExtend32<16>(Insn & 0xffff); 1896 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1897 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1898 1899 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1900 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1901 1902 Inst.addOperand(MCOperand::createReg(Reg)); 1903 Inst.addOperand(MCOperand::createReg(Base)); 1904 Inst.addOperand(MCOperand::createImm(Offset)); 1905 1906 return MCDisassembler::Success; 1907 } 1908 1909 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1910 unsigned Insn, 1911 uint64_t Address, 1912 const void *Decoder) { 1913 int Offset = SignExtend32<11>(Insn & 0x07ff); 1914 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1915 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1916 1917 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1918 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1919 1920 Inst.addOperand(MCOperand::createReg(Reg)); 1921 Inst.addOperand(MCOperand::createReg(Base)); 1922 Inst.addOperand(MCOperand::createImm(Offset)); 1923 1924 return MCDisassembler::Success; 1925 } 1926 1927 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 1928 uint64_t Address, const void *Decoder) { 1929 int Offset = SignExtend32<11>(Insn & 0x07ff); 1930 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1931 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1932 1933 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1934 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1935 1936 Inst.addOperand(MCOperand::createReg(Reg)); 1937 Inst.addOperand(MCOperand::createReg(Base)); 1938 Inst.addOperand(MCOperand::createImm(Offset)); 1939 1940 return MCDisassembler::Success; 1941 } 1942 1943 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1944 unsigned Insn, 1945 uint64_t Address, 1946 const void *Decoder) { 1947 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1948 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1949 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1950 1951 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1952 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1953 1954 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1955 Inst.addOperand(MCOperand::createReg(Rt)); 1956 } 1957 1958 Inst.addOperand(MCOperand::createReg(Rt)); 1959 Inst.addOperand(MCOperand::createReg(Base)); 1960 Inst.addOperand(MCOperand::createImm(Offset)); 1961 1962 return MCDisassembler::Success; 1963 } 1964 1965 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1966 unsigned RegNo, 1967 uint64_t Address, 1968 const void *Decoder) { 1969 // Currently only hardware register 29 is supported. 1970 if (RegNo != 29) 1971 return MCDisassembler::Fail; 1972 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 1973 return MCDisassembler::Success; 1974 } 1975 1976 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1977 unsigned RegNo, 1978 uint64_t Address, 1979 const void *Decoder) { 1980 if (RegNo > 30 || RegNo %2) 1981 return MCDisassembler::Fail; 1982 1983 ; 1984 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1985 Inst.addOperand(MCOperand::createReg(Reg)); 1986 return MCDisassembler::Success; 1987 } 1988 1989 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1990 unsigned RegNo, 1991 uint64_t Address, 1992 const void *Decoder) { 1993 if (RegNo >= 4) 1994 return MCDisassembler::Fail; 1995 1996 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1997 Inst.addOperand(MCOperand::createReg(Reg)); 1998 return MCDisassembler::Success; 1999 } 2000 2001 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2002 unsigned RegNo, 2003 uint64_t Address, 2004 const void *Decoder) { 2005 if (RegNo >= 4) 2006 return MCDisassembler::Fail; 2007 2008 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2009 Inst.addOperand(MCOperand::createReg(Reg)); 2010 return MCDisassembler::Success; 2011 } 2012 2013 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2014 unsigned RegNo, 2015 uint64_t Address, 2016 const void *Decoder) { 2017 if (RegNo >= 4) 2018 return MCDisassembler::Fail; 2019 2020 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2021 Inst.addOperand(MCOperand::createReg(Reg)); 2022 return MCDisassembler::Success; 2023 } 2024 2025 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2026 unsigned RegNo, 2027 uint64_t Address, 2028 const void *Decoder) { 2029 if (RegNo > 31) 2030 return MCDisassembler::Fail; 2031 2032 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2033 Inst.addOperand(MCOperand::createReg(Reg)); 2034 return MCDisassembler::Success; 2035 } 2036 2037 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2038 unsigned RegNo, 2039 uint64_t Address, 2040 const void *Decoder) { 2041 if (RegNo > 31) 2042 return MCDisassembler::Fail; 2043 2044 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2045 Inst.addOperand(MCOperand::createReg(Reg)); 2046 return MCDisassembler::Success; 2047 } 2048 2049 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2050 unsigned RegNo, 2051 uint64_t Address, 2052 const void *Decoder) { 2053 if (RegNo > 31) 2054 return MCDisassembler::Fail; 2055 2056 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2057 Inst.addOperand(MCOperand::createReg(Reg)); 2058 return MCDisassembler::Success; 2059 } 2060 2061 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2062 unsigned RegNo, 2063 uint64_t Address, 2064 const void *Decoder) { 2065 if (RegNo > 31) 2066 return MCDisassembler::Fail; 2067 2068 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2069 Inst.addOperand(MCOperand::createReg(Reg)); 2070 return MCDisassembler::Success; 2071 } 2072 2073 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2074 unsigned RegNo, 2075 uint64_t Address, 2076 const void *Decoder) { 2077 if (RegNo > 7) 2078 return MCDisassembler::Fail; 2079 2080 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2081 Inst.addOperand(MCOperand::createReg(Reg)); 2082 return MCDisassembler::Success; 2083 } 2084 2085 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2086 unsigned RegNo, 2087 uint64_t Address, 2088 const void *Decoder) { 2089 if (RegNo > 31) 2090 return MCDisassembler::Fail; 2091 2092 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2093 Inst.addOperand(MCOperand::createReg(Reg)); 2094 return MCDisassembler::Success; 2095 } 2096 2097 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2098 unsigned RegNo, 2099 uint64_t Address, 2100 const void *Decoder) { 2101 if (RegNo > 31) 2102 return MCDisassembler::Fail; 2103 2104 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2105 Inst.addOperand(MCOperand::createReg(Reg)); 2106 return MCDisassembler::Success; 2107 } 2108 2109 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2110 unsigned Offset, 2111 uint64_t Address, 2112 const void *Decoder) { 2113 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2114 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2115 return MCDisassembler::Success; 2116 } 2117 2118 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2119 unsigned Offset, 2120 uint64_t Address, 2121 const void *Decoder) { 2122 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2123 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2124 return MCDisassembler::Success; 2125 } 2126 2127 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2128 unsigned Insn, 2129 uint64_t Address, 2130 const void *Decoder) { 2131 2132 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2133 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2134 return MCDisassembler::Success; 2135 } 2136 2137 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2138 unsigned Offset, 2139 uint64_t Address, 2140 const void *Decoder) { 2141 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2142 2143 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2144 return MCDisassembler::Success; 2145 } 2146 2147 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2148 unsigned Offset, 2149 uint64_t Address, 2150 const void *Decoder) { 2151 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2152 2153 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2154 return MCDisassembler::Success; 2155 } 2156 2157 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2158 unsigned Offset, 2159 uint64_t Address, 2160 const void *Decoder) { 2161 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2162 2163 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2164 return MCDisassembler::Success; 2165 } 2166 2167 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2168 unsigned Offset, 2169 uint64_t Address, 2170 const void *Decoder) { 2171 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 2172 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2173 return MCDisassembler::Success; 2174 } 2175 2176 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2177 unsigned Offset, 2178 uint64_t Address, 2179 const void *Decoder) { 2180 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 2181 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2182 return MCDisassembler::Success; 2183 } 2184 2185 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2186 unsigned Offset, 2187 uint64_t Address, 2188 const void *Decoder) { 2189 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2190 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2191 return MCDisassembler::Success; 2192 } 2193 2194 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2195 unsigned Offset, 2196 uint64_t Address, 2197 const void *Decoder) { 2198 int32_t BranchOffset = SignExtend32<26>(Offset) << 1; 2199 2200 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2201 return MCDisassembler::Success; 2202 } 2203 2204 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2205 unsigned Insn, 2206 uint64_t Address, 2207 const void *Decoder) { 2208 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2209 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2210 return MCDisassembler::Success; 2211 } 2212 2213 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2214 unsigned Value, 2215 uint64_t Address, 2216 const void *Decoder) { 2217 if (Value == 0) 2218 Inst.addOperand(MCOperand::createImm(1)); 2219 else if (Value == 0x7) 2220 Inst.addOperand(MCOperand::createImm(-1)); 2221 else 2222 Inst.addOperand(MCOperand::createImm(Value << 2)); 2223 return MCDisassembler::Success; 2224 } 2225 2226 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2227 unsigned Value, 2228 uint64_t Address, 2229 const void *Decoder) { 2230 if (Value == 0x7F) 2231 Inst.addOperand(MCOperand::createImm(-1)); 2232 else 2233 Inst.addOperand(MCOperand::createImm(Value)); 2234 return MCDisassembler::Success; 2235 } 2236 2237 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2238 unsigned Value, 2239 uint64_t Address, 2240 const void *Decoder) { 2241 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2242 return MCDisassembler::Success; 2243 } 2244 2245 template <unsigned Bits, int Offset, int Scale> 2246 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2247 uint64_t Address, 2248 const void *Decoder) { 2249 Value &= ((1 << Bits) - 1); 2250 Value *= Scale; 2251 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2252 return MCDisassembler::Success; 2253 } 2254 2255 template <unsigned Bits, int Offset, int ScaleBy> 2256 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2257 uint64_t Address, 2258 const void *Decoder) { 2259 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2260 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2261 return MCDisassembler::Success; 2262 } 2263 2264 static DecodeStatus DecodeInsSize(MCInst &Inst, 2265 unsigned Insn, 2266 uint64_t Address, 2267 const void *Decoder) { 2268 // First we need to grab the pos(lsb) from MCInst. 2269 int Pos = Inst.getOperand(2).getImm(); 2270 int Size = (int) Insn - Pos + 1; 2271 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2272 return MCDisassembler::Success; 2273 } 2274 2275 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2276 uint64_t Address, const void *Decoder) { 2277 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2278 return MCDisassembler::Success; 2279 } 2280 2281 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2282 uint64_t Address, const void *Decoder) { 2283 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2284 return MCDisassembler::Success; 2285 } 2286 2287 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2288 uint64_t Address, const void *Decoder) { 2289 int32_t DecodedValue; 2290 switch (Insn) { 2291 case 0: DecodedValue = 256; break; 2292 case 1: DecodedValue = 257; break; 2293 case 510: DecodedValue = -258; break; 2294 case 511: DecodedValue = -257; break; 2295 default: DecodedValue = SignExtend32<9>(Insn); break; 2296 } 2297 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2298 return MCDisassembler::Success; 2299 } 2300 2301 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2302 uint64_t Address, const void *Decoder) { 2303 // Insn must be >= 0, since it is unsigned that condition is always true. 2304 assert(Insn < 16); 2305 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2306 255, 32768, 65535}; 2307 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2308 return MCDisassembler::Success; 2309 } 2310 2311 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2312 unsigned Insn, 2313 uint64_t Address, 2314 const void *Decoder) { 2315 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2316 Mips::S6, Mips::S7, Mips::FP}; 2317 unsigned RegNum; 2318 2319 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2320 2321 // Empty register lists are not allowed. 2322 if (RegLst == 0) 2323 return MCDisassembler::Fail; 2324 2325 RegNum = RegLst & 0xf; 2326 2327 // RegLst values 10-15, and 26-31 are reserved. 2328 if (RegNum > 9) 2329 return MCDisassembler::Fail; 2330 2331 for (unsigned i = 0; i < RegNum; i++) 2332 Inst.addOperand(MCOperand::createReg(Regs[i])); 2333 2334 if (RegLst & 0x10) 2335 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2336 2337 return MCDisassembler::Success; 2338 } 2339 2340 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2341 uint64_t Address, 2342 const void *Decoder) { 2343 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2344 unsigned RegLst; 2345 switch(Inst.getOpcode()) { 2346 default: 2347 RegLst = fieldFromInstruction(Insn, 4, 2); 2348 break; 2349 case Mips::LWM16_MMR6: 2350 case Mips::SWM16_MMR6: 2351 RegLst = fieldFromInstruction(Insn, 8, 2); 2352 break; 2353 } 2354 unsigned RegNum = RegLst & 0x3; 2355 2356 for (unsigned i = 0; i <= RegNum; i++) 2357 Inst.addOperand(MCOperand::createReg(Regs[i])); 2358 2359 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2360 2361 return MCDisassembler::Success; 2362 } 2363 2364 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, 2365 uint64_t Address, const void *Decoder) { 2366 2367 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2368 2369 switch (RegPair) { 2370 default: 2371 return MCDisassembler::Fail; 2372 case 0: 2373 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2374 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2375 break; 2376 case 1: 2377 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2378 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2379 break; 2380 case 2: 2381 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2382 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2383 break; 2384 case 3: 2385 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2386 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2387 break; 2388 case 4: 2389 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2390 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2391 break; 2392 case 5: 2393 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2394 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2395 break; 2396 case 6: 2397 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2398 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2399 break; 2400 case 7: 2401 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2402 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2403 break; 2404 } 2405 2406 return MCDisassembler::Success; 2407 } 2408 2409 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2410 uint64_t Address, const void *Decoder) { 2411 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2412 return MCDisassembler::Success; 2413 } 2414 2415 template <typename InsnType> 2416 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2417 uint64_t Address, 2418 const void *Decoder) { 2419 // We have: 2420 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2421 // Invalid if rt == 0 2422 // BGTZALC_MMR6 if rs == 0 && rt != 0 2423 // BLTZALC_MMR6 if rs != 0 && rs == rt 2424 // BLTUC_MMR6 if rs != 0 && rs != rt 2425 2426 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2427 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2428 InsnType Imm = 0; 2429 bool HasRs = false; 2430 bool HasRt = false; 2431 2432 if (Rt == 0) 2433 return MCDisassembler::Fail; 2434 else if (Rs == 0) { 2435 MI.setOpcode(Mips::BGTZALC_MMR6); 2436 HasRt = true; 2437 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2438 } 2439 else if (Rs == Rt) { 2440 MI.setOpcode(Mips::BLTZALC_MMR6); 2441 HasRs = true; 2442 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2443 } 2444 else { 2445 MI.setOpcode(Mips::BLTUC_MMR6); 2446 HasRs = true; 2447 HasRt = true; 2448 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2449 } 2450 2451 if (HasRs) 2452 MI.addOperand( 2453 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2454 2455 if (HasRt) 2456 MI.addOperand( 2457 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2458 2459 MI.addOperand(MCOperand::createImm(Imm)); 2460 2461 return MCDisassembler::Success; 2462 } 2463 2464 template <typename InsnType> 2465 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2466 uint64_t Address, 2467 const void *Decoder) { 2468 // We have: 2469 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2470 // Invalid if rt == 0 2471 // BLEZALC_MMR6 if rs == 0 && rt != 0 2472 // BGEZALC_MMR6 if rs == rt && rt != 0 2473 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2474 2475 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2476 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2477 InsnType Imm = 0; 2478 bool HasRs = false; 2479 2480 if (Rt == 0) 2481 return MCDisassembler::Fail; 2482 else if (Rs == 0) { 2483 MI.setOpcode(Mips::BLEZALC_MMR6); 2484 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2485 } 2486 else if (Rs == Rt) { 2487 MI.setOpcode(Mips::BGEZALC_MMR6); 2488 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2489 } 2490 else { 2491 HasRs = true; 2492 MI.setOpcode(Mips::BGEUC_MMR6); 2493 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2494 } 2495 2496 if (HasRs) 2497 MI.addOperand( 2498 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2499 MI.addOperand( 2500 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2501 2502 MI.addOperand(MCOperand::createImm(Imm)); 2503 2504 return MCDisassembler::Success; 2505 } 2506