1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/MipsMCTargetDesc.h" 15 #include "Mips.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCOP3() const { 67 // Only present in MIPS-I and MIPS-II 68 return !hasMips32() && !hasMips3(); 69 } 70 71 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 72 ArrayRef<uint8_t> Bytes, uint64_t Address, 73 raw_ostream &VStream, 74 raw_ostream &CStream) const override; 75 }; 76 77 } // end anonymous namespace 78 79 // Forward declare these because the autogenerated code will reference them. 80 // Definitions are further down. 81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 82 unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 86 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 97 unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 102 unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 106 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 107 unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 111 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 112 unsigned Insn, 113 uint64_t Address, 114 const void *Decoder); 115 116 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 117 unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 121 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 126 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 127 unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 131 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 132 unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder); 135 136 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 137 unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 141 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, 143 const void *Decoder); 144 145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 146 unsigned Insn, 147 uint64_t Address, 148 const void *Decoder); 149 150 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 151 unsigned RegNo, 152 uint64_t Address, 153 const void *Decoder); 154 155 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 156 unsigned RegNo, 157 uint64_t Address, 158 const void *Decoder); 159 160 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 161 unsigned RegNo, 162 uint64_t Address, 163 const void *Decoder); 164 165 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 170 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Address, 183 const void *Decoder); 184 185 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 186 unsigned RegNo, 187 uint64_t Address, 188 const void *Decoder); 189 190 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 191 unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 195 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Address, 198 const void *Decoder); 199 200 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 201 unsigned RegNo, 202 uint64_t Address, 203 const void *Decoder); 204 205 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 206 unsigned Offset, 207 uint64_t Address, 208 const void *Decoder); 209 210 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 211 unsigned Offset, 212 uint64_t Address, 213 const void *Decoder); 214 215 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 216 unsigned Insn, 217 uint64_t Address, 218 const void *Decoder); 219 220 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 221 unsigned Offset, 222 uint64_t Address, 223 const void *Decoder); 224 225 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 226 unsigned Offset, 227 uint64_t Address, 228 const void *Decoder); 229 230 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 231 unsigned Offset, 232 uint64_t Address, 233 const void *Decoder); 234 235 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 236 // shifted left by 1 bit. 237 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 238 unsigned Offset, 239 uint64_t Address, 240 const void *Decoder); 241 242 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 243 // shifted left by 1 bit. 244 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 245 unsigned Offset, 246 uint64_t Address, 247 const void *Decoder); 248 249 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 250 // shifted left by 1 bit. 251 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 252 unsigned Offset, 253 uint64_t Address, 254 const void *Decoder); 255 256 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 257 // shifted left by 1 bit. 258 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 259 unsigned Offset, 260 uint64_t Address, 261 const void *Decoder); 262 263 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 264 // shifted left by 1 bit. 265 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 266 unsigned Insn, 267 uint64_t Address, 268 const void *Decoder); 269 270 static DecodeStatus DecodeMem(MCInst &Inst, 271 unsigned Insn, 272 uint64_t Address, 273 const void *Decoder); 274 275 static DecodeStatus DecodeMemEVA(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 286 const void *Decoder); 287 288 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 289 unsigned Insn, 290 uint64_t Address, 291 const void *Decoder); 292 293 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 294 unsigned Insn, 295 uint64_t Address, 296 const void *Decoder); 297 298 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 299 unsigned Insn, 300 uint64_t Address, 301 const void *Decoder); 302 303 static DecodeStatus DecodeSyncI(MCInst &Inst, 304 unsigned Insn, 305 uint64_t Address, 306 const void *Decoder); 307 308 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, 309 unsigned Insn, 310 uint64_t Address, 311 const void *Decoder); 312 313 static DecodeStatus DecodeSynciR6(MCInst &Inst, 314 unsigned Insn, 315 uint64_t Address, 316 const void *Decoder); 317 318 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 321 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 322 unsigned Insn, 323 uint64_t Address, 324 const void *Decoder); 325 326 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 327 unsigned Insn, 328 uint64_t Address, 329 const void *Decoder); 330 331 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 332 unsigned Insn, 333 uint64_t Address, 334 const void *Decoder); 335 336 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 337 unsigned Insn, 338 uint64_t Address, 339 const void *Decoder); 340 341 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 342 unsigned Insn, 343 uint64_t Address, 344 const void *Decoder); 345 346 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 347 unsigned Insn, 348 uint64_t Address, 349 const void *Decoder); 350 351 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 352 unsigned Insn, 353 uint64_t Address, 354 const void *Decoder); 355 356 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 357 uint64_t Address, 358 const void *Decoder); 359 360 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 361 uint64_t Address, 362 const void *Decoder); 363 364 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 365 const void *Decoder); 366 367 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 368 const void *Decoder); 369 370 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 373 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 374 uint64_t Address, 375 const void *Decoder); 376 377 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 378 unsigned Insn, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 383 unsigned Value, 384 uint64_t Address, 385 const void *Decoder); 386 387 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 388 unsigned Value, 389 uint64_t Address, 390 const void *Decoder); 391 392 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 393 unsigned Value, 394 uint64_t Address, 395 const void *Decoder); 396 397 template <unsigned Bits, int Offset, int Scale> 398 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 399 uint64_t Address, 400 const void *Decoder); 401 402 template <unsigned Bits, int Offset> 403 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 404 uint64_t Address, 405 const void *Decoder) { 406 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 407 Decoder); 408 } 409 410 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 411 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 412 uint64_t Address, 413 const void *Decoder); 414 415 static DecodeStatus DecodeInsSize(MCInst &Inst, 416 unsigned Insn, 417 uint64_t Address, 418 const void *Decoder); 419 420 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 421 uint64_t Address, const void *Decoder); 422 423 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 424 uint64_t Address, const void *Decoder); 425 426 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void *Decoder); 428 429 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 430 uint64_t Address, const void *Decoder); 431 432 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 433 uint64_t Address, const void *Decoder); 434 435 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 436 /// handle. 437 template <typename InsnType> 438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 439 const void *Decoder); 440 441 template <typename InsnType> 442 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 443 const void *Decoder); 444 445 template <typename InsnType> 446 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 447 const void *Decoder); 448 449 template <typename InsnType> 450 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 451 const void *Decoder); 452 453 template <typename InsnType> 454 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 455 const void *Decoder); 456 457 template <typename InsnType> 458 static DecodeStatus 459 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 460 const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus 464 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 465 const void *Decoder); 466 467 template <typename InsnType> 468 static DecodeStatus 469 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 470 const void *Decoder); 471 472 template <typename InsnType> 473 static DecodeStatus 474 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 475 const void *Decoder); 476 477 template <typename InsnType> 478 static DecodeStatus 479 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 480 const void *Decoder); 481 482 template <typename InsnType> 483 static DecodeStatus 484 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 485 const void *Decoder); 486 487 template <typename InsnType> 488 static DecodeStatus 489 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 490 const void *Decoder); 491 492 template <typename InsnType> 493 static DecodeStatus 494 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 495 const void *Decoder); 496 497 template <typename InsnType> 498 static DecodeStatus 499 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 500 const void *Decoder); 501 502 template <typename InsnType> 503 static DecodeStatus 504 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 505 const void *Decoder); 506 507 template <typename InsnType> 508 static DecodeStatus 509 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 510 const void *Decoder); 511 512 template <typename InsnType> 513 static DecodeStatus 514 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 515 const void *Decoder); 516 517 template <typename InsnType> 518 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 519 const void *Decoder); 520 521 template <typename InsnType> 522 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 523 const void *Decoder); 524 525 template <typename InsnType> 526 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 527 const void *Decoder); 528 529 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 530 uint64_t Address, 531 const void *Decoder); 532 533 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 534 uint64_t Address, 535 const void *Decoder); 536 537 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 538 uint64_t Address, 539 const void *Decoder); 540 541 namespace llvm { 542 543 Target &getTheMipselTarget(); 544 Target &getTheMipsTarget(); 545 Target &getTheMips64Target(); 546 Target &getTheMips64elTarget(); 547 548 } // end namespace llvm 549 550 static MCDisassembler *createMipsDisassembler( 551 const Target &T, 552 const MCSubtargetInfo &STI, 553 MCContext &Ctx) { 554 return new MipsDisassembler(STI, Ctx, true); 555 } 556 557 static MCDisassembler *createMipselDisassembler( 558 const Target &T, 559 const MCSubtargetInfo &STI, 560 MCContext &Ctx) { 561 return new MipsDisassembler(STI, Ctx, false); 562 } 563 564 extern "C" void LLVMInitializeMipsDisassembler() { 565 // Register the disassembler. 566 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 567 createMipsDisassembler); 568 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 569 createMipselDisassembler); 570 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 571 createMipsDisassembler); 572 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 573 createMipselDisassembler); 574 } 575 576 #include "MipsGenDisassemblerTables.inc" 577 578 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 579 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 580 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 581 return *(RegInfo->getRegClass(RC).begin() + RegNo); 582 } 583 584 template <typename InsnType> 585 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 586 const void *Decoder) { 587 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 588 589 // The size of the n field depends on the element size 590 // The register class also depends on this. 591 InsnType tmp = fieldFromInstruction(insn, 17, 5); 592 unsigned NSize = 0; 593 DecodeFN RegDecoder = nullptr; 594 if ((tmp & 0x18) == 0x00) { // INSVE_B 595 NSize = 4; 596 RegDecoder = DecodeMSA128BRegisterClass; 597 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 598 NSize = 3; 599 RegDecoder = DecodeMSA128HRegisterClass; 600 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 601 NSize = 2; 602 RegDecoder = DecodeMSA128WRegisterClass; 603 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 604 NSize = 1; 605 RegDecoder = DecodeMSA128DRegisterClass; 606 } else 607 llvm_unreachable("Invalid encoding"); 608 609 assert(NSize != 0 && RegDecoder != nullptr); 610 611 // $wd 612 tmp = fieldFromInstruction(insn, 6, 5); 613 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 614 return MCDisassembler::Fail; 615 // $wd_in 616 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 617 return MCDisassembler::Fail; 618 // $n 619 tmp = fieldFromInstruction(insn, 16, NSize); 620 MI.addOperand(MCOperand::createImm(tmp)); 621 // $ws 622 tmp = fieldFromInstruction(insn, 11, 5); 623 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 624 return MCDisassembler::Fail; 625 // $n2 626 MI.addOperand(MCOperand::createImm(0)); 627 628 return MCDisassembler::Success; 629 } 630 631 template <typename InsnType> 632 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 633 const void *Decoder) { 634 InsnType Rs = fieldFromInstruction(insn, 16, 5); 635 InsnType Imm = fieldFromInstruction(insn, 0, 16); 636 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 637 Rs))); 638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 639 Rs))); 640 MI.addOperand(MCOperand::createImm(Imm)); 641 642 return MCDisassembler::Success; 643 } 644 645 template <typename InsnType> 646 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 647 const void *Decoder) { 648 InsnType Rs = fieldFromInstruction(insn, 21, 5); 649 InsnType Imm = fieldFromInstruction(insn, 0, 16); 650 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 651 Rs))); 652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 653 Rs))); 654 MI.addOperand(MCOperand::createImm(Imm)); 655 656 return MCDisassembler::Success; 657 } 658 659 template <typename InsnType> 660 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 661 uint64_t Address, 662 const void *Decoder) { 663 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 664 // (otherwise we would have matched the ADDI instruction from the earlier 665 // ISA's instead). 666 // 667 // We have: 668 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 669 // BOVC if rs >= rt 670 // BEQZALC if rs == 0 && rt != 0 671 // BEQC if rs < rt && rs != 0 672 673 InsnType Rs = fieldFromInstruction(insn, 21, 5); 674 InsnType Rt = fieldFromInstruction(insn, 16, 5); 675 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 676 bool HasRs = false; 677 678 if (Rs >= Rt) { 679 MI.setOpcode(Mips::BOVC); 680 HasRs = true; 681 } else if (Rs != 0 && Rs < Rt) { 682 MI.setOpcode(Mips::BEQC); 683 HasRs = true; 684 } else 685 MI.setOpcode(Mips::BEQZALC); 686 687 if (HasRs) 688 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 689 Rs))); 690 691 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 692 Rt))); 693 MI.addOperand(MCOperand::createImm(Imm)); 694 695 return MCDisassembler::Success; 696 } 697 698 template <typename InsnType> 699 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 700 uint64_t Address, 701 const void *Decoder) { 702 InsnType Rt = fieldFromInstruction(insn, 21, 5); 703 InsnType Rs = fieldFromInstruction(insn, 16, 5); 704 int64_t Imm = 0; 705 706 if (Rs >= Rt) { 707 MI.setOpcode(Mips::BOVC_MMR6); 708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 709 Rt))); 710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 711 Rs))); 712 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 713 } else if (Rs != 0 && Rs < Rt) { 714 MI.setOpcode(Mips::BEQC_MMR6); 715 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 716 Rs))); 717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 718 Rt))); 719 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 720 } else { 721 MI.setOpcode(Mips::BEQZALC_MMR6); 722 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 723 Rt))); 724 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 725 } 726 727 MI.addOperand(MCOperand::createImm(Imm)); 728 729 return MCDisassembler::Success; 730 } 731 732 template <typename InsnType> 733 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 734 uint64_t Address, 735 const void *Decoder) { 736 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 737 // (otherwise we would have matched the ADDI instruction from the earlier 738 // ISA's instead). 739 // 740 // We have: 741 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 742 // BNVC if rs >= rt 743 // BNEZALC if rs == 0 && rt != 0 744 // BNEC if rs < rt && rs != 0 745 746 InsnType Rs = fieldFromInstruction(insn, 21, 5); 747 InsnType Rt = fieldFromInstruction(insn, 16, 5); 748 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 749 bool HasRs = false; 750 751 if (Rs >= Rt) { 752 MI.setOpcode(Mips::BNVC); 753 HasRs = true; 754 } else if (Rs != 0 && Rs < Rt) { 755 MI.setOpcode(Mips::BNEC); 756 HasRs = true; 757 } else 758 MI.setOpcode(Mips::BNEZALC); 759 760 if (HasRs) 761 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 762 Rs))); 763 764 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 765 Rt))); 766 MI.addOperand(MCOperand::createImm(Imm)); 767 768 return MCDisassembler::Success; 769 } 770 771 template <typename InsnType> 772 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 773 uint64_t Address, 774 const void *Decoder) { 775 InsnType Rt = fieldFromInstruction(insn, 21, 5); 776 InsnType Rs = fieldFromInstruction(insn, 16, 5); 777 int64_t Imm = 0; 778 779 if (Rs >= Rt) { 780 MI.setOpcode(Mips::BNVC_MMR6); 781 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 782 Rt))); 783 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 784 Rs))); 785 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 786 } else if (Rs != 0 && Rs < Rt) { 787 MI.setOpcode(Mips::BNEC_MMR6); 788 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 789 Rs))); 790 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 791 Rt))); 792 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 793 } else { 794 MI.setOpcode(Mips::BNEZALC_MMR6); 795 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 796 Rt))); 797 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 798 } 799 800 MI.addOperand(MCOperand::createImm(Imm)); 801 802 return MCDisassembler::Success; 803 } 804 805 template <typename InsnType> 806 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 807 uint64_t Address, 808 const void *Decoder) { 809 // We have: 810 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 811 // Invalid if rt == 0 812 // BGTZC_MMR6 if rs == 0 && rt != 0 813 // BLTZC_MMR6 if rs == rt && rt != 0 814 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 815 816 InsnType Rt = fieldFromInstruction(insn, 21, 5); 817 InsnType Rs = fieldFromInstruction(insn, 16, 5); 818 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 819 bool HasRs = false; 820 821 if (Rt == 0) 822 return MCDisassembler::Fail; 823 else if (Rs == 0) 824 MI.setOpcode(Mips::BGTZC_MMR6); 825 else if (Rs == Rt) 826 MI.setOpcode(Mips::BLTZC_MMR6); 827 else { 828 MI.setOpcode(Mips::BLTC_MMR6); 829 HasRs = true; 830 } 831 832 if (HasRs) 833 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 834 Rs))); 835 836 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 837 Rt))); 838 839 MI.addOperand(MCOperand::createImm(Imm)); 840 841 return MCDisassembler::Success; 842 } 843 844 template <typename InsnType> 845 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 846 uint64_t Address, 847 const void *Decoder) { 848 // We have: 849 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 850 // Invalid if rt == 0 851 // BLEZC_MMR6 if rs == 0 && rt != 0 852 // BGEZC_MMR6 if rs == rt && rt != 0 853 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 854 855 InsnType Rt = fieldFromInstruction(insn, 21, 5); 856 InsnType Rs = fieldFromInstruction(insn, 16, 5); 857 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 858 bool HasRs = false; 859 860 if (Rt == 0) 861 return MCDisassembler::Fail; 862 else if (Rs == 0) 863 MI.setOpcode(Mips::BLEZC_MMR6); 864 else if (Rs == Rt) 865 MI.setOpcode(Mips::BGEZC_MMR6); 866 else { 867 HasRs = true; 868 MI.setOpcode(Mips::BGEC_MMR6); 869 } 870 871 if (HasRs) 872 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 873 Rs))); 874 875 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 876 Rt))); 877 878 MI.addOperand(MCOperand::createImm(Imm)); 879 880 return MCDisassembler::Success; 881 } 882 883 template <typename InsnType> 884 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 885 uint64_t Address, 886 const void *Decoder) { 887 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 888 // (otherwise we would have matched the BLEZL instruction from the earlier 889 // ISA's instead). 890 // 891 // We have: 892 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 893 // Invalid if rs == 0 894 // BLEZC if rs == 0 && rt != 0 895 // BGEZC if rs == rt && rt != 0 896 // BGEC if rs != rt && rs != 0 && rt != 0 897 898 InsnType Rs = fieldFromInstruction(insn, 21, 5); 899 InsnType Rt = fieldFromInstruction(insn, 16, 5); 900 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 901 bool HasRs = false; 902 903 if (Rt == 0) 904 return MCDisassembler::Fail; 905 else if (Rs == 0) 906 MI.setOpcode(Mips::BLEZC); 907 else if (Rs == Rt) 908 MI.setOpcode(Mips::BGEZC); 909 else { 910 HasRs = true; 911 MI.setOpcode(Mips::BGEC); 912 } 913 914 if (HasRs) 915 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 916 Rs))); 917 918 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 919 Rt))); 920 921 MI.addOperand(MCOperand::createImm(Imm)); 922 923 return MCDisassembler::Success; 924 } 925 926 template <typename InsnType> 927 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 928 uint64_t Address, 929 const void *Decoder) { 930 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 931 // (otherwise we would have matched the BGTZL instruction from the earlier 932 // ISA's instead). 933 // 934 // We have: 935 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 936 // Invalid if rs == 0 937 // BGTZC if rs == 0 && rt != 0 938 // BLTZC if rs == rt && rt != 0 939 // BLTC if rs != rt && rs != 0 && rt != 0 940 941 bool HasRs = false; 942 943 InsnType Rs = fieldFromInstruction(insn, 21, 5); 944 InsnType Rt = fieldFromInstruction(insn, 16, 5); 945 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 946 947 if (Rt == 0) 948 return MCDisassembler::Fail; 949 else if (Rs == 0) 950 MI.setOpcode(Mips::BGTZC); 951 else if (Rs == Rt) 952 MI.setOpcode(Mips::BLTZC); 953 else { 954 MI.setOpcode(Mips::BLTC); 955 HasRs = true; 956 } 957 958 if (HasRs) 959 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 960 Rs))); 961 962 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 963 Rt))); 964 965 MI.addOperand(MCOperand::createImm(Imm)); 966 967 return MCDisassembler::Success; 968 } 969 970 template <typename InsnType> 971 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 972 uint64_t Address, 973 const void *Decoder) { 974 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 975 // (otherwise we would have matched the BGTZ instruction from the earlier 976 // ISA's instead). 977 // 978 // We have: 979 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 980 // BGTZ if rt == 0 981 // BGTZALC if rs == 0 && rt != 0 982 // BLTZALC if rs != 0 && rs == rt 983 // BLTUC if rs != 0 && rs != rt 984 985 InsnType Rs = fieldFromInstruction(insn, 21, 5); 986 InsnType Rt = fieldFromInstruction(insn, 16, 5); 987 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 988 bool HasRs = false; 989 bool HasRt = false; 990 991 if (Rt == 0) { 992 MI.setOpcode(Mips::BGTZ); 993 HasRs = true; 994 } else if (Rs == 0) { 995 MI.setOpcode(Mips::BGTZALC); 996 HasRt = true; 997 } else if (Rs == Rt) { 998 MI.setOpcode(Mips::BLTZALC); 999 HasRs = true; 1000 } else { 1001 MI.setOpcode(Mips::BLTUC); 1002 HasRs = true; 1003 HasRt = true; 1004 } 1005 1006 if (HasRs) 1007 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1008 Rs))); 1009 1010 if (HasRt) 1011 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1012 Rt))); 1013 1014 MI.addOperand(MCOperand::createImm(Imm)); 1015 1016 return MCDisassembler::Success; 1017 } 1018 1019 template <typename InsnType> 1020 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1021 uint64_t Address, 1022 const void *Decoder) { 1023 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1024 // (otherwise we would have matched the BLEZL instruction from the earlier 1025 // ISA's instead). 1026 // 1027 // We have: 1028 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1029 // Invalid if rs == 0 1030 // BLEZALC if rs == 0 && rt != 0 1031 // BGEZALC if rs == rt && rt != 0 1032 // BGEUC if rs != rt && rs != 0 && rt != 0 1033 1034 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1035 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1036 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1037 bool HasRs = false; 1038 1039 if (Rt == 0) 1040 return MCDisassembler::Fail; 1041 else if (Rs == 0) 1042 MI.setOpcode(Mips::BLEZALC); 1043 else if (Rs == Rt) 1044 MI.setOpcode(Mips::BGEZALC); 1045 else { 1046 HasRs = true; 1047 MI.setOpcode(Mips::BGEUC); 1048 } 1049 1050 if (HasRs) 1051 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1052 Rs))); 1053 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1054 Rt))); 1055 1056 MI.addOperand(MCOperand::createImm(Imm)); 1057 1058 return MCDisassembler::Success; 1059 } 1060 1061 // Override the generated disassembler to produce DEXT all the time. This is 1062 // for feature / behaviour parity with binutils. 1063 template <typename InsnType> 1064 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1065 const void *Decoder) { 1066 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1067 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1068 unsigned Size = 0; 1069 unsigned Pos = 0; 1070 1071 switch (MI.getOpcode()) { 1072 case Mips::DEXT: 1073 Pos = Lsb; 1074 Size = Msbd + 1; 1075 break; 1076 case Mips::DEXTM: 1077 Pos = Lsb; 1078 Size = Msbd + 1 + 32; 1079 break; 1080 case Mips::DEXTU: 1081 Pos = Lsb + 32; 1082 Size = Msbd + 1; 1083 break; 1084 default: 1085 llvm_unreachable("Unknown DEXT instruction!"); 1086 } 1087 1088 MI.setOpcode(Mips::DEXT); 1089 1090 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1091 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1092 1093 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1094 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1095 MI.addOperand(MCOperand::createImm(Pos)); 1096 MI.addOperand(MCOperand::createImm(Size)); 1097 1098 return MCDisassembler::Success; 1099 } 1100 1101 // Override the generated disassembler to produce DINS all the time. This is 1102 // for feature / behaviour parity with binutils. 1103 template <typename InsnType> 1104 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1105 const void *Decoder) { 1106 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1107 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1108 unsigned Size = 0; 1109 unsigned Pos = 0; 1110 1111 switch (MI.getOpcode()) { 1112 case Mips::DINS: 1113 Pos = Lsb; 1114 Size = Msbd + 1 - Pos; 1115 break; 1116 case Mips::DINSM: 1117 Pos = Lsb; 1118 Size = Msbd + 33 - Pos; 1119 break; 1120 case Mips::DINSU: 1121 Pos = Lsb + 32; 1122 // mbsd = pos + size - 33 1123 // mbsd - pos + 33 = size 1124 Size = Msbd + 33 - Pos; 1125 break; 1126 default: 1127 llvm_unreachable("Unknown DINS instruction!"); 1128 } 1129 1130 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1131 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1132 1133 MI.setOpcode(Mips::DINS); 1134 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1135 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1136 MI.addOperand(MCOperand::createImm(Pos)); 1137 MI.addOperand(MCOperand::createImm(Size)); 1138 1139 return MCDisassembler::Success; 1140 } 1141 1142 // Auto-generated decoder wouldn't add the third operand for CRC32*. 1143 template <typename InsnType> 1144 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 1145 const void *Decoder) { 1146 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1147 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1148 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1149 Rt))); 1150 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1151 Rs))); 1152 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1153 Rt))); 1154 return MCDisassembler::Success; 1155 } 1156 1157 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1158 /// according to the given endianness. 1159 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1160 uint64_t &Size, uint32_t &Insn, 1161 bool IsBigEndian) { 1162 // We want to read exactly 2 Bytes of data. 1163 if (Bytes.size() < 2) { 1164 Size = 0; 1165 return MCDisassembler::Fail; 1166 } 1167 1168 if (IsBigEndian) { 1169 Insn = (Bytes[0] << 8) | Bytes[1]; 1170 } else { 1171 Insn = (Bytes[1] << 8) | Bytes[0]; 1172 } 1173 1174 return MCDisassembler::Success; 1175 } 1176 1177 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1178 /// according to the given endianness. 1179 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1180 uint64_t &Size, uint32_t &Insn, 1181 bool IsBigEndian, bool IsMicroMips) { 1182 // We want to read exactly 4 Bytes of data. 1183 if (Bytes.size() < 4) { 1184 Size = 0; 1185 return MCDisassembler::Fail; 1186 } 1187 1188 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1189 // always precede the low 16 bits in the instruction stream (that is, they 1190 // are placed at lower addresses in the instruction stream). 1191 // 1192 // microMIPS byte ordering: 1193 // Big-endian: 0 | 1 | 2 | 3 1194 // Little-endian: 1 | 0 | 3 | 2 1195 1196 if (IsBigEndian) { 1197 // Encoded as a big-endian 32-bit word in the stream. 1198 Insn = 1199 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1200 } else { 1201 if (IsMicroMips) { 1202 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1203 (Bytes[1] << 24); 1204 } else { 1205 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1206 (Bytes[3] << 24); 1207 } 1208 } 1209 1210 return MCDisassembler::Success; 1211 } 1212 1213 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1214 ArrayRef<uint8_t> Bytes, 1215 uint64_t Address, 1216 raw_ostream &VStream, 1217 raw_ostream &CStream) const { 1218 uint32_t Insn; 1219 DecodeStatus Result; 1220 Size = 0; 1221 1222 if (IsMicroMips) { 1223 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1224 if (Result == MCDisassembler::Fail) 1225 return MCDisassembler::Fail; 1226 1227 if (hasMips32r6()) { 1228 LLVM_DEBUG( 1229 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1230 // Calling the auto-generated decoder function for microMIPS32R6 1231 // 16-bit instructions. 1232 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1233 Address, this, STI); 1234 if (Result != MCDisassembler::Fail) { 1235 Size = 2; 1236 return Result; 1237 } 1238 } 1239 1240 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1241 // Calling the auto-generated decoder function for microMIPS 16-bit 1242 // instructions. 1243 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1244 this, STI); 1245 if (Result != MCDisassembler::Fail) { 1246 Size = 2; 1247 return Result; 1248 } 1249 1250 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1251 if (Result == MCDisassembler::Fail) 1252 return MCDisassembler::Fail; 1253 1254 if (hasMips32r6()) { 1255 LLVM_DEBUG( 1256 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1257 // Calling the auto-generated decoder function. 1258 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1259 this, STI); 1260 if (Result != MCDisassembler::Fail) { 1261 Size = 4; 1262 return Result; 1263 } 1264 } 1265 1266 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1267 // Calling the auto-generated decoder function. 1268 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1269 this, STI); 1270 if (Result != MCDisassembler::Fail) { 1271 Size = 4; 1272 return Result; 1273 } 1274 1275 if (isFP64()) { 1276 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1277 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1278 Address, this, STI); 1279 if (Result != MCDisassembler::Fail) { 1280 Size = 4; 1281 return Result; 1282 } 1283 } 1284 1285 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1286 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1287 // could form a valid instruction. The two bytes we rejected as an 1288 // instruction could have actually beeen an inline constant pool that is 1289 // unconditionally branched over. 1290 Size = 2; 1291 return MCDisassembler::Fail; 1292 } 1293 1294 // Attempt to read the instruction so that we can attempt to decode it. If 1295 // the buffer is not 4 bytes long, let the higher level logic figure out 1296 // what to do with a size of zero and MCDisassembler::Fail. 1297 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1298 if (Result == MCDisassembler::Fail) 1299 return MCDisassembler::Fail; 1300 1301 // The only instruction size for standard encoded MIPS. 1302 Size = 4; 1303 1304 if (hasCOP3()) { 1305 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1306 Result = 1307 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1308 if (Result != MCDisassembler::Fail) 1309 return Result; 1310 } 1311 1312 if (hasMips32r6() && isGP64()) { 1313 LLVM_DEBUG( 1314 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1315 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1316 Address, this, STI); 1317 if (Result != MCDisassembler::Fail) 1318 return Result; 1319 } 1320 1321 if (hasMips32r6() && isPTR64()) { 1322 LLVM_DEBUG( 1323 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1324 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1325 Address, this, STI); 1326 if (Result != MCDisassembler::Fail) 1327 return Result; 1328 } 1329 1330 if (hasMips32r6()) { 1331 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1332 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1333 Address, this, STI); 1334 if (Result != MCDisassembler::Fail) 1335 return Result; 1336 } 1337 1338 if (hasMips2() && isPTR64()) { 1339 LLVM_DEBUG( 1340 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1341 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1342 Address, this, STI); 1343 if (Result != MCDisassembler::Fail) 1344 return Result; 1345 } 1346 1347 if (hasCnMips()) { 1348 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1349 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1350 Address, this, STI); 1351 if (Result != MCDisassembler::Fail) 1352 return Result; 1353 } 1354 1355 if (isGP64()) { 1356 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1357 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1358 Address, this, STI); 1359 if (Result != MCDisassembler::Fail) 1360 return Result; 1361 } 1362 1363 if (isFP64()) { 1364 LLVM_DEBUG( 1365 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1366 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1367 Address, this, STI); 1368 if (Result != MCDisassembler::Fail) 1369 return Result; 1370 } 1371 1372 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1373 // Calling the auto-generated decoder function. 1374 Result = 1375 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1376 if (Result != MCDisassembler::Fail) 1377 return Result; 1378 1379 return MCDisassembler::Fail; 1380 } 1381 1382 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1383 unsigned RegNo, 1384 uint64_t Address, 1385 const void *Decoder) { 1386 return MCDisassembler::Fail; 1387 } 1388 1389 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1390 unsigned RegNo, 1391 uint64_t Address, 1392 const void *Decoder) { 1393 if (RegNo > 31) 1394 return MCDisassembler::Fail; 1395 1396 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1397 Inst.addOperand(MCOperand::createReg(Reg)); 1398 return MCDisassembler::Success; 1399 } 1400 1401 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1402 unsigned RegNo, 1403 uint64_t Address, 1404 const void *Decoder) { 1405 if (RegNo > 7) 1406 return MCDisassembler::Fail; 1407 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1408 Inst.addOperand(MCOperand::createReg(Reg)); 1409 return MCDisassembler::Success; 1410 } 1411 1412 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1413 unsigned RegNo, 1414 uint64_t Address, 1415 const void *Decoder) { 1416 if (RegNo > 7) 1417 return MCDisassembler::Fail; 1418 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1419 Inst.addOperand(MCOperand::createReg(Reg)); 1420 return MCDisassembler::Success; 1421 } 1422 1423 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1424 unsigned RegNo, 1425 uint64_t Address, 1426 const void *Decoder) { 1427 if (RegNo > 7) 1428 return MCDisassembler::Fail; 1429 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1430 Inst.addOperand(MCOperand::createReg(Reg)); 1431 return MCDisassembler::Success; 1432 } 1433 1434 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1435 unsigned RegNo, 1436 uint64_t Address, 1437 const void *Decoder) { 1438 if (RegNo > 31) 1439 return MCDisassembler::Fail; 1440 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1441 Inst.addOperand(MCOperand::createReg(Reg)); 1442 return MCDisassembler::Success; 1443 } 1444 1445 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1446 unsigned RegNo, 1447 uint64_t Address, 1448 const void *Decoder) { 1449 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1450 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1451 1452 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1453 } 1454 1455 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1456 unsigned RegNo, 1457 uint64_t Address, 1458 const void *Decoder) { 1459 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1460 } 1461 1462 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1463 unsigned RegNo, 1464 uint64_t Address, 1465 const void *Decoder) { 1466 if (RegNo > 31) 1467 return MCDisassembler::Fail; 1468 1469 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1470 Inst.addOperand(MCOperand::createReg(Reg)); 1471 return MCDisassembler::Success; 1472 } 1473 1474 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1475 unsigned RegNo, 1476 uint64_t Address, 1477 const void *Decoder) { 1478 if (RegNo > 31) 1479 return MCDisassembler::Fail; 1480 1481 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1482 Inst.addOperand(MCOperand::createReg(Reg)); 1483 return MCDisassembler::Success; 1484 } 1485 1486 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1487 unsigned RegNo, 1488 uint64_t Address, 1489 const void *Decoder) { 1490 if (RegNo > 31) 1491 return MCDisassembler::Fail; 1492 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1493 Inst.addOperand(MCOperand::createReg(Reg)); 1494 return MCDisassembler::Success; 1495 } 1496 1497 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1498 unsigned RegNo, 1499 uint64_t Address, 1500 const void *Decoder) { 1501 if (RegNo > 7) 1502 return MCDisassembler::Fail; 1503 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1504 Inst.addOperand(MCOperand::createReg(Reg)); 1505 return MCDisassembler::Success; 1506 } 1507 1508 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1509 uint64_t Address, 1510 const void *Decoder) { 1511 if (RegNo > 31) 1512 return MCDisassembler::Fail; 1513 1514 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1515 Inst.addOperand(MCOperand::createReg(Reg)); 1516 return MCDisassembler::Success; 1517 } 1518 1519 static DecodeStatus DecodeMem(MCInst &Inst, 1520 unsigned Insn, 1521 uint64_t Address, 1522 const void *Decoder) { 1523 int Offset = SignExtend32<16>(Insn & 0xffff); 1524 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1525 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1526 1527 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1528 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1529 1530 if (Inst.getOpcode() == Mips::SC || 1531 Inst.getOpcode() == Mips::SCD) 1532 Inst.addOperand(MCOperand::createReg(Reg)); 1533 1534 Inst.addOperand(MCOperand::createReg(Reg)); 1535 Inst.addOperand(MCOperand::createReg(Base)); 1536 Inst.addOperand(MCOperand::createImm(Offset)); 1537 1538 return MCDisassembler::Success; 1539 } 1540 1541 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1542 unsigned Insn, 1543 uint64_t Address, 1544 const void *Decoder) { 1545 int Offset = SignExtend32<9>(Insn >> 7); 1546 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1547 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1548 1549 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1550 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1551 1552 if (Inst.getOpcode() == Mips::SCE) 1553 Inst.addOperand(MCOperand::createReg(Reg)); 1554 1555 Inst.addOperand(MCOperand::createReg(Reg)); 1556 Inst.addOperand(MCOperand::createReg(Base)); 1557 Inst.addOperand(MCOperand::createImm(Offset)); 1558 1559 return MCDisassembler::Success; 1560 } 1561 1562 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1563 unsigned Insn, 1564 uint64_t Address, 1565 const void *Decoder) { 1566 int Offset = SignExtend32<16>(Insn & 0xffff); 1567 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1568 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1569 1570 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1571 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1572 1573 Inst.addOperand(MCOperand::createReg(Reg)); 1574 Inst.addOperand(MCOperand::createReg(Base)); 1575 Inst.addOperand(MCOperand::createImm(Offset)); 1576 1577 return MCDisassembler::Success; 1578 } 1579 1580 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1581 unsigned Insn, 1582 uint64_t Address, 1583 const void *Decoder) { 1584 int Offset = SignExtend32<16>(Insn & 0xffff); 1585 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1586 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1587 1588 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1589 1590 Inst.addOperand(MCOperand::createReg(Base)); 1591 Inst.addOperand(MCOperand::createImm(Offset)); 1592 Inst.addOperand(MCOperand::createImm(Hint)); 1593 1594 return MCDisassembler::Success; 1595 } 1596 1597 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1598 unsigned Insn, 1599 uint64_t Address, 1600 const void *Decoder) { 1601 int Offset = SignExtend32<12>(Insn & 0xfff); 1602 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1603 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1604 1605 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1606 1607 Inst.addOperand(MCOperand::createReg(Base)); 1608 Inst.addOperand(MCOperand::createImm(Offset)); 1609 Inst.addOperand(MCOperand::createImm(Hint)); 1610 1611 return MCDisassembler::Success; 1612 } 1613 1614 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1615 unsigned Insn, 1616 uint64_t Address, 1617 const void *Decoder) { 1618 int Offset = SignExtend32<9>(Insn & 0x1ff); 1619 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1620 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1621 1622 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1623 1624 Inst.addOperand(MCOperand::createReg(Base)); 1625 Inst.addOperand(MCOperand::createImm(Offset)); 1626 Inst.addOperand(MCOperand::createImm(Hint)); 1627 1628 return MCDisassembler::Success; 1629 } 1630 1631 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1632 unsigned Insn, 1633 uint64_t Address, 1634 const void *Decoder) { 1635 int Offset = SignExtend32<9>(Insn >> 7); 1636 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1637 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1638 1639 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1640 1641 Inst.addOperand(MCOperand::createReg(Base)); 1642 Inst.addOperand(MCOperand::createImm(Offset)); 1643 Inst.addOperand(MCOperand::createImm(Hint)); 1644 1645 return MCDisassembler::Success; 1646 } 1647 1648 static DecodeStatus DecodeSyncI(MCInst &Inst, 1649 unsigned Insn, 1650 uint64_t Address, 1651 const void *Decoder) { 1652 int Offset = SignExtend32<16>(Insn & 0xffff); 1653 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1654 1655 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1656 1657 Inst.addOperand(MCOperand::createReg(Base)); 1658 Inst.addOperand(MCOperand::createImm(Offset)); 1659 1660 return MCDisassembler::Success; 1661 } 1662 1663 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 1664 uint64_t Address, const void *Decoder) { 1665 int Offset = SignExtend32<16>(Insn & 0xffff); 1666 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1667 1668 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1669 1670 Inst.addOperand(MCOperand::createReg(Base)); 1671 Inst.addOperand(MCOperand::createImm(Offset)); 1672 1673 return MCDisassembler::Success; 1674 } 1675 1676 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1677 unsigned Insn, 1678 uint64_t Address, 1679 const void *Decoder) { 1680 int Immediate = SignExtend32<16>(Insn & 0xffff); 1681 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1682 1683 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1684 1685 Inst.addOperand(MCOperand::createReg(Base)); 1686 Inst.addOperand(MCOperand::createImm(Immediate)); 1687 1688 return MCDisassembler::Success; 1689 } 1690 1691 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1692 uint64_t Address, const void *Decoder) { 1693 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1694 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1695 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1696 1697 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1698 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1699 1700 Inst.addOperand(MCOperand::createReg(Reg)); 1701 Inst.addOperand(MCOperand::createReg(Base)); 1702 1703 // The immediate field of an LD/ST instruction is scaled which means it must 1704 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1705 // data format. 1706 // .b - 1 byte 1707 // .h - 2 bytes 1708 // .w - 4 bytes 1709 // .d - 8 bytes 1710 switch(Inst.getOpcode()) 1711 { 1712 default: 1713 assert(false && "Unexpected instruction"); 1714 return MCDisassembler::Fail; 1715 break; 1716 case Mips::LD_B: 1717 case Mips::ST_B: 1718 Inst.addOperand(MCOperand::createImm(Offset)); 1719 break; 1720 case Mips::LD_H: 1721 case Mips::ST_H: 1722 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1723 break; 1724 case Mips::LD_W: 1725 case Mips::ST_W: 1726 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1727 break; 1728 case Mips::LD_D: 1729 case Mips::ST_D: 1730 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1731 break; 1732 } 1733 1734 return MCDisassembler::Success; 1735 } 1736 1737 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1738 unsigned Insn, 1739 uint64_t Address, 1740 const void *Decoder) { 1741 unsigned Offset = Insn & 0xf; 1742 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1743 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1744 1745 switch (Inst.getOpcode()) { 1746 case Mips::LBU16_MM: 1747 case Mips::LHU16_MM: 1748 case Mips::LW16_MM: 1749 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1750 == MCDisassembler::Fail) 1751 return MCDisassembler::Fail; 1752 break; 1753 case Mips::SB16_MM: 1754 case Mips::SB16_MMR6: 1755 case Mips::SH16_MM: 1756 case Mips::SH16_MMR6: 1757 case Mips::SW16_MM: 1758 case Mips::SW16_MMR6: 1759 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1760 == MCDisassembler::Fail) 1761 return MCDisassembler::Fail; 1762 break; 1763 } 1764 1765 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1766 == MCDisassembler::Fail) 1767 return MCDisassembler::Fail; 1768 1769 switch (Inst.getOpcode()) { 1770 case Mips::LBU16_MM: 1771 if (Offset == 0xf) 1772 Inst.addOperand(MCOperand::createImm(-1)); 1773 else 1774 Inst.addOperand(MCOperand::createImm(Offset)); 1775 break; 1776 case Mips::SB16_MM: 1777 case Mips::SB16_MMR6: 1778 Inst.addOperand(MCOperand::createImm(Offset)); 1779 break; 1780 case Mips::LHU16_MM: 1781 case Mips::SH16_MM: 1782 case Mips::SH16_MMR6: 1783 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1784 break; 1785 case Mips::LW16_MM: 1786 case Mips::SW16_MM: 1787 case Mips::SW16_MMR6: 1788 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1789 break; 1790 } 1791 1792 return MCDisassembler::Success; 1793 } 1794 1795 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1796 unsigned Insn, 1797 uint64_t Address, 1798 const void *Decoder) { 1799 unsigned Offset = Insn & 0x1F; 1800 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1801 1802 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1803 1804 Inst.addOperand(MCOperand::createReg(Reg)); 1805 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1806 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1807 1808 return MCDisassembler::Success; 1809 } 1810 1811 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1812 unsigned Insn, 1813 uint64_t Address, 1814 const void *Decoder) { 1815 unsigned Offset = Insn & 0x7F; 1816 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1817 1818 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1819 1820 Inst.addOperand(MCOperand::createReg(Reg)); 1821 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1822 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1823 1824 return MCDisassembler::Success; 1825 } 1826 1827 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1828 unsigned Insn, 1829 uint64_t Address, 1830 const void *Decoder) { 1831 int Offset; 1832 switch (Inst.getOpcode()) { 1833 case Mips::LWM16_MMR6: 1834 case Mips::SWM16_MMR6: 1835 Offset = fieldFromInstruction(Insn, 4, 4); 1836 break; 1837 default: 1838 Offset = SignExtend32<4>(Insn & 0xf); 1839 break; 1840 } 1841 1842 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1843 == MCDisassembler::Fail) 1844 return MCDisassembler::Fail; 1845 1846 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1847 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1848 1849 return MCDisassembler::Success; 1850 } 1851 1852 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1853 unsigned Insn, 1854 uint64_t Address, 1855 const void *Decoder) { 1856 int Offset = SignExtend32<9>(Insn & 0x1ff); 1857 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1858 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1859 1860 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1861 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1862 1863 if (Inst.getOpcode() == Mips::SCE_MM) 1864 Inst.addOperand(MCOperand::createReg(Reg)); 1865 1866 Inst.addOperand(MCOperand::createReg(Reg)); 1867 Inst.addOperand(MCOperand::createReg(Base)); 1868 Inst.addOperand(MCOperand::createImm(Offset)); 1869 1870 return MCDisassembler::Success; 1871 } 1872 1873 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1874 unsigned Insn, 1875 uint64_t Address, 1876 const void *Decoder) { 1877 int Offset = SignExtend32<12>(Insn & 0x0fff); 1878 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1879 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1880 1881 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1882 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1883 1884 switch (Inst.getOpcode()) { 1885 case Mips::SWM32_MM: 1886 case Mips::LWM32_MM: 1887 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1888 == MCDisassembler::Fail) 1889 return MCDisassembler::Fail; 1890 Inst.addOperand(MCOperand::createReg(Base)); 1891 Inst.addOperand(MCOperand::createImm(Offset)); 1892 break; 1893 case Mips::SC_MM: 1894 Inst.addOperand(MCOperand::createReg(Reg)); 1895 LLVM_FALLTHROUGH; 1896 default: 1897 Inst.addOperand(MCOperand::createReg(Reg)); 1898 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || 1899 Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) 1900 Inst.addOperand(MCOperand::createReg(Reg+1)); 1901 1902 Inst.addOperand(MCOperand::createReg(Base)); 1903 Inst.addOperand(MCOperand::createImm(Offset)); 1904 } 1905 1906 return MCDisassembler::Success; 1907 } 1908 1909 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1910 unsigned Insn, 1911 uint64_t Address, 1912 const void *Decoder) { 1913 int Offset = SignExtend32<16>(Insn & 0xffff); 1914 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1915 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1916 1917 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1918 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1919 1920 Inst.addOperand(MCOperand::createReg(Reg)); 1921 Inst.addOperand(MCOperand::createReg(Base)); 1922 Inst.addOperand(MCOperand::createImm(Offset)); 1923 1924 return MCDisassembler::Success; 1925 } 1926 1927 static DecodeStatus DecodeFMem(MCInst &Inst, 1928 unsigned Insn, 1929 uint64_t Address, 1930 const void *Decoder) { 1931 int Offset = SignExtend32<16>(Insn & 0xffff); 1932 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1933 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1934 1935 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1936 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1937 1938 Inst.addOperand(MCOperand::createReg(Reg)); 1939 Inst.addOperand(MCOperand::createReg(Base)); 1940 Inst.addOperand(MCOperand::createImm(Offset)); 1941 1942 return MCDisassembler::Success; 1943 } 1944 1945 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1946 uint64_t Address, const void *Decoder) { 1947 // This function is the same as DecodeFMem but with the Reg and Base fields 1948 // swapped according to microMIPS spec. 1949 int Offset = SignExtend32<16>(Insn & 0xffff); 1950 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1951 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1952 1953 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1954 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1955 1956 Inst.addOperand(MCOperand::createReg(Reg)); 1957 Inst.addOperand(MCOperand::createReg(Base)); 1958 Inst.addOperand(MCOperand::createImm(Offset)); 1959 1960 return MCDisassembler::Success; 1961 } 1962 1963 static DecodeStatus DecodeFMem2(MCInst &Inst, 1964 unsigned Insn, 1965 uint64_t Address, 1966 const void *Decoder) { 1967 int Offset = SignExtend32<16>(Insn & 0xffff); 1968 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1969 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1970 1971 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1972 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1973 1974 Inst.addOperand(MCOperand::createReg(Reg)); 1975 Inst.addOperand(MCOperand::createReg(Base)); 1976 Inst.addOperand(MCOperand::createImm(Offset)); 1977 1978 return MCDisassembler::Success; 1979 } 1980 1981 static DecodeStatus DecodeFMem3(MCInst &Inst, 1982 unsigned Insn, 1983 uint64_t Address, 1984 const void *Decoder) { 1985 int Offset = SignExtend32<16>(Insn & 0xffff); 1986 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1987 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1988 1989 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1990 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1991 1992 Inst.addOperand(MCOperand::createReg(Reg)); 1993 Inst.addOperand(MCOperand::createReg(Base)); 1994 Inst.addOperand(MCOperand::createImm(Offset)); 1995 1996 return MCDisassembler::Success; 1997 } 1998 1999 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 2000 unsigned Insn, 2001 uint64_t Address, 2002 const void *Decoder) { 2003 int Offset = SignExtend32<11>(Insn & 0x07ff); 2004 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2005 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2006 2007 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2008 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2009 2010 Inst.addOperand(MCOperand::createReg(Reg)); 2011 Inst.addOperand(MCOperand::createReg(Base)); 2012 Inst.addOperand(MCOperand::createImm(Offset)); 2013 2014 return MCDisassembler::Success; 2015 } 2016 2017 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2018 uint64_t Address, const void *Decoder) { 2019 int Offset = SignExtend32<11>(Insn & 0x07ff); 2020 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2021 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2022 2023 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2024 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2025 2026 Inst.addOperand(MCOperand::createReg(Reg)); 2027 Inst.addOperand(MCOperand::createReg(Base)); 2028 Inst.addOperand(MCOperand::createImm(Offset)); 2029 2030 return MCDisassembler::Success; 2031 } 2032 2033 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2034 unsigned Insn, 2035 uint64_t Address, 2036 const void *Decoder) { 2037 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2038 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2039 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2040 2041 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2042 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2043 2044 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2045 Inst.addOperand(MCOperand::createReg(Rt)); 2046 } 2047 2048 Inst.addOperand(MCOperand::createReg(Rt)); 2049 Inst.addOperand(MCOperand::createReg(Base)); 2050 Inst.addOperand(MCOperand::createImm(Offset)); 2051 2052 return MCDisassembler::Success; 2053 } 2054 2055 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2056 unsigned RegNo, 2057 uint64_t Address, 2058 const void *Decoder) { 2059 // Currently only hardware register 29 is supported. 2060 if (RegNo != 29) 2061 return MCDisassembler::Fail; 2062 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2063 return MCDisassembler::Success; 2064 } 2065 2066 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2067 unsigned RegNo, 2068 uint64_t Address, 2069 const void *Decoder) { 2070 if (RegNo > 30 || RegNo %2) 2071 return MCDisassembler::Fail; 2072 2073 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2074 Inst.addOperand(MCOperand::createReg(Reg)); 2075 return MCDisassembler::Success; 2076 } 2077 2078 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2079 unsigned RegNo, 2080 uint64_t Address, 2081 const void *Decoder) { 2082 if (RegNo >= 4) 2083 return MCDisassembler::Fail; 2084 2085 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2086 Inst.addOperand(MCOperand::createReg(Reg)); 2087 return MCDisassembler::Success; 2088 } 2089 2090 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2091 unsigned RegNo, 2092 uint64_t Address, 2093 const void *Decoder) { 2094 if (RegNo >= 4) 2095 return MCDisassembler::Fail; 2096 2097 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2098 Inst.addOperand(MCOperand::createReg(Reg)); 2099 return MCDisassembler::Success; 2100 } 2101 2102 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2103 unsigned RegNo, 2104 uint64_t Address, 2105 const void *Decoder) { 2106 if (RegNo >= 4) 2107 return MCDisassembler::Fail; 2108 2109 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2110 Inst.addOperand(MCOperand::createReg(Reg)); 2111 return MCDisassembler::Success; 2112 } 2113 2114 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2115 unsigned RegNo, 2116 uint64_t Address, 2117 const void *Decoder) { 2118 if (RegNo > 31) 2119 return MCDisassembler::Fail; 2120 2121 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2122 Inst.addOperand(MCOperand::createReg(Reg)); 2123 return MCDisassembler::Success; 2124 } 2125 2126 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2127 unsigned RegNo, 2128 uint64_t Address, 2129 const void *Decoder) { 2130 if (RegNo > 31) 2131 return MCDisassembler::Fail; 2132 2133 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2134 Inst.addOperand(MCOperand::createReg(Reg)); 2135 return MCDisassembler::Success; 2136 } 2137 2138 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2139 unsigned RegNo, 2140 uint64_t Address, 2141 const void *Decoder) { 2142 if (RegNo > 31) 2143 return MCDisassembler::Fail; 2144 2145 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2146 Inst.addOperand(MCOperand::createReg(Reg)); 2147 return MCDisassembler::Success; 2148 } 2149 2150 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2151 unsigned RegNo, 2152 uint64_t Address, 2153 const void *Decoder) { 2154 if (RegNo > 31) 2155 return MCDisassembler::Fail; 2156 2157 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2158 Inst.addOperand(MCOperand::createReg(Reg)); 2159 return MCDisassembler::Success; 2160 } 2161 2162 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2163 unsigned RegNo, 2164 uint64_t Address, 2165 const void *Decoder) { 2166 if (RegNo > 7) 2167 return MCDisassembler::Fail; 2168 2169 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2170 Inst.addOperand(MCOperand::createReg(Reg)); 2171 return MCDisassembler::Success; 2172 } 2173 2174 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2175 unsigned RegNo, 2176 uint64_t Address, 2177 const void *Decoder) { 2178 if (RegNo > 31) 2179 return MCDisassembler::Fail; 2180 2181 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2182 Inst.addOperand(MCOperand::createReg(Reg)); 2183 return MCDisassembler::Success; 2184 } 2185 2186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2187 unsigned RegNo, 2188 uint64_t Address, 2189 const void *Decoder) { 2190 if (RegNo > 31) 2191 return MCDisassembler::Fail; 2192 2193 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2194 Inst.addOperand(MCOperand::createReg(Reg)); 2195 return MCDisassembler::Success; 2196 } 2197 2198 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2199 unsigned Offset, 2200 uint64_t Address, 2201 const void *Decoder) { 2202 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2203 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2204 return MCDisassembler::Success; 2205 } 2206 2207 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2208 unsigned Offset, 2209 uint64_t Address, 2210 const void *Decoder) { 2211 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2212 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2213 return MCDisassembler::Success; 2214 } 2215 2216 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2217 unsigned Insn, 2218 uint64_t Address, 2219 const void *Decoder) { 2220 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2221 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2222 return MCDisassembler::Success; 2223 } 2224 2225 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2226 unsigned Offset, 2227 uint64_t Address, 2228 const void *Decoder) { 2229 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2230 2231 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2232 return MCDisassembler::Success; 2233 } 2234 2235 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2236 unsigned Offset, 2237 uint64_t Address, 2238 const void *Decoder) { 2239 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2240 2241 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2242 return MCDisassembler::Success; 2243 } 2244 2245 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2246 unsigned Offset, 2247 uint64_t Address, 2248 const void *Decoder) { 2249 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2250 2251 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2252 return MCDisassembler::Success; 2253 } 2254 2255 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2256 unsigned Offset, 2257 uint64_t Address, 2258 const void *Decoder) { 2259 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2260 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2261 return MCDisassembler::Success; 2262 } 2263 2264 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2265 unsigned Offset, 2266 uint64_t Address, 2267 const void *Decoder) { 2268 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2269 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2270 return MCDisassembler::Success; 2271 } 2272 2273 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2274 unsigned Offset, 2275 uint64_t Address, 2276 const void *Decoder) { 2277 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2278 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2279 return MCDisassembler::Success; 2280 } 2281 2282 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2283 unsigned Offset, 2284 uint64_t Address, 2285 const void *Decoder) { 2286 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2287 2288 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2289 return MCDisassembler::Success; 2290 } 2291 2292 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2293 unsigned Insn, 2294 uint64_t Address, 2295 const void *Decoder) { 2296 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2297 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2298 return MCDisassembler::Success; 2299 } 2300 2301 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2302 unsigned Value, 2303 uint64_t Address, 2304 const void *Decoder) { 2305 if (Value == 0) 2306 Inst.addOperand(MCOperand::createImm(1)); 2307 else if (Value == 0x7) 2308 Inst.addOperand(MCOperand::createImm(-1)); 2309 else 2310 Inst.addOperand(MCOperand::createImm(Value << 2)); 2311 return MCDisassembler::Success; 2312 } 2313 2314 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2315 unsigned Value, 2316 uint64_t Address, 2317 const void *Decoder) { 2318 if (Value == 0x7F) 2319 Inst.addOperand(MCOperand::createImm(-1)); 2320 else 2321 Inst.addOperand(MCOperand::createImm(Value)); 2322 return MCDisassembler::Success; 2323 } 2324 2325 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2326 unsigned Value, 2327 uint64_t Address, 2328 const void *Decoder) { 2329 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2330 return MCDisassembler::Success; 2331 } 2332 2333 template <unsigned Bits, int Offset, int Scale> 2334 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2335 uint64_t Address, 2336 const void *Decoder) { 2337 Value &= ((1 << Bits) - 1); 2338 Value *= Scale; 2339 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2340 return MCDisassembler::Success; 2341 } 2342 2343 template <unsigned Bits, int Offset, int ScaleBy> 2344 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2345 uint64_t Address, 2346 const void *Decoder) { 2347 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2348 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2349 return MCDisassembler::Success; 2350 } 2351 2352 static DecodeStatus DecodeInsSize(MCInst &Inst, 2353 unsigned Insn, 2354 uint64_t Address, 2355 const void *Decoder) { 2356 // First we need to grab the pos(lsb) from MCInst. 2357 // This function only handles the 32 bit variants of ins, as dins 2358 // variants are handled differently. 2359 int Pos = Inst.getOperand(2).getImm(); 2360 int Size = (int) Insn - Pos + 1; 2361 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2362 return MCDisassembler::Success; 2363 } 2364 2365 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2366 uint64_t Address, const void *Decoder) { 2367 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2368 return MCDisassembler::Success; 2369 } 2370 2371 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2372 uint64_t Address, const void *Decoder) { 2373 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2374 return MCDisassembler::Success; 2375 } 2376 2377 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2378 uint64_t Address, const void *Decoder) { 2379 int32_t DecodedValue; 2380 switch (Insn) { 2381 case 0: DecodedValue = 256; break; 2382 case 1: DecodedValue = 257; break; 2383 case 510: DecodedValue = -258; break; 2384 case 511: DecodedValue = -257; break; 2385 default: DecodedValue = SignExtend32<9>(Insn); break; 2386 } 2387 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2388 return MCDisassembler::Success; 2389 } 2390 2391 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2392 uint64_t Address, const void *Decoder) { 2393 // Insn must be >= 0, since it is unsigned that condition is always true. 2394 assert(Insn < 16); 2395 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2396 255, 32768, 65535}; 2397 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2398 return MCDisassembler::Success; 2399 } 2400 2401 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2402 unsigned Insn, 2403 uint64_t Address, 2404 const void *Decoder) { 2405 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2406 Mips::S6, Mips::S7, Mips::FP}; 2407 unsigned RegNum; 2408 2409 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2410 2411 // Empty register lists are not allowed. 2412 if (RegLst == 0) 2413 return MCDisassembler::Fail; 2414 2415 RegNum = RegLst & 0xf; 2416 2417 // RegLst values 10-15, and 26-31 are reserved. 2418 if (RegNum > 9) 2419 return MCDisassembler::Fail; 2420 2421 for (unsigned i = 0; i < RegNum; i++) 2422 Inst.addOperand(MCOperand::createReg(Regs[i])); 2423 2424 if (RegLst & 0x10) 2425 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2426 2427 return MCDisassembler::Success; 2428 } 2429 2430 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2431 uint64_t Address, 2432 const void *Decoder) { 2433 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2434 unsigned RegLst; 2435 switch(Inst.getOpcode()) { 2436 default: 2437 RegLst = fieldFromInstruction(Insn, 4, 2); 2438 break; 2439 case Mips::LWM16_MMR6: 2440 case Mips::SWM16_MMR6: 2441 RegLst = fieldFromInstruction(Insn, 8, 2); 2442 break; 2443 } 2444 unsigned RegNum = RegLst & 0x3; 2445 2446 for (unsigned i = 0; i <= RegNum; i++) 2447 Inst.addOperand(MCOperand::createReg(Regs[i])); 2448 2449 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2450 2451 return MCDisassembler::Success; 2452 } 2453 2454 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2455 uint64_t Address, const void *Decoder) { 2456 switch (RegPair) { 2457 default: 2458 return MCDisassembler::Fail; 2459 case 0: 2460 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2461 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2462 break; 2463 case 1: 2464 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2465 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2466 break; 2467 case 2: 2468 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2469 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2470 break; 2471 case 3: 2472 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2473 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2474 break; 2475 case 4: 2476 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2477 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2478 break; 2479 case 5: 2480 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2481 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2482 break; 2483 case 6: 2484 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2485 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2486 break; 2487 case 7: 2488 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2489 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2490 break; 2491 } 2492 2493 return MCDisassembler::Success; 2494 } 2495 2496 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2497 uint64_t Address, const void *Decoder) { 2498 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2499 return MCDisassembler::Success; 2500 } 2501 2502 template <typename InsnType> 2503 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2504 uint64_t Address, 2505 const void *Decoder) { 2506 // We have: 2507 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2508 // Invalid if rt == 0 2509 // BGTZALC_MMR6 if rs == 0 && rt != 0 2510 // BLTZALC_MMR6 if rs != 0 && rs == rt 2511 // BLTUC_MMR6 if rs != 0 && rs != rt 2512 2513 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2514 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2515 InsnType Imm = 0; 2516 bool HasRs = false; 2517 bool HasRt = false; 2518 2519 if (Rt == 0) 2520 return MCDisassembler::Fail; 2521 else if (Rs == 0) { 2522 MI.setOpcode(Mips::BGTZALC_MMR6); 2523 HasRt = true; 2524 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2525 } 2526 else if (Rs == Rt) { 2527 MI.setOpcode(Mips::BLTZALC_MMR6); 2528 HasRs = true; 2529 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2530 } 2531 else { 2532 MI.setOpcode(Mips::BLTUC_MMR6); 2533 HasRs = true; 2534 HasRt = true; 2535 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2536 } 2537 2538 if (HasRs) 2539 MI.addOperand( 2540 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2541 2542 if (HasRt) 2543 MI.addOperand( 2544 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2545 2546 MI.addOperand(MCOperand::createImm(Imm)); 2547 2548 return MCDisassembler::Success; 2549 } 2550 2551 template <typename InsnType> 2552 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2553 uint64_t Address, 2554 const void *Decoder) { 2555 // We have: 2556 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2557 // Invalid if rt == 0 2558 // BLEZALC_MMR6 if rs == 0 && rt != 0 2559 // BGEZALC_MMR6 if rs == rt && rt != 0 2560 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2561 2562 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2563 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2564 InsnType Imm = 0; 2565 bool HasRs = false; 2566 2567 if (Rt == 0) 2568 return MCDisassembler::Fail; 2569 else if (Rs == 0) { 2570 MI.setOpcode(Mips::BLEZALC_MMR6); 2571 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2572 } 2573 else if (Rs == Rt) { 2574 MI.setOpcode(Mips::BGEZALC_MMR6); 2575 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2576 } 2577 else { 2578 HasRs = true; 2579 MI.setOpcode(Mips::BGEUC_MMR6); 2580 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2581 } 2582 2583 if (HasRs) 2584 MI.addOperand( 2585 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2586 MI.addOperand( 2587 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2588 2589 MI.addOperand(MCOperand::createImm(Imm)); 2590 2591 return MCDisassembler::Success; 2592 } 2593