1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 /// A disassembler class for Mips. 34 class MipsDisassemblerBase : public MCDisassembler { 35 public: 36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, 37 bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit), 40 IsBigEndian(IsBigEndian) {} 41 42 virtual ~MipsDisassemblerBase() {} 43 44 bool isGP64Bit() const { return IsGP64Bit; } 45 46 private: 47 bool IsGP64Bit; 48 protected: 49 bool IsBigEndian; 50 }; 51 52 /// A disassembler class for Mips32. 53 class MipsDisassembler : public MipsDisassemblerBase { 54 bool IsMicroMips; 55 public: 56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) 57 : MipsDisassemblerBase(STI, Ctx, bigEndian) { 58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; 59 } 60 61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; } 62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; } 63 bool hasMips32r6() const { 64 return STI.getFeatureBits() & Mips::FeatureMips32r6; 65 } 66 67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; } 68 69 bool hasCOP3() const { 70 // Only present in MIPS-I and MIPS-II 71 return !hasMips32() && !hasMips3(); 72 } 73 74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 75 ArrayRef<uint8_t> Bytes, uint64_t Address, 76 raw_ostream &VStream, 77 raw_ostream &CStream) const override; 78 }; 79 80 /// A disassembler class for Mips64. 81 class Mips64Disassembler : public MipsDisassemblerBase { 82 public: 83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 84 bool bigEndian) : 85 MipsDisassemblerBase(STI, Ctx, bigEndian) {} 86 87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 88 ArrayRef<uint8_t> Bytes, uint64_t Address, 89 raw_ostream &VStream, 90 raw_ostream &CStream) const override; 91 }; 92 93 } // end anonymous namespace 94 95 // Forward declare these because the autogenerated code will reference them. 96 // Definitions are further down. 97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 98 unsigned RegNo, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 123 unsigned Insn, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 128 unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 133 unsigned RegNo, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 143 unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 148 unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 157 unsigned Insn, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 192 unsigned RegNo, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 197 unsigned RegNo, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 202 unsigned RegNo, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 207 unsigned RegNo, 208 uint64_t Address, 209 const void *Decoder); 210 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 212 unsigned Offset, 213 uint64_t Address, 214 const void *Decoder); 215 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 217 unsigned Insn, 218 uint64_t Address, 219 const void *Decoder); 220 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 222 unsigned Offset, 223 uint64_t Address, 224 const void *Decoder); 225 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 227 unsigned Offset, 228 uint64_t Address, 229 const void *Decoder); 230 231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 232 // shifted left by 1 bit. 233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 234 unsigned Offset, 235 uint64_t Address, 236 const void *Decoder); 237 238 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 239 // shifted left by 1 bit. 240 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 241 unsigned Offset, 242 uint64_t Address, 243 const void *Decoder); 244 245 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 246 // shifted left by 1 bit. 247 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 248 unsigned Offset, 249 uint64_t Address, 250 const void *Decoder); 251 252 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 253 // shifted left by 1 bit. 254 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 255 unsigned Insn, 256 uint64_t Address, 257 const void *Decoder); 258 259 static DecodeStatus DecodeMem(MCInst &Inst, 260 unsigned Insn, 261 uint64_t Address, 262 const void *Decoder); 263 264 static DecodeStatus DecodeCacheOp(MCInst &Inst, 265 unsigned Insn, 266 uint64_t Address, 267 const void *Decoder); 268 269 static DecodeStatus DecodeCacheOpR6(MCInst &Inst, 270 unsigned Insn, 271 uint64_t Address, 272 const void *Decoder); 273 274 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 275 unsigned Insn, 276 uint64_t Address, 277 const void *Decoder); 278 279 static DecodeStatus DecodeSyncI(MCInst &Inst, 280 unsigned Insn, 281 uint64_t Address, 282 const void *Decoder); 283 284 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 287 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 288 unsigned Insn, 289 uint64_t Address, 290 const void *Decoder); 291 292 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 293 unsigned Insn, 294 uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 313 uint64_t Address, 314 const void *Decoder); 315 316 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 317 uint64_t Address, 318 const void *Decoder); 319 320 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 321 uint64_t Address, 322 const void *Decoder); 323 324 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 325 uint64_t Address, 326 const void *Decoder); 327 328 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 329 unsigned Insn, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 334 unsigned Value, 335 uint64_t Address, 336 const void *Decoder); 337 338 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 339 unsigned Value, 340 uint64_t Address, 341 const void *Decoder); 342 343 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 344 unsigned Value, 345 uint64_t Address, 346 const void *Decoder); 347 348 static DecodeStatus DecodeSimm4(MCInst &Inst, 349 unsigned Value, 350 uint64_t Address, 351 const void *Decoder); 352 353 static DecodeStatus DecodeSimm16(MCInst &Inst, 354 unsigned Insn, 355 uint64_t Address, 356 const void *Decoder); 357 358 // Decode the immediate field of an LSA instruction which 359 // is off by one. 360 static DecodeStatus DecodeLSAImm(MCInst &Inst, 361 unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeInsSize(MCInst &Inst, 366 unsigned Insn, 367 uint64_t Address, 368 const void *Decoder); 369 370 static DecodeStatus DecodeExtSize(MCInst &Inst, 371 unsigned Insn, 372 uint64_t Address, 373 const void *Decoder); 374 375 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 378 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 379 uint64_t Address, const void *Decoder); 380 381 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 384 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 385 uint64_t Address, const void *Decoder); 386 387 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 388 uint64_t Address, const void *Decoder); 389 390 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 391 uint64_t Address, const void *Decoder); 392 393 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 394 /// handle. 395 template <typename InsnType> 396 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 397 const void *Decoder); 398 399 template <typename InsnType> 400 static DecodeStatus 401 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 402 const void *Decoder); 403 404 template <typename InsnType> 405 static DecodeStatus 406 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 407 const void *Decoder); 408 409 template <typename InsnType> 410 static DecodeStatus 411 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 412 const void *Decoder); 413 414 template <typename InsnType> 415 static DecodeStatus 416 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 417 const void *Decoder); 418 419 template <typename InsnType> 420 static DecodeStatus 421 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 422 const void *Decoder); 423 424 template <typename InsnType> 425 static DecodeStatus 426 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 427 const void *Decoder); 428 429 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 430 uint64_t Address, 431 const void *Decoder); 432 433 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 434 uint64_t Address, 435 const void *Decoder); 436 437 namespace llvm { 438 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 439 TheMips64elTarget; 440 } 441 442 static MCDisassembler *createMipsDisassembler( 443 const Target &T, 444 const MCSubtargetInfo &STI, 445 MCContext &Ctx) { 446 return new MipsDisassembler(STI, Ctx, true); 447 } 448 449 static MCDisassembler *createMipselDisassembler( 450 const Target &T, 451 const MCSubtargetInfo &STI, 452 MCContext &Ctx) { 453 return new MipsDisassembler(STI, Ctx, false); 454 } 455 456 static MCDisassembler *createMips64Disassembler( 457 const Target &T, 458 const MCSubtargetInfo &STI, 459 MCContext &Ctx) { 460 return new Mips64Disassembler(STI, Ctx, true); 461 } 462 463 static MCDisassembler *createMips64elDisassembler( 464 const Target &T, 465 const MCSubtargetInfo &STI, 466 MCContext &Ctx) { 467 return new Mips64Disassembler(STI, Ctx, false); 468 } 469 470 extern "C" void LLVMInitializeMipsDisassembler() { 471 // Register the disassembler. 472 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 473 createMipsDisassembler); 474 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 475 createMipselDisassembler); 476 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 477 createMips64Disassembler); 478 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 479 createMips64elDisassembler); 480 } 481 482 #include "MipsGenDisassemblerTables.inc" 483 484 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 485 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); 486 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 487 return *(RegInfo->getRegClass(RC).begin() + RegNo); 488 } 489 490 template <typename InsnType> 491 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 492 const void *Decoder) { 493 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 494 // The size of the n field depends on the element size 495 // The register class also depends on this. 496 InsnType tmp = fieldFromInstruction(insn, 17, 5); 497 unsigned NSize = 0; 498 DecodeFN RegDecoder = nullptr; 499 if ((tmp & 0x18) == 0x00) { // INSVE_B 500 NSize = 4; 501 RegDecoder = DecodeMSA128BRegisterClass; 502 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 503 NSize = 3; 504 RegDecoder = DecodeMSA128HRegisterClass; 505 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 506 NSize = 2; 507 RegDecoder = DecodeMSA128WRegisterClass; 508 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 509 NSize = 1; 510 RegDecoder = DecodeMSA128DRegisterClass; 511 } else 512 llvm_unreachable("Invalid encoding"); 513 514 assert(NSize != 0 && RegDecoder != nullptr); 515 516 // $wd 517 tmp = fieldFromInstruction(insn, 6, 5); 518 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 519 return MCDisassembler::Fail; 520 // $wd_in 521 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 522 return MCDisassembler::Fail; 523 // $n 524 tmp = fieldFromInstruction(insn, 16, NSize); 525 MI.addOperand(MCOperand::CreateImm(tmp)); 526 // $ws 527 tmp = fieldFromInstruction(insn, 11, 5); 528 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 529 return MCDisassembler::Fail; 530 // $n2 531 MI.addOperand(MCOperand::CreateImm(0)); 532 533 return MCDisassembler::Success; 534 } 535 536 template <typename InsnType> 537 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 538 uint64_t Address, 539 const void *Decoder) { 540 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 541 // (otherwise we would have matched the ADDI instruction from the earlier 542 // ISA's instead). 543 // 544 // We have: 545 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 546 // BOVC if rs >= rt 547 // BEQZALC if rs == 0 && rt != 0 548 // BEQC if rs < rt && rs != 0 549 550 InsnType Rs = fieldFromInstruction(insn, 21, 5); 551 InsnType Rt = fieldFromInstruction(insn, 16, 5); 552 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 553 bool HasRs = false; 554 555 if (Rs >= Rt) { 556 MI.setOpcode(Mips::BOVC); 557 HasRs = true; 558 } else if (Rs != 0 && Rs < Rt) { 559 MI.setOpcode(Mips::BEQC); 560 HasRs = true; 561 } else 562 MI.setOpcode(Mips::BEQZALC); 563 564 if (HasRs) 565 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 566 Rs))); 567 568 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 569 Rt))); 570 MI.addOperand(MCOperand::CreateImm(Imm)); 571 572 return MCDisassembler::Success; 573 } 574 575 template <typename InsnType> 576 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 577 uint64_t Address, 578 const void *Decoder) { 579 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 580 // (otherwise we would have matched the ADDI instruction from the earlier 581 // ISA's instead). 582 // 583 // We have: 584 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 585 // BNVC if rs >= rt 586 // BNEZALC if rs == 0 && rt != 0 587 // BNEC if rs < rt && rs != 0 588 589 InsnType Rs = fieldFromInstruction(insn, 21, 5); 590 InsnType Rt = fieldFromInstruction(insn, 16, 5); 591 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 592 bool HasRs = false; 593 594 if (Rs >= Rt) { 595 MI.setOpcode(Mips::BNVC); 596 HasRs = true; 597 } else if (Rs != 0 && Rs < Rt) { 598 MI.setOpcode(Mips::BNEC); 599 HasRs = true; 600 } else 601 MI.setOpcode(Mips::BNEZALC); 602 603 if (HasRs) 604 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 605 Rs))); 606 607 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 608 Rt))); 609 MI.addOperand(MCOperand::CreateImm(Imm)); 610 611 return MCDisassembler::Success; 612 } 613 614 template <typename InsnType> 615 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 616 uint64_t Address, 617 const void *Decoder) { 618 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 619 // (otherwise we would have matched the BLEZL instruction from the earlier 620 // ISA's instead). 621 // 622 // We have: 623 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 624 // Invalid if rs == 0 625 // BLEZC if rs == 0 && rt != 0 626 // BGEZC if rs == rt && rt != 0 627 // BGEC if rs != rt && rs != 0 && rt != 0 628 629 InsnType Rs = fieldFromInstruction(insn, 21, 5); 630 InsnType Rt = fieldFromInstruction(insn, 16, 5); 631 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 632 bool HasRs = false; 633 634 if (Rt == 0) 635 return MCDisassembler::Fail; 636 else if (Rs == 0) 637 MI.setOpcode(Mips::BLEZC); 638 else if (Rs == Rt) 639 MI.setOpcode(Mips::BGEZC); 640 else { 641 HasRs = true; 642 MI.setOpcode(Mips::BGEC); 643 } 644 645 if (HasRs) 646 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 647 Rs))); 648 649 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 650 Rt))); 651 652 MI.addOperand(MCOperand::CreateImm(Imm)); 653 654 return MCDisassembler::Success; 655 } 656 657 template <typename InsnType> 658 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 659 uint64_t Address, 660 const void *Decoder) { 661 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 662 // (otherwise we would have matched the BGTZL instruction from the earlier 663 // ISA's instead). 664 // 665 // We have: 666 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 667 // Invalid if rs == 0 668 // BGTZC if rs == 0 && rt != 0 669 // BLTZC if rs == rt && rt != 0 670 // BLTC if rs != rt && rs != 0 && rt != 0 671 672 bool HasRs = false; 673 674 InsnType Rs = fieldFromInstruction(insn, 21, 5); 675 InsnType Rt = fieldFromInstruction(insn, 16, 5); 676 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 677 678 if (Rt == 0) 679 return MCDisassembler::Fail; 680 else if (Rs == 0) 681 MI.setOpcode(Mips::BGTZC); 682 else if (Rs == Rt) 683 MI.setOpcode(Mips::BLTZC); 684 else { 685 MI.setOpcode(Mips::BLTC); 686 HasRs = true; 687 } 688 689 if (HasRs) 690 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 691 Rs))); 692 693 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 694 Rt))); 695 696 MI.addOperand(MCOperand::CreateImm(Imm)); 697 698 return MCDisassembler::Success; 699 } 700 701 template <typename InsnType> 702 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 703 uint64_t Address, 704 const void *Decoder) { 705 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 706 // (otherwise we would have matched the BGTZ instruction from the earlier 707 // ISA's instead). 708 // 709 // We have: 710 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 711 // BGTZ if rt == 0 712 // BGTZALC if rs == 0 && rt != 0 713 // BLTZALC if rs != 0 && rs == rt 714 // BLTUC if rs != 0 && rs != rt 715 716 InsnType Rs = fieldFromInstruction(insn, 21, 5); 717 InsnType Rt = fieldFromInstruction(insn, 16, 5); 718 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 719 bool HasRs = false; 720 bool HasRt = false; 721 722 if (Rt == 0) { 723 MI.setOpcode(Mips::BGTZ); 724 HasRs = true; 725 } else if (Rs == 0) { 726 MI.setOpcode(Mips::BGTZALC); 727 HasRt = true; 728 } else if (Rs == Rt) { 729 MI.setOpcode(Mips::BLTZALC); 730 HasRs = true; 731 } else { 732 MI.setOpcode(Mips::BLTUC); 733 HasRs = true; 734 HasRt = true; 735 } 736 737 if (HasRs) 738 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 739 Rs))); 740 741 if (HasRt) 742 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 743 Rt))); 744 745 MI.addOperand(MCOperand::CreateImm(Imm)); 746 747 return MCDisassembler::Success; 748 } 749 750 template <typename InsnType> 751 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 752 uint64_t Address, 753 const void *Decoder) { 754 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 755 // (otherwise we would have matched the BLEZL instruction from the earlier 756 // ISA's instead). 757 // 758 // We have: 759 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 760 // Invalid if rs == 0 761 // BLEZALC if rs == 0 && rt != 0 762 // BGEZALC if rs == rt && rt != 0 763 // BGEUC if rs != rt && rs != 0 && rt != 0 764 765 InsnType Rs = fieldFromInstruction(insn, 21, 5); 766 InsnType Rt = fieldFromInstruction(insn, 16, 5); 767 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 768 bool HasRs = false; 769 770 if (Rt == 0) 771 return MCDisassembler::Fail; 772 else if (Rs == 0) 773 MI.setOpcode(Mips::BLEZALC); 774 else if (Rs == Rt) 775 MI.setOpcode(Mips::BGEZALC); 776 else { 777 HasRs = true; 778 MI.setOpcode(Mips::BGEUC); 779 } 780 781 if (HasRs) 782 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 783 Rs))); 784 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 785 Rt))); 786 787 MI.addOperand(MCOperand::CreateImm(Imm)); 788 789 return MCDisassembler::Success; 790 } 791 792 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 793 /// according to the given endianess. 794 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 795 uint64_t &Size, uint32_t &Insn, 796 bool IsBigEndian) { 797 // We want to read exactly 2 Bytes of data. 798 if (Bytes.size() < 2) { 799 Size = 0; 800 return MCDisassembler::Fail; 801 } 802 803 if (IsBigEndian) { 804 Insn = (Bytes[0] << 8) | Bytes[1]; 805 } else { 806 Insn = (Bytes[1] << 8) | Bytes[0]; 807 } 808 809 return MCDisassembler::Success; 810 } 811 812 /// Read four bytes from the ArrayRef and return 32 bit word sorted 813 /// according to the given endianess 814 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 815 uint64_t &Size, uint32_t &Insn, 816 bool IsBigEndian, bool IsMicroMips) { 817 // We want to read exactly 4 Bytes of data. 818 if (Bytes.size() < 4) { 819 Size = 0; 820 return MCDisassembler::Fail; 821 } 822 823 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 824 // always precede the low 16 bits in the instruction stream (that is, they 825 // are placed at lower addresses in the instruction stream). 826 // 827 // microMIPS byte ordering: 828 // Big-endian: 0 | 1 | 2 | 3 829 // Little-endian: 1 | 0 | 3 | 2 830 831 if (IsBigEndian) { 832 // Encoded as a big-endian 32-bit word in the stream. 833 Insn = 834 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 835 } else { 836 if (IsMicroMips) { 837 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 838 (Bytes[1] << 24); 839 } else { 840 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 841 (Bytes[3] << 24); 842 } 843 } 844 845 return MCDisassembler::Success; 846 } 847 848 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 849 ArrayRef<uint8_t> Bytes, 850 uint64_t Address, 851 raw_ostream &VStream, 852 raw_ostream &CStream) const { 853 uint32_t Insn; 854 DecodeStatus Result; 855 856 if (IsMicroMips) { 857 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 858 859 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 860 // Calling the auto-generated decoder function. 861 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 862 this, STI); 863 if (Result != MCDisassembler::Fail) { 864 Size = 2; 865 return Result; 866 } 867 868 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 869 if (Result == MCDisassembler::Fail) 870 return MCDisassembler::Fail; 871 872 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 873 // Calling the auto-generated decoder function. 874 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 875 this, STI); 876 if (Result != MCDisassembler::Fail) { 877 Size = 4; 878 return Result; 879 } 880 return MCDisassembler::Fail; 881 } 882 883 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 884 if (Result == MCDisassembler::Fail) 885 return MCDisassembler::Fail; 886 887 if (hasCOP3()) { 888 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 889 Result = 890 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 891 if (Result != MCDisassembler::Fail) { 892 Size = 4; 893 return Result; 894 } 895 } 896 897 if (hasMips32r6() && isGP64()) { 898 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 899 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 900 Address, this, STI); 901 if (Result != MCDisassembler::Fail) { 902 Size = 4; 903 return Result; 904 } 905 } 906 907 if (hasMips32r6()) { 908 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 909 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 910 Address, this, STI); 911 if (Result != MCDisassembler::Fail) { 912 Size = 4; 913 return Result; 914 } 915 } 916 917 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 918 // Calling the auto-generated decoder function. 919 Result = 920 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 921 if (Result != MCDisassembler::Fail) { 922 Size = 4; 923 return Result; 924 } 925 926 return MCDisassembler::Fail; 927 } 928 929 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size, 930 ArrayRef<uint8_t> Bytes, 931 uint64_t Address, 932 raw_ostream &VStream, 933 raw_ostream &CStream) const { 934 uint32_t Insn; 935 936 DecodeStatus Result = 937 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 938 if (Result == MCDisassembler::Fail) 939 return MCDisassembler::Fail; 940 941 // Calling the auto-generated decoder function. 942 Result = 943 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); 944 if (Result != MCDisassembler::Fail) { 945 Size = 4; 946 return Result; 947 } 948 // If we fail to decode in Mips64 decoder space we can try in Mips32 949 Result = 950 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 951 if (Result != MCDisassembler::Fail) { 952 Size = 4; 953 return Result; 954 } 955 956 return MCDisassembler::Fail; 957 } 958 959 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 960 unsigned RegNo, 961 uint64_t Address, 962 const void *Decoder) { 963 964 return MCDisassembler::Fail; 965 966 } 967 968 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 969 unsigned RegNo, 970 uint64_t Address, 971 const void *Decoder) { 972 973 if (RegNo > 31) 974 return MCDisassembler::Fail; 975 976 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 977 Inst.addOperand(MCOperand::CreateReg(Reg)); 978 return MCDisassembler::Success; 979 } 980 981 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 982 unsigned RegNo, 983 uint64_t Address, 984 const void *Decoder) { 985 if (RegNo > 7) 986 return MCDisassembler::Fail; 987 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 988 Inst.addOperand(MCOperand::CreateReg(Reg)); 989 return MCDisassembler::Success; 990 } 991 992 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 993 unsigned RegNo, 994 uint64_t Address, 995 const void *Decoder) { 996 if (RegNo > 7) 997 return MCDisassembler::Fail; 998 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 999 Inst.addOperand(MCOperand::CreateReg(Reg)); 1000 return MCDisassembler::Success; 1001 } 1002 1003 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1004 unsigned RegNo, 1005 uint64_t Address, 1006 const void *Decoder) { 1007 if (RegNo > 31) 1008 return MCDisassembler::Fail; 1009 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1010 Inst.addOperand(MCOperand::CreateReg(Reg)); 1011 return MCDisassembler::Success; 1012 } 1013 1014 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1015 unsigned RegNo, 1016 uint64_t Address, 1017 const void *Decoder) { 1018 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit()) 1019 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1020 1021 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1022 } 1023 1024 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1025 unsigned RegNo, 1026 uint64_t Address, 1027 const void *Decoder) { 1028 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1029 } 1030 1031 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1032 unsigned RegNo, 1033 uint64_t Address, 1034 const void *Decoder) { 1035 if (RegNo > 31) 1036 return MCDisassembler::Fail; 1037 1038 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1039 Inst.addOperand(MCOperand::CreateReg(Reg)); 1040 return MCDisassembler::Success; 1041 } 1042 1043 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1044 unsigned RegNo, 1045 uint64_t Address, 1046 const void *Decoder) { 1047 if (RegNo > 31) 1048 return MCDisassembler::Fail; 1049 1050 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1051 Inst.addOperand(MCOperand::CreateReg(Reg)); 1052 return MCDisassembler::Success; 1053 } 1054 1055 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1056 unsigned RegNo, 1057 uint64_t Address, 1058 const void *Decoder) { 1059 if (RegNo > 31) 1060 return MCDisassembler::Fail; 1061 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1062 Inst.addOperand(MCOperand::CreateReg(Reg)); 1063 return MCDisassembler::Success; 1064 } 1065 1066 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1067 unsigned RegNo, 1068 uint64_t Address, 1069 const void *Decoder) { 1070 if (RegNo > 7) 1071 return MCDisassembler::Fail; 1072 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1073 Inst.addOperand(MCOperand::CreateReg(Reg)); 1074 return MCDisassembler::Success; 1075 } 1076 1077 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1078 uint64_t Address, 1079 const void *Decoder) { 1080 if (RegNo > 31) 1081 return MCDisassembler::Fail; 1082 1083 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1084 Inst.addOperand(MCOperand::CreateReg(Reg)); 1085 return MCDisassembler::Success; 1086 } 1087 1088 static DecodeStatus DecodeMem(MCInst &Inst, 1089 unsigned Insn, 1090 uint64_t Address, 1091 const void *Decoder) { 1092 int Offset = SignExtend32<16>(Insn & 0xffff); 1093 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1094 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1095 1096 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1097 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1098 1099 if(Inst.getOpcode() == Mips::SC || 1100 Inst.getOpcode() == Mips::SCD){ 1101 Inst.addOperand(MCOperand::CreateReg(Reg)); 1102 } 1103 1104 Inst.addOperand(MCOperand::CreateReg(Reg)); 1105 Inst.addOperand(MCOperand::CreateReg(Base)); 1106 Inst.addOperand(MCOperand::CreateImm(Offset)); 1107 1108 return MCDisassembler::Success; 1109 } 1110 1111 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1112 unsigned Insn, 1113 uint64_t Address, 1114 const void *Decoder) { 1115 int Offset = SignExtend32<16>(Insn & 0xffff); 1116 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1117 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1118 1119 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1120 1121 Inst.addOperand(MCOperand::CreateReg(Base)); 1122 Inst.addOperand(MCOperand::CreateImm(Offset)); 1123 Inst.addOperand(MCOperand::CreateImm(Hint)); 1124 1125 return MCDisassembler::Success; 1126 } 1127 1128 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1129 unsigned Insn, 1130 uint64_t Address, 1131 const void *Decoder) { 1132 int Offset = SignExtend32<12>(Insn & 0xfff); 1133 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1134 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1135 1136 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1137 1138 Inst.addOperand(MCOperand::CreateReg(Base)); 1139 Inst.addOperand(MCOperand::CreateImm(Offset)); 1140 Inst.addOperand(MCOperand::CreateImm(Hint)); 1141 1142 return MCDisassembler::Success; 1143 } 1144 1145 static DecodeStatus DecodeCacheOpR6(MCInst &Inst, 1146 unsigned Insn, 1147 uint64_t Address, 1148 const void *Decoder) { 1149 int Offset = fieldFromInstruction(Insn, 7, 9); 1150 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1151 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1152 1153 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1154 1155 Inst.addOperand(MCOperand::CreateReg(Base)); 1156 Inst.addOperand(MCOperand::CreateImm(Offset)); 1157 Inst.addOperand(MCOperand::CreateImm(Hint)); 1158 1159 return MCDisassembler::Success; 1160 } 1161 1162 static DecodeStatus DecodeSyncI(MCInst &Inst, 1163 unsigned Insn, 1164 uint64_t Address, 1165 const void *Decoder) { 1166 int Offset = SignExtend32<16>(Insn & 0xffff); 1167 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1168 1169 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1170 1171 Inst.addOperand(MCOperand::CreateReg(Base)); 1172 Inst.addOperand(MCOperand::CreateImm(Offset)); 1173 1174 return MCDisassembler::Success; 1175 } 1176 1177 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1178 uint64_t Address, const void *Decoder) { 1179 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1180 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1181 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1182 1183 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1184 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1185 1186 Inst.addOperand(MCOperand::CreateReg(Reg)); 1187 Inst.addOperand(MCOperand::CreateReg(Base)); 1188 1189 // The immediate field of an LD/ST instruction is scaled which means it must 1190 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1191 // data format. 1192 // .b - 1 byte 1193 // .h - 2 bytes 1194 // .w - 4 bytes 1195 // .d - 8 bytes 1196 switch(Inst.getOpcode()) 1197 { 1198 default: 1199 assert (0 && "Unexpected instruction"); 1200 return MCDisassembler::Fail; 1201 break; 1202 case Mips::LD_B: 1203 case Mips::ST_B: 1204 Inst.addOperand(MCOperand::CreateImm(Offset)); 1205 break; 1206 case Mips::LD_H: 1207 case Mips::ST_H: 1208 Inst.addOperand(MCOperand::CreateImm(Offset * 2)); 1209 break; 1210 case Mips::LD_W: 1211 case Mips::ST_W: 1212 Inst.addOperand(MCOperand::CreateImm(Offset * 4)); 1213 break; 1214 case Mips::LD_D: 1215 case Mips::ST_D: 1216 Inst.addOperand(MCOperand::CreateImm(Offset * 8)); 1217 break; 1218 } 1219 1220 return MCDisassembler::Success; 1221 } 1222 1223 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1224 unsigned Insn, 1225 uint64_t Address, 1226 const void *Decoder) { 1227 unsigned Offset = Insn & 0xf; 1228 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1229 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1230 1231 switch (Inst.getOpcode()) { 1232 case Mips::LBU16_MM: 1233 case Mips::LHU16_MM: 1234 case Mips::LW16_MM: 1235 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1236 == MCDisassembler::Fail) 1237 return MCDisassembler::Fail; 1238 break; 1239 case Mips::SB16_MM: 1240 case Mips::SH16_MM: 1241 case Mips::SW16_MM: 1242 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1243 == MCDisassembler::Fail) 1244 return MCDisassembler::Fail; 1245 break; 1246 } 1247 1248 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1249 == MCDisassembler::Fail) 1250 return MCDisassembler::Fail; 1251 1252 switch (Inst.getOpcode()) { 1253 case Mips::LBU16_MM: 1254 if (Offset == 0xf) 1255 Inst.addOperand(MCOperand::CreateImm(-1)); 1256 else 1257 Inst.addOperand(MCOperand::CreateImm(Offset)); 1258 break; 1259 case Mips::SB16_MM: 1260 Inst.addOperand(MCOperand::CreateImm(Offset)); 1261 break; 1262 case Mips::LHU16_MM: 1263 case Mips::SH16_MM: 1264 Inst.addOperand(MCOperand::CreateImm(Offset << 1)); 1265 break; 1266 case Mips::LW16_MM: 1267 case Mips::SW16_MM: 1268 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1269 break; 1270 } 1271 1272 return MCDisassembler::Success; 1273 } 1274 1275 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1276 unsigned Insn, 1277 uint64_t Address, 1278 const void *Decoder) { 1279 unsigned Offset = Insn & 0x1F; 1280 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1281 1282 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1283 1284 Inst.addOperand(MCOperand::CreateReg(Reg)); 1285 Inst.addOperand(MCOperand::CreateReg(Mips::SP)); 1286 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1287 1288 return MCDisassembler::Success; 1289 } 1290 1291 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1292 unsigned Insn, 1293 uint64_t Address, 1294 const void *Decoder) { 1295 unsigned Offset = Insn & 0x7F; 1296 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1297 1298 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1299 1300 Inst.addOperand(MCOperand::CreateReg(Reg)); 1301 Inst.addOperand(MCOperand::CreateReg(Mips::GP)); 1302 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1303 1304 return MCDisassembler::Success; 1305 } 1306 1307 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1308 unsigned Insn, 1309 uint64_t Address, 1310 const void *Decoder) { 1311 int Offset = SignExtend32<12>(Insn & 0x0fff); 1312 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1313 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1314 1315 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1316 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1317 1318 switch (Inst.getOpcode()) { 1319 case Mips::SWM32_MM: 1320 case Mips::LWM32_MM: 1321 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1322 == MCDisassembler::Fail) 1323 return MCDisassembler::Fail; 1324 Inst.addOperand(MCOperand::CreateReg(Base)); 1325 Inst.addOperand(MCOperand::CreateImm(Offset)); 1326 break; 1327 case Mips::SC_MM: 1328 Inst.addOperand(MCOperand::CreateReg(Reg)); 1329 // fallthrough 1330 default: 1331 Inst.addOperand(MCOperand::CreateReg(Reg)); 1332 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1333 Inst.addOperand(MCOperand::CreateReg(Reg+1)); 1334 1335 Inst.addOperand(MCOperand::CreateReg(Base)); 1336 Inst.addOperand(MCOperand::CreateImm(Offset)); 1337 } 1338 1339 return MCDisassembler::Success; 1340 } 1341 1342 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1343 unsigned Insn, 1344 uint64_t Address, 1345 const void *Decoder) { 1346 int Offset = SignExtend32<16>(Insn & 0xffff); 1347 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1348 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1349 1350 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1351 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1352 1353 Inst.addOperand(MCOperand::CreateReg(Reg)); 1354 Inst.addOperand(MCOperand::CreateReg(Base)); 1355 Inst.addOperand(MCOperand::CreateImm(Offset)); 1356 1357 return MCDisassembler::Success; 1358 } 1359 1360 static DecodeStatus DecodeFMem(MCInst &Inst, 1361 unsigned Insn, 1362 uint64_t Address, 1363 const void *Decoder) { 1364 int Offset = SignExtend32<16>(Insn & 0xffff); 1365 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1366 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1367 1368 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1369 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1370 1371 Inst.addOperand(MCOperand::CreateReg(Reg)); 1372 Inst.addOperand(MCOperand::CreateReg(Base)); 1373 Inst.addOperand(MCOperand::CreateImm(Offset)); 1374 1375 return MCDisassembler::Success; 1376 } 1377 1378 static DecodeStatus DecodeFMem2(MCInst &Inst, 1379 unsigned Insn, 1380 uint64_t Address, 1381 const void *Decoder) { 1382 int Offset = SignExtend32<16>(Insn & 0xffff); 1383 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1384 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1385 1386 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1387 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1388 1389 Inst.addOperand(MCOperand::CreateReg(Reg)); 1390 Inst.addOperand(MCOperand::CreateReg(Base)); 1391 Inst.addOperand(MCOperand::CreateImm(Offset)); 1392 1393 return MCDisassembler::Success; 1394 } 1395 1396 static DecodeStatus DecodeFMem3(MCInst &Inst, 1397 unsigned Insn, 1398 uint64_t Address, 1399 const void *Decoder) { 1400 int Offset = SignExtend32<16>(Insn & 0xffff); 1401 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1402 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1403 1404 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1405 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1406 1407 Inst.addOperand(MCOperand::CreateReg(Reg)); 1408 Inst.addOperand(MCOperand::CreateReg(Base)); 1409 Inst.addOperand(MCOperand::CreateImm(Offset)); 1410 1411 return MCDisassembler::Success; 1412 } 1413 1414 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 1415 unsigned Insn, 1416 uint64_t Address, 1417 const void *Decoder) { 1418 int Offset = SignExtend32<11>(Insn & 0x07ff); 1419 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1420 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1421 1422 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1423 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1424 1425 Inst.addOperand(MCOperand::CreateReg(Reg)); 1426 Inst.addOperand(MCOperand::CreateReg(Base)); 1427 Inst.addOperand(MCOperand::CreateImm(Offset)); 1428 1429 return MCDisassembler::Success; 1430 } 1431 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1432 unsigned Insn, 1433 uint64_t Address, 1434 const void *Decoder) { 1435 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1436 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1437 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1438 1439 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1440 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1441 1442 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1443 Inst.addOperand(MCOperand::CreateReg(Rt)); 1444 } 1445 1446 Inst.addOperand(MCOperand::CreateReg(Rt)); 1447 Inst.addOperand(MCOperand::CreateReg(Base)); 1448 Inst.addOperand(MCOperand::CreateImm(Offset)); 1449 1450 return MCDisassembler::Success; 1451 } 1452 1453 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1454 unsigned RegNo, 1455 uint64_t Address, 1456 const void *Decoder) { 1457 // Currently only hardware register 29 is supported. 1458 if (RegNo != 29) 1459 return MCDisassembler::Fail; 1460 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); 1461 return MCDisassembler::Success; 1462 } 1463 1464 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1465 unsigned RegNo, 1466 uint64_t Address, 1467 const void *Decoder) { 1468 if (RegNo > 30 || RegNo %2) 1469 return MCDisassembler::Fail; 1470 1471 ; 1472 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1473 Inst.addOperand(MCOperand::CreateReg(Reg)); 1474 return MCDisassembler::Success; 1475 } 1476 1477 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1478 unsigned RegNo, 1479 uint64_t Address, 1480 const void *Decoder) { 1481 if (RegNo >= 4) 1482 return MCDisassembler::Fail; 1483 1484 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1485 Inst.addOperand(MCOperand::CreateReg(Reg)); 1486 return MCDisassembler::Success; 1487 } 1488 1489 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1490 unsigned RegNo, 1491 uint64_t Address, 1492 const void *Decoder) { 1493 if (RegNo >= 4) 1494 return MCDisassembler::Fail; 1495 1496 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1497 Inst.addOperand(MCOperand::CreateReg(Reg)); 1498 return MCDisassembler::Success; 1499 } 1500 1501 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1502 unsigned RegNo, 1503 uint64_t Address, 1504 const void *Decoder) { 1505 if (RegNo >= 4) 1506 return MCDisassembler::Fail; 1507 1508 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1509 Inst.addOperand(MCOperand::CreateReg(Reg)); 1510 return MCDisassembler::Success; 1511 } 1512 1513 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1514 unsigned RegNo, 1515 uint64_t Address, 1516 const void *Decoder) { 1517 if (RegNo > 31) 1518 return MCDisassembler::Fail; 1519 1520 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1521 Inst.addOperand(MCOperand::CreateReg(Reg)); 1522 return MCDisassembler::Success; 1523 } 1524 1525 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1526 unsigned RegNo, 1527 uint64_t Address, 1528 const void *Decoder) { 1529 if (RegNo > 31) 1530 return MCDisassembler::Fail; 1531 1532 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1533 Inst.addOperand(MCOperand::CreateReg(Reg)); 1534 return MCDisassembler::Success; 1535 } 1536 1537 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1538 unsigned RegNo, 1539 uint64_t Address, 1540 const void *Decoder) { 1541 if (RegNo > 31) 1542 return MCDisassembler::Fail; 1543 1544 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1545 Inst.addOperand(MCOperand::CreateReg(Reg)); 1546 return MCDisassembler::Success; 1547 } 1548 1549 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1550 unsigned RegNo, 1551 uint64_t Address, 1552 const void *Decoder) { 1553 if (RegNo > 31) 1554 return MCDisassembler::Fail; 1555 1556 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1557 Inst.addOperand(MCOperand::CreateReg(Reg)); 1558 return MCDisassembler::Success; 1559 } 1560 1561 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1562 unsigned RegNo, 1563 uint64_t Address, 1564 const void *Decoder) { 1565 if (RegNo > 7) 1566 return MCDisassembler::Fail; 1567 1568 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1569 Inst.addOperand(MCOperand::CreateReg(Reg)); 1570 return MCDisassembler::Success; 1571 } 1572 1573 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1574 unsigned RegNo, 1575 uint64_t Address, 1576 const void *Decoder) { 1577 if (RegNo > 31) 1578 return MCDisassembler::Fail; 1579 1580 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1581 Inst.addOperand(MCOperand::CreateReg(Reg)); 1582 return MCDisassembler::Success; 1583 } 1584 1585 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1586 unsigned Offset, 1587 uint64_t Address, 1588 const void *Decoder) { 1589 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1590 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1591 return MCDisassembler::Success; 1592 } 1593 1594 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1595 unsigned Insn, 1596 uint64_t Address, 1597 const void *Decoder) { 1598 1599 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1600 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1601 return MCDisassembler::Success; 1602 } 1603 1604 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1605 unsigned Offset, 1606 uint64_t Address, 1607 const void *Decoder) { 1608 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1609 1610 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1611 return MCDisassembler::Success; 1612 } 1613 1614 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1615 unsigned Offset, 1616 uint64_t Address, 1617 const void *Decoder) { 1618 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1619 1620 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1621 return MCDisassembler::Success; 1622 } 1623 1624 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1625 unsigned Offset, 1626 uint64_t Address, 1627 const void *Decoder) { 1628 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1629 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1630 return MCDisassembler::Success; 1631 } 1632 1633 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 1634 unsigned Offset, 1635 uint64_t Address, 1636 const void *Decoder) { 1637 int32_t BranchOffset = SignExtend32<10>(Offset) << 1; 1638 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1639 return MCDisassembler::Success; 1640 } 1641 1642 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1643 unsigned Offset, 1644 uint64_t Address, 1645 const void *Decoder) { 1646 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1647 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1648 return MCDisassembler::Success; 1649 } 1650 1651 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1652 unsigned Insn, 1653 uint64_t Address, 1654 const void *Decoder) { 1655 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1656 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1657 return MCDisassembler::Success; 1658 } 1659 1660 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1661 unsigned Value, 1662 uint64_t Address, 1663 const void *Decoder) { 1664 if (Value == 0) 1665 Inst.addOperand(MCOperand::CreateImm(1)); 1666 else if (Value == 0x7) 1667 Inst.addOperand(MCOperand::CreateImm(-1)); 1668 else 1669 Inst.addOperand(MCOperand::CreateImm(Value << 2)); 1670 return MCDisassembler::Success; 1671 } 1672 1673 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1674 unsigned Value, 1675 uint64_t Address, 1676 const void *Decoder) { 1677 Inst.addOperand(MCOperand::CreateImm(Value << 2)); 1678 return MCDisassembler::Success; 1679 } 1680 1681 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1682 unsigned Value, 1683 uint64_t Address, 1684 const void *Decoder) { 1685 if (Value == 0x7F) 1686 Inst.addOperand(MCOperand::CreateImm(-1)); 1687 else 1688 Inst.addOperand(MCOperand::CreateImm(Value)); 1689 return MCDisassembler::Success; 1690 } 1691 1692 static DecodeStatus DecodeSimm4(MCInst &Inst, 1693 unsigned Value, 1694 uint64_t Address, 1695 const void *Decoder) { 1696 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value))); 1697 return MCDisassembler::Success; 1698 } 1699 1700 static DecodeStatus DecodeSimm16(MCInst &Inst, 1701 unsigned Insn, 1702 uint64_t Address, 1703 const void *Decoder) { 1704 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); 1705 return MCDisassembler::Success; 1706 } 1707 1708 static DecodeStatus DecodeLSAImm(MCInst &Inst, 1709 unsigned Insn, 1710 uint64_t Address, 1711 const void *Decoder) { 1712 // We add one to the immediate field as it was encoded as 'imm - 1'. 1713 Inst.addOperand(MCOperand::CreateImm(Insn + 1)); 1714 return MCDisassembler::Success; 1715 } 1716 1717 static DecodeStatus DecodeInsSize(MCInst &Inst, 1718 unsigned Insn, 1719 uint64_t Address, 1720 const void *Decoder) { 1721 // First we need to grab the pos(lsb) from MCInst. 1722 int Pos = Inst.getOperand(2).getImm(); 1723 int Size = (int) Insn - Pos + 1; 1724 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1725 return MCDisassembler::Success; 1726 } 1727 1728 static DecodeStatus DecodeExtSize(MCInst &Inst, 1729 unsigned Insn, 1730 uint64_t Address, 1731 const void *Decoder) { 1732 int Size = (int) Insn + 1; 1733 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1734 return MCDisassembler::Success; 1735 } 1736 1737 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1738 uint64_t Address, const void *Decoder) { 1739 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4)); 1740 return MCDisassembler::Success; 1741 } 1742 1743 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1744 uint64_t Address, const void *Decoder) { 1745 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8)); 1746 return MCDisassembler::Success; 1747 } 1748 1749 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1750 uint64_t Address, const void *Decoder) { 1751 int32_t DecodedValue; 1752 switch (Insn) { 1753 case 0: DecodedValue = 256; break; 1754 case 1: DecodedValue = 257; break; 1755 case 510: DecodedValue = -258; break; 1756 case 511: DecodedValue = -257; break; 1757 default: DecodedValue = SignExtend32<9>(Insn); break; 1758 } 1759 Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4)); 1760 return MCDisassembler::Success; 1761 } 1762 1763 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1764 uint64_t Address, const void *Decoder) { 1765 // Insn must be >= 0, since it is unsigned that condition is always true. 1766 assert(Insn < 16); 1767 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1768 255, 32768, 65535}; 1769 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn])); 1770 return MCDisassembler::Success; 1771 } 1772 1773 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 1774 uint64_t Address, const void *Decoder) { 1775 Inst.addOperand(MCOperand::CreateImm(Insn << 2)); 1776 return MCDisassembler::Success; 1777 } 1778 1779 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 1780 unsigned Insn, 1781 uint64_t Address, 1782 const void *Decoder) { 1783 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 1784 Mips::S6, Mips::FP}; 1785 unsigned RegNum; 1786 1787 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 1788 // Empty register lists are not allowed. 1789 if (RegLst == 0) 1790 return MCDisassembler::Fail; 1791 1792 RegNum = RegLst & 0xf; 1793 for (unsigned i = 0; i < RegNum; i++) 1794 Inst.addOperand(MCOperand::CreateReg(Regs[i])); 1795 1796 if (RegLst & 0x10) 1797 Inst.addOperand(MCOperand::CreateReg(Mips::RA)); 1798 1799 return MCDisassembler::Success; 1800 } 1801 1802 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 1803 uint64_t Address, 1804 const void *Decoder) { 1805 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 1806 unsigned RegNum; 1807 1808 unsigned RegLst = fieldFromInstruction(Insn, 4, 2); 1809 // Empty register lists are not allowed. 1810 if (RegLst == 0) 1811 return MCDisassembler::Fail; 1812 1813 RegNum = RegLst & 0x3; 1814 for (unsigned i = 0; i < RegNum - 1; i++) 1815 Inst.addOperand(MCOperand::CreateReg(Regs[i])); 1816 1817 Inst.addOperand(MCOperand::CreateReg(Mips::RA)); 1818 1819 return MCDisassembler::Success; 1820 } 1821 1822 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 1823 uint64_t Address, const void *Decoder) { 1824 Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2)); 1825 return MCDisassembler::Success; 1826 } 1827